JP2808988B2 - Memory IC test system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor test apparatus,
In particular, it relates to a test system for a memory IC.

[0002]

2. Description of the Related Art In a conventional test system for a memory IC formed on a semiconductor substrate, a preliminary electrical test for replacing a defective cell portion of a memory IC with a redundant spare cell portion is first performed. To replace a defective cell portion of the memory IC with a spare cell portion, a selected fuse wiring on the memory IC is cut by a laser, an address of the defective cell portion is stored, and access to the defective cell portion is performed. The spare electrical test is performed by detecting the defective cell portion of each memory IC on the semiconductor substrate, and the redundant electrical portion is redundantly provided in the spare cell portion. The fuse wiring that needs to be cut off is selected, and at the same time, the number of non-defective ICs on each semiconductor substrate and I
The number of C is detected and output to a printer. Thereafter, the fuse wiring is cut by a laser, a final electrical test is performed, and the number of non-defective ICs on each semiconductor substrate is detected and output to a printer.

[0003] After the final electrical test is completed, a non-defective IC which is a test result of a preliminary electrical test output to a printer.
And the number of ICs requiring redundancy, and the number of non-defective ICs that are the test results of the final electrical test,
The redundancy rate of each semiconductor substrate is calculated. The redundancy ratio indicates a ratio of ICs determined to require redundancy in a preliminary electrical test to become non-defective ICs due to cutting of fuse wiring.

[0004]

However, in this conventional memory IC test system, the value of the test result of the preliminary electrical test output from the printer to monitor the redundancy success rate of the memory IC and the final Since the calculation is performed by comparing the value of the test result of the electrical test with each semiconductor substrate, there are problems that the number of man-hours increases and calculation errors easily occur.

[0005]

SUMMARY OF THE INVENTION The gist of the present invention is to provide an IC test apparatus and a prober for performing a preliminary electrical test for inspecting the necessity of replacing a defective circuit of a memory on a semiconductor substrate with a spare circuit. Test result of preliminary electrical test and test of final electrical test in a memory IC test system including an IC test apparatus and a prober for performing a final electrical test of a memory after performing a predetermined replacement process on a required memory A computer that collects the results, calculates the redundancy success rate of the memory on each semiconductor substrate based on the collected test results, and a communication cable that electrically connects these devices.

[0006]

When the preliminary electrical test is performed, the results are stored in the computer via a communication cable, and the results of the final electrical test are also sent to the computer via the communication cable. Therefore, the computer calculates the redundancy success rate.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a memory IC test system according to a first embodiment of the present invention. FIG. 2 is a flowchart showing the procedure of the computer. In this test system, the number of non-defective ICs and the number of ICs that require redundancy, which are the test results of the preliminary electric test of each semiconductor substrate, are transmitted from the preliminary electric test IC test apparatus 1 through the communication cable 6 to the computer 5. And store it in the storage medium of the computer 5.

Next, the fuse wiring of the IC requiring redundancy on the semiconductor substrate is cut by a laser so that the defective cell part can be replaced with a spare cell part.

After that, the number of non-defective ICs, which is the result of the final electrical test of each semiconductor substrate, is transferred to the computer 5 from the final electrical test IC test apparatus 3 through the communication cable 6. The computer 5 uses the number of non-defective ICs of the final electrical test received at this time, the number of non-defective ICs obtained in the preliminary electric test, and the number of ICs requiring redundancy as follows. Automatically calculate the redundancy rate. (Redundancy rate) = ｛(number of non-defective ICs in final electrical test) −
(Number of non-defective ICs in the preliminary electrical test) / (Number of ICs requiring redundancy) The redundancy rate calculated by the computer 5 is output to a printer after the final electrical test, and the technician determines the redundancy. Check the rate to see if the fuse wiring has been cut correctly.

[0010] When the redundancy rate is low, a technician investigates a device for cutting the fuse wiring and analyzes the failure of the memory IC. Therefore, manual calculations are not required, and production can be efficiently managed.

FIG. 3 is a block diagram showing a memory IC test system according to a second embodiment of the present invention, and FIG. 4 is a flowchart showing a processing procedure of the computer 5.

In this test system, the number of non-defective ICs as test results of the preliminary electrical test and the number of ICs requiring redundancy are
Are transferred from the prober 2 to the computer 5 and stored in a storage medium. After the fuse wiring is cut, the number of non-defective ICs in the final electrical test and the arrangement coordinates of the ICs on the semiconductor substrate are transferred from the prober 4 to the computer 5.
In addition to calculating the redundancy rate in the above, the arrangement coordinates of the memory IC on the semiconductor substrate which is determined to need redundancy in the preliminary electric test, and the arrangement coordinates of the memory IC which is not good in the final electric test. Are compared, and if there is the same arrangement coordinate, the arrangement coordinate is stored in the computer 5,
The printer outputs the redundancy rate together with the printer.

An engineer can examine the memory IC on the semiconductor substrate with reference to the arrangement coordinates and analyze the cause of the failure.

[0014]

As described above, according to the present invention, the test result of the preliminary electrical test is automatically stored in the computer through the communication cable, and the final electrical test result is also automatically stored in the computer through the communication cable. By transferring the data to a computer, the computer automatically calculates the redundancy rate of each semiconductor substrate, and outputs the result to a printer, a technician can quickly and regularly know the redundancy rate of each semiconductor substrate. As a result, the abnormality of the fuse wiring cutting device can be quickly and constantly monitored, and the abnormality of the IC can be promptly processed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing procedure of a computer according to the first embodiment.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a flowchart illustrating a processing procedure of a computer according to a second embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 spare electric test IC tester 2 prober 3 final electric test IC tester 4 prober 5 computer 6 communication cable

Continuation of the front page (51) Int.Cl. ⁶ identification code FI H01L 27/10 491 H01L 21/82 T G01R 31/28 B (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/82 G01R 31/26 G01R 31/28 G11C 29/00 303

Claims (1)

(57) [Claims] An IC test apparatus and a prober for performing a preliminary electrical test for inspecting the necessity of replacing a defective circuit of a memory on a semiconductor substrate with a spare circuit, and a predetermined replacement process for the memory that needs to be replaced The test result of the preliminary electric test and the test result of the final electric test are collected in the memory IC test system including the IC test apparatus and the prober for performing the final electric test of the memory after performing A memory IC test system, comprising: a computer for calculating a redundancy success rate of a memory on each semiconductor substrate based on a test result; and a communication cable for electrically connecting these devices.