JP2001165987A - Method for detecting disconnection of internal wiring of semiconductor device - Google Patents

Method for detecting disconnection of internal wiring of semiconductor device

Info

Publication number
JP2001165987A
JP2001165987A JP35183099A JP35183099A JP2001165987A JP 2001165987 A JP2001165987 A JP 2001165987A JP 35183099 A JP35183099 A JP 35183099A JP 35183099 A JP35183099 A JP 35183099A JP 2001165987 A JP2001165987 A JP 2001165987A
Authority
JP
Japan
Prior art keywords
disconnection
semiconductor chips
signal line
internal wiring
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP35183099A
Other languages
Japanese (ja)
Other versions
JP3979619B2 (en
Inventor
Katsuhiro Sawada
勝広 沢田
Kaneki Hirata
甲子己 平田
Takashi Tsubota
崇 坪田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP35183099A priority Critical patent/JP3979619B2/en
Publication of JP2001165987A publication Critical patent/JP2001165987A/en
Application granted granted Critical
Publication of JP3979619B2 publication Critical patent/JP3979619B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To provide a disconnection detection method for a semiconductor device of a multi-chip module or the like with a plurality of semiconductor chips mounted to the same package, whereby a disconnection of a signal line connected in common to the plurality of semiconductor chips can be detected simply. SOLUTION: According to the disconnection detection method for internal wiring, the disconnection of the signal line connected in common to the plurality of semiconductor chips 11 and 12 is detected for the semiconductor device, having the plurality of semiconductor chips 11 and 12 mounted in the same package 1. A constant current is impressed from a power source 6 for testing to an external terminal An, to which the signal line is connected. A terminal voltage VDF at the external terminal is measured and is compared with a terminal voltage of a good product, whereby the presence/absence of the disconnection of the signal line is detected.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は同一パッケージに複
数の半導体チップが搭載されたマルチチップモジュール
等の半導体装置の検査方法に係り、特に複数の半導体チ
ップに共通に接続されている信号線の断線を簡単に検出
することが可能な断線検出方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for testing a semiconductor device such as a multi-chip module in which a plurality of semiconductor chips are mounted on the same package, and more particularly, to disconnection of a signal line commonly connected to a plurality of semiconductor chips. And a disconnection detection method capable of easily detecting the disconnection.

【0002】マルチチップモジュール(以下MCMと略
称する)では同一パッケージの中に複数の半導体チップ
が搭載されており、それぞれの半導体チップの端子はワ
イヤや配線パターン等を介してパッケージに設けられた
外部端子に接続されている。
2. Description of the Related Art In a multi-chip module (hereinafter abbreviated as MCM), a plurality of semiconductor chips are mounted in the same package, and terminals of each semiconductor chip are connected to external parts provided in the package via wires, wiring patterns, and the like. Connected to terminal.

【0003】これらの配線の中にメモリのデータ線やア
ドレス線など複数の半導体チップに共通に接続されてい
る信号線が含まれ、共通に接続されている配線は片側の
半導体チップ側に通じる配線が断線してもMCMとして
の正常な動作が阻害される。
[0003] Among these wirings, signal lines commonly connected to a plurality of semiconductor chips, such as data lines and address lines of a memory, are included. Wirings commonly connected are wirings connected to one semiconductor chip. Is broken, the normal operation of the MCM is hindered.

【0004】したがって、配線の断線は確実に検出する
必要がありMCMの試験では全配線を対象に断線の有無
を確認しているが、従来の断線検出方法によるこのよう
な共通に接続されている信号線の断線検出は作業が複雑
で簡単に検出できなかった。
Therefore, it is necessary to reliably detect the disconnection of the wiring. In the MCM test, the presence or absence of the disconnection is checked for all the wirings. However, such common connection is performed by the conventional disconnection detecting method. The operation of detecting the disconnection of the signal line was complicated and could not be easily detected.

【0005】そこで複数の半導体チップに共通に接続さ
れた信号線の断線を簡単に検出できる断線検出方法の開
発が要望されている。
Therefore, there is a demand for the development of a disconnection detecting method capable of easily detecting a disconnection of a signal line commonly connected to a plurality of semiconductor chips.

【0006】[0006]

【従来の技術】図5は被測定デバイスの回路構成例を示
す図、図6は内部配線の断線例を示す図、図7は従来の
試験方法を示すフローチャートである。
2. Description of the Related Art FIG. 5 is a diagram showing an example of a circuit configuration of a device under test, FIG. 6 is a diagram showing an example of disconnection of internal wiring, and FIG. 7 is a flowchart showing a conventional test method.

【0007】図5において対象となる被測定デバイスは
同一パッケージ1内に複数(図では2個)の半導体チッ
プ11、12が搭載され、半導体チップ11、12の各端子はワ
イヤや配線パターン等を介しパッケージ1に設けられた
外部端子に接続されている。
In FIG. 5, a target device to be measured has a plurality of (two in the figure) semiconductor chips 11 and 12 mounted in the same package 1, and each terminal of the semiconductor chips 11 and 12 has a wire, a wiring pattern or the like. It is connected to an external terminal provided on the package 1 via the intermediary terminal.

【0008】即ち、外部端子A1 〜AX 、B1 〜BX
内部配線を介して半導体チップ11および半導体チップ12
の端子に接続され、場合により外部端子AZ 、BZ のよ
うにいずれか一方の半導体チップの端子に接続される外
部端子を有することもある。
Namely, the semiconductor chip 11 and the semiconductor chip 12 via an external terminal A 1 to A X, the B 1 .about.B X is internal wiring
Is connected to the terminal, if the sometimes having external terminals A Z, the external terminal connected to a terminal of one of the semiconductor chips as B Z.

【0009】このような被測定デバイスは半導体チップ
と内部配線の間がボンディングされたワイヤにより接続
されることが多く、例えば、モールディングされた樹脂
パッケージの中に封入する際等にワイヤに外力が印加さ
れ断線が生じることがある。
In such a device under test, the semiconductor chip and the internal wiring are often connected by a bonded wire. For example, an external force is applied to the wire when the device is sealed in a molded resin package. Disconnection may occur.

【0010】その結果、図6に示す如く外部端子A1
接続される半導体チップ11の端子と内部配線との間に断
線13が発生すると、外部端子A1 と半導体チップ12を接
続する配線に断線が無くても被測定デバイスの正常な動
作が阻害される場合がある。
As a result, as shown in FIG. 6, when a disconnection 13 occurs between the terminal of the semiconductor chip 11 connected to the external terminal A 1 and the internal wiring, the wiring connecting the external terminal A 1 and the semiconductor chip 12 is disconnected. Even if there is no disconnection, the normal operation of the device under test may be hindered.

【0011】そこで従来は個々の半導体チップを単独で
動作させ全ての内部配線をアクティブ化すると共に、外
部端子にそれぞれ試験信号を印加したときの出力信号等
を検知することで、ワイヤ等の接続部を含む全ての内部
配線の断線を検出している。
Therefore, conventionally, individual semiconductor chips are operated independently to activate all internal wirings, and at the same time, by detecting output signals when test signals are applied to external terminals, connection portions such as wires are connected. Disconnection of all the internal wirings including.

【0012】即ち、図7に示す如く被測定デバイスを測
定装置のソケット等にセットして、被測定デバイスのチ
ップセレクト線を選択することで、最初の半導体チッ
プ、例えば半導体チップ11が動作して関連する全ての内
部配線がアクティブ化される。
That is, as shown in FIG. 7, a device to be measured is set in a socket or the like of a measuring device and a chip select line of the device to be measured is selected, so that the first semiconductor chip, for example, the semiconductor chip 11 operates. All relevant internal wiring is activated.

【0013】被測定デバイスは1個の半導体チップが動
作状態にあるとき関連する外部端子A1 〜AX に試験信
号が印加されると、印加された試験信号のHレベルまた
はLレベルに対応して半導体チップの出力信号、例えば
B信号のレベルが変化する。
[0013] DUT corresponds to H level or L level of the associated the test signal to an external terminal A 1 to A X is applied, the applied test signal when one of the semiconductor chip is in operation Thus, the output signal of the semiconductor chip, for example, the level of the B signal changes.

【0014】また、外部端子A1 〜AX に印加される試
験信号に代え、動作状態にある半導体チップに対し制御
信号、例えばC信号が印加されると、印加されたC信号
のHレベルまたはLレベルに対応して外部端子A1 〜A
X の電圧レベルが変化する。
When a control signal, for example, a C signal is applied to the operating semiconductor chip instead of the test signal applied to the external terminals A 1 -A X , the H level of the applied C signal or External terminals A 1 to A corresponding to the L level
The voltage level of X changes.

【0015】しかし、外部端子A1 〜AX に接続されて
いる内部配線に断線が生じている場合は、外部端子A1
〜AX に試験信号が印加されてもB信号が変化せず、半
導体チップにC信号が印加されても外部端子A1 〜AX
の電圧レベルが変化しない。
However, if the internal wiring connected to the external terminals A 1 to A X is broken, the external terminal A 1
Even test signal is applied to to A X without B signals changes, the external terminals A 1 to A X be C signal is applied to the semiconductor chip
Voltage level does not change.

【0016】したがって、図示の如く外部端子An に試
験信号を印加してB信号が期待通りであるか確認し、半
導体チップにC信号を印加し外部端子An の電圧レベ
ル、即ちAn 信号が期待通りであるか確認することによ
って良品と不良を判別できる。
[0016] Thus, to see if B signal by applying a test signal to an external terminal A n as shown is expected, the voltage level of the external terminals A n applies the C signal to the semiconductor chip, i.e. A n signal Can be discriminated as a good product or a defective product by confirming that the product is as expected.

【0017】なお、被測定デバイスには図5に示す如く
外部端子A1 〜AX の他に外部端子B1 〜BX があり、
図7には記載されていないが、外部端子A1 〜AX に接
続される内部配線と同様に外部端子B1 〜BX に接続さ
れる内部配線も試験される。
[0017] Note that the device under test there are other outside terminal B 1 .about.B X external terminals A 1 to A X as shown in FIG. 5,
Although not described in FIG. 7, the internal wiring connected to the external terminals A 1 Similarly external terminal and internal wiring connected to ~A X B 1 ~B X are also tested.

【0018】[0018]

【発明が解決しようとする課題】しかし、被測定デバイ
スの回路構成によっては搭載された半導体チップを個々
に動作させることが不可能な場合があり、この場合は半
導体チップを順次動作状態にして内部配線の断線の有無
を検出する従来の断線検出方法は適用できない。
However, depending on the circuit configuration of the device under test, it may not be possible to individually operate the mounted semiconductor chips. In this case, the semiconductor chips are sequentially operated and the internal chips are not operated. The conventional disconnection detection method for detecting the presence / absence of disconnection of the wiring cannot be applied.

【0019】また、図7に示す如く半導体チップを個々
に動作させて、外部端子A1 〜AXに試験信号を印加
し、次いで半導体チップに対してC信号を印加し、この
作業を全ての外部端子を対象として繰り返し遂行する必
要があり試験に時間がかかる。
Further, by individually operating the semiconductor chip as shown in FIG. 7, a test signal is applied to the external terminals A 1 to A X, then the C signal is applied to the semiconductor chip, all this work The test needs to be repeatedly performed for the external terminals, and the test takes time.

【0020】しかも、従来の試験方法において不良と判
定された場合に、半導体チップ自体の不良に起因するも
のなのか、或いは内部配線の断線等に起因するものなの
かが不明であり、不良になった原因の解析が極めて困難
であるという問題があった。
In addition, when it is determined that the semiconductor device is defective in the conventional test method, it is unclear whether the defect is caused by a defect of the semiconductor chip itself or a disconnection of the internal wiring. There is a problem that it is extremely difficult to analyze the cause.

【0021】本発明の目的は複数の半導体チップに共通
に接続された信号線の断線を簡単に検出できる断線検出
方法を提供することにある。
An object of the present invention is to provide a disconnection detecting method capable of easily detecting a disconnection of a signal line commonly connected to a plurality of semiconductor chips.

【0022】[0022]

【課題を解決するための手段】図1は本発明になる断線
検出方法を示す原理図である。なお全図を通し同じ対象
物は同一記号で表している。
FIG. 1 is a principle diagram showing a disconnection detecting method according to the present invention. The same object is denoted by the same symbol throughout the drawings.

【0023】上記課題は同一パッケージ1の中に複数の
半導体チップ11、12が搭載されている半導体装置を対象
として、複数の半導体チップ11、12に共通に接続された
信号線の断線を検出する断線検出方法であって、信号線
が接続された外部端子An に試験用電源6から定電流を
印加すると共に、外部端子における端子電圧VDFを測
定し、良品の半導体装置における端子電圧と比較するこ
とによって、信号線の断線の有無を検出する半導体装置
の内部配線断線検出方法により達成される。
The object is to detect a disconnection of a signal line commonly connected to a plurality of semiconductor chips 11, 12 for a semiconductor device having a plurality of semiconductor chips 11, 12 mounted in the same package 1. a disconnection detection method, the signal line applies a constant current from the test power supply 6 to the connected external terminals a n, measured terminal voltage VDF of the external terminal, is compared with the terminal voltage of the semiconductor device of good This is achieved by a method for detecting disconnection of internal wiring of a semiconductor device, which detects the presence or absence of disconnection of a signal line.

【0024】本発明の対象となる被測定デバイスは図1
(a) に示す如く同一パッケージ1内に複数の半導体チッ
プ11、12が搭載され、半導体チップ11、12の各端子はワ
イヤや配線パターンを介しパッケージに設けられた外部
端子An に接続されている。
FIG. 1 shows a device under test to which the present invention is applied.
a plurality of semiconductor chips 11 and 12 in the same package 1 as shown in (a) are mounted, the terminals of the semiconductor chips 11 and 12 are connected to the external terminal A n provided on the package via a wire or a wiring pattern I have.

【0025】接続部も含めた内部配線に断線が無い場合
は外部端子An に定電流を印加すると定電流は両方の半
導体チップに分流し、半導体チップ内部の保護ダイオー
ド特性によって決まる電圧値VDFが外部端子An と接
地端子Gとの間に発生する。
[0025] When there is no disconnection in the internal wiring, including the connections for applying a constant current to an external terminal A n constant current is shunted to both of the semiconductor chip, the voltage value VDF determined by the protection diode characteristics of the semiconductor chip It occurs between the external terminal An and the ground terminal G.

【0026】それに対し内部配線に断線13が発生すると
外部端子An に印加された電流は一方の半導体チップ
(図では11)に流れ、外部端子An と接地端子Gとの間
の電圧値VDFS は内部配線に断線が無い場合の電圧値
VDFに比べて当然高くなる。
[0026] In contrast to flow into the disconnection internal wiring 13 is generated external terminals A n to the applied current is one of the semiconductor chip (11 in the figure), a voltage value VDF between the external terminals A n and the ground terminal G S naturally becomes higher than the voltage value VDF when there is no disconnection in the internal wiring.

【0027】したがって、信号線が接続された外部端子
に定電流電源から電流を印加すると共に外部端子におけ
る電圧値を測定し、予め測定されている良品における端
子電圧値と比較することによって信号線の断線の有無を
検出することが可能になる。
Therefore, by applying a current from the constant current power supply to the external terminal to which the signal line is connected, measuring the voltage value at the external terminal, and comparing the measured voltage value with the previously measured terminal voltage value of the non-defective product. It is possible to detect the presence or absence of disconnection.

【0028】このように本発明の断線検出方法は半導体
チップを動作状態にすることなく内部配線の断線の有無
を検知できるため、回路構成上の理由によって搭載され
た半導体チップを個々に動作させることが不可能な場合
も断線の検知が可能である。
As described above, according to the disconnection detecting method of the present invention, the presence / absence of disconnection of the internal wiring can be detected without putting the semiconductor chip into an operating state, so that the mounted semiconductor chips can be individually operated for circuit configuration reasons. Even if it is not possible, disconnection can be detected.

【0029】また、個々の半導体チップに試験信号や制
御信号等を繰り返し印加する必要がないため、作業が簡
略化されると共に試験時間が短縮され、しかも、半導体
チップの動作は関係ないため内部配線に起因する不良の
みを検知することができる。
Further, since it is not necessary to repeatedly apply a test signal, a control signal, and the like to each semiconductor chip, the operation is simplified and the test time is shortened. Can be detected only.

【0030】即ち、複数の半導体チップに共通に接続さ
れた信号線の断線を簡単に検出できる断線検出方法を実
現することができる。
That is, it is possible to realize a disconnection detecting method capable of easily detecting a disconnection of a signal line commonly connected to a plurality of semiconductor chips.

【0031】[0031]

【発明の実施の形態】以下添付図により本発明の実施例
について説明する。図2は外部端子における電圧値の分
布を示す図、図3は断線検出に用いる測定装置の一例を
示すブロック図、図4は本発明になる断線検出方法を示
すフローチャートである。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings. 2 is a diagram showing a distribution of voltage values at external terminals, FIG. 3 is a block diagram showing an example of a measuring device used for disconnection detection, and FIG. 4 is a flowchart showing a disconnection detection method according to the present invention.

【0032】図5に示す如く被測定デバイスは外部端子
1 〜AX の他に外部端子B1 〜B X がそれぞれの半導
体チップに接続され、外部端子を介して単独の半導体チ
ップに定電流を印加すると電圧値VDFは図2(a) およ
び(b) に示す如く分布する。
As shown in FIG. 5, the device under test has external terminals.
A1~ AXExternal terminal B1~ B XAre each semiconductive
Connected to the semiconductor chip, and a single semiconductor chip
When a constant current is applied to the tip, the voltage value VDF changes as shown in FIG.
And (b).

【0033】一方、複数の半導体チップが共に内部配線
を介して外部端子A1 〜AX および外部端子B1 〜BX
に接続されたとき、電圧値VDFは図2(a) および(b)
に示した二つの分布が合成されるため電圧値VDFは図
2(c) に示す如く分布する。
On the other hand, the external terminals A 1 through an internal wiring plurality of semiconductor chips are both to A X and the external terminals B 1 .about.B X
2 (a) and (b)
2 are combined, the voltage value VDF is distributed as shown in FIG. 2 (c).

【0034】電圧値VDFはそれぞれの半導体チップの
保護ダイオード特性によって決まる値であり、図2(a)
、(b) に示す分布の形は被測定デバイスを構成する半
導体チップにより変化し、それに伴って図2(c) に示す
電圧値VDFの分布も変わる。
The voltage value VDF is a value determined by the protection diode characteristics of each semiconductor chip.
, (B) changes depending on the semiconductor chip constituting the device under test, and the distribution of the voltage value VDF shown in FIG. 2 (c) changes accordingly.

【0035】しかし、半導体チップが異なる場合でも電
圧値VDFの分布の最大値(max )と最小値(min )の
差は近似しており、被測定デバイスを構成する半導体チ
ップ数が同じであれば図2(c) に示す如くmax とmin と
の差は近似したものになる。
However, even when the semiconductor chips are different, the difference between the maximum value (max) and the minimum value (min) of the distribution of the voltage value VDF is similar, and if the number of semiconductor chips constituting the device to be measured is the same. As shown in FIG. 2C, the difference between max and min is approximate.

【0036】したがって、電圧値VDFの分布が図2
(d) に示す如く他の電圧値VDFから大きく外れたmax
値を含んでいる場合は、電圧値VDFがmax 値を示す外
部端子と半導体チップの端子との間で内部配線に断線が
発生していることを意味する。
Therefore, the distribution of the voltage value VDF is shown in FIG.
As shown in (d), max deviates greatly from other voltage values VDF.
When the value includes the value, it means that a disconnection has occurred in the internal wiring between the external terminal whose voltage value VDF indicates the maximum value and the terminal of the semiconductor chip.

【0037】図3は本発明になる断線検出方法に基づい
て被測定デバイス2の内部配線の断線を検出する測定装
置の一例であって、少なくともソケット(またはプロー
ブユニット)3とスイッチユニット4と電圧計5と試験
用電源6で構成されている。
FIG. 3 shows an example of a measuring device for detecting a disconnection of the internal wiring of the device under test 2 based on the disconnection detecting method according to the present invention, wherein at least a socket (or probe unit) 3, a switch unit 4, a voltage It comprises a total of 5 and a test power supply 6.

【0038】被測定デバイス2はソケット(またはプロ
ーブユニット)3に装着され、被測定デバイス2の外部
端子A1 〜AX 、B1 〜BX (図示していない)は、ソ
ケット(またはプローブユニット)3を介しスイッチユ
ニット4に接続されている。
The device under test 2 is mounted on a socket (or probe unit) 3, and the external terminals A 1 to A X and B 1 to B X (not shown) of the device under test 2 are connected to the socket (or probe unit). ) 3 to the switch unit 4.

【0039】スイッチユニット4は外部端子A1
X 、B1 〜BX (図示していない)に対応する数のス
イッチ41を具えており、スイッチ41は任意の外部端子
(図はA2)を試験用電源6に接続すると共に他の外部
端子を接地回路GNDに接続する。
The switch unit 4 has external terminals A 1 -A
A X, B 1 ~B X (not shown) and comprises a number of switches 41 corresponding to the switch 41 (FIG. A 2) any external terminals other with connecting to the test power supply 6 An external terminal is connected to the ground circuit GND.

【0040】外部端子A1 〜AX 、B1 〜BX に接続さ
れているスイッチユニット4は、個々のスイッチ41を手
動によって切り替える方式に限定したものではなく、例
えば制御信号の入力によって自動的に切り替えることが
できるものであってもよい。
The switch units 4 connected to the external terminals A 1 to A X and B 1 to B X are not limited to a system in which the individual switches 41 are manually switched. It may be one that can be switched to.

【0041】試験用電源6の電極は一方がスイッチユニ
ット4のスイッチ41に接続されると共に他方に接地回路
GNDに接続され、それぞれの外部端子の電圧値VDF
を測定する電圧計5が試験用電源6と並列にスイッチユ
ニット4に接続されている。
One of the electrodes of the test power supply 6 is connected to the switch 41 of the switch unit 4 and the other is connected to the ground circuit GND.
Is connected to the switch unit 4 in parallel with the test power supply 6.

【0042】なお、図示省略されているが電圧計5によ
る計測値をデジタル化することにより例えば計測値を記
憶装置に格納したり、或いは計測値を規定値と比較して
良・不良の自動判定を行い測定結果の表示やプリントア
ウト等の実行が可能になる。
Although not shown, the measured value of the voltmeter 5 is digitized to store, for example, the measured value in a storage device, or to compare the measured value with a specified value to automatically determine good / bad. And display of measurement results and execution of printout and the like can be performed.

【0043】本発明になる断線検出方法は図4に示す如
く被測定デバイスを測定装置のソケットまたはプローブ
ユニットにセットし、スイッチユニットを操作すること
により外部端子A1 を試験用電源に接続し他の外部端子
を接地回路GNDに落とす。
The breakage detecting method according to the present invention is set to a socket or a probe unit of the measuring apparatus device under test as shown in FIG. 4, the other to connect the external terminals A 1 to the test power supply by operating the switch unit Is dropped to the ground circuit GND.

【0044】外部端子A1 に定電流を入力すると共に電
圧計によって外部端子A1 の電圧を測定して測定結果を
記憶装置に格納し、外部端子A1 〜AX の全てについて
測定されるまでスイッチユニットの操作から測定結果の
格納に至る工程を繰り返す。
[0044] stores the measurement result by measuring the voltage of the external terminal A 1 by a voltmeter and inputs a constant current to an external terminal A 1 in the storage device until it is determined for all of the external terminals A 1 to A X The steps from the operation of the switch unit to the storage of the measurement result are repeated.

【0045】外部端子A1 〜AX の全てから得られた測
定値の最大値をVmax 、最小値をVmin としてVmax と
Vmin の差を算出し、Vmax とVmin の差を規定値と比
較して大きければ被測定デバイスを不良、小さければ被
測定デバイスを良品とする。
The difference between Vmax and Vmin is calculated with the maximum value of the measured values obtained from all of the external terminals A 1 to A X as Vmax and the minimum value as Vmin, and the difference between Vmax and Vmin is compared with a specified value. If the size is larger, the device under test is defective. If the size is smaller, the device under test is non-defective.

【0046】なお、図示省略されているが外部端子B1
〜BX についても同様に電圧を測定することでVmax と
Vmin の差を算出し、Vmax とVmin の差を規定値と比
較して大きければ被測定デバイスを不良、小さければ被
測定デバイスを良品とする。
Although not shown, the external terminal B 1
Calculating the difference between Vmax and Vmin by measuring the voltage Similarly, the .about.B X, larger by comparing the difference between Vmax and Vmin a specified value to be measured device failure, and good products DUT smaller I do.

【0047】このように本発明の断線検出方法は半導体
チップを動作状態にすることなく内部配線の断線の有無
を検知できるため、回路構成上の理由によって搭載され
た半導体チップを個々に動作させることが不可能な場合
も断線の検知が可能である。
As described above, according to the disconnection detecting method of the present invention, the presence or absence of disconnection of the internal wiring can be detected without putting the semiconductor chip into an operating state. Even if it is not possible, disconnection can be detected.

【0048】また、個々の半導体チップに試験信号や制
御信号等を繰り返し印加する必要がないため、作業が簡
略化されると共に試験時間が短縮され、しかも、半導体
チップの動作は関係ないため内部配線に起因する不良の
みを検知することができる。
Further, since it is not necessary to repeatedly apply a test signal, a control signal, and the like to each semiconductor chip, the operation is simplified and the test time is shortened. Can be detected only.

【0049】[0049]

【発明の効果】上述の如く本発明によれば複数の半導体
チップに共通に接続された信号線の断線を、簡単に検出
できる断線検出方法を提供することができる。
As described above, according to the present invention, it is possible to provide a disconnection detecting method capable of easily detecting a disconnection of a signal line commonly connected to a plurality of semiconductor chips.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明になる断線検出方法を示す原理図であ
る。
FIG. 1 is a principle diagram showing a disconnection detection method according to the present invention.

【図2】 外部端子における電圧値の分布を示す図であ
る。
FIG. 2 is a diagram showing a distribution of voltage values at external terminals.

【図3】 断線検出に用いる測定装置の一例を示すブロ
ック図である。
FIG. 3 is a block diagram showing an example of a measuring device used for disconnection detection.

【図4】 本発明になる断線検出方法を示すフローチャ
ートである。
FIG. 4 is a flowchart illustrating a disconnection detection method according to the present invention.

【図5】 被測定デバイスの回路構成例を示す図であ
る。
FIG. 5 is a diagram illustrating a circuit configuration example of a device under test.

【図6】 内部配線の断線例を示す図である。FIG. 6 is a diagram showing an example of disconnection of internal wiring.

【図7】 従来の試験方法を示すフローチャートであ
る。
FIG. 7 is a flowchart showing a conventional test method.

【符号の説明】[Explanation of symbols]

1 パッケージ 2 被測定デバイス 3 ソケット 4 スイッチユニット 5 電圧計 6 試験用電源 11、12 半導体チップ 13 断線 41 スイッチ DESCRIPTION OF SYMBOLS 1 Package 2 Device under test 3 Socket 4 Switch unit 5 Voltmeter 6 Test power supply 11, 12 Semiconductor chip 13 Disconnection 41 Switch

フロントページの続き (72)発明者 坪田 崇 長野県須坂市大字小山460番地 富士通メ ディアデバイス株式会社内 Fターム(参考) 2G003 AA07 AB18 AE08 AF01 AF04 AF06 AG01 AH03 AH04 2G014 AA02 AB51 AC07 AC15 Continued on the front page (72) Inventor Takashi Tsubota 460 Oyama, Sazaka, Nagano Prefecture F-term in Fujitsu Media Devices Limited (Reference) 2G003 AA07 AB18 AE08 AF01 AF04 AF06 AG01 AH03 AH04 2G014 AA02 AB51 AC07 AC15

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 同一パッケージの中に複数の半導体チッ
プが搭載されている半導体装置を対象として、複数の該
半導体チップに共通に接続された信号線の断線を検出す
る断線検出方法であって、 該信号線が接続された外部端子に試験用電源から定電流
を印加すると共に、該外部端子における端子電圧を測定
し、 良品の半導体装置における端子電圧と比較することによ
って、該信号線の断線の有無を検出することを特徴とす
る半導体装置の内部配線断線検出方法。
1. A disconnection detecting method for detecting a disconnection of a signal line commonly connected to a plurality of semiconductor chips for a semiconductor device having a plurality of semiconductor chips mounted in the same package. A constant current is applied from a test power supply to the external terminal to which the signal line is connected, and the terminal voltage at the external terminal is measured and compared with the terminal voltage of a non-defective semiconductor device. A method for detecting internal wire disconnection in a semiconductor device, comprising detecting presence or absence.
JP35183099A 1999-12-10 1999-12-10 Method for detecting disconnection of internal wiring of semiconductor device Expired - Lifetime JP3979619B2 (en)

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Application Number Priority Date Filing Date Title
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Application Number Priority Date Filing Date Title
JP35183099A JP3979619B2 (en) 1999-12-10 1999-12-10 Method for detecting disconnection of internal wiring of semiconductor device

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JP3979619B2 JP3979619B2 (en) 2007-09-19

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100335910C (en) * 2001-12-31 2007-09-05 技嘉科技股份有限公司 Open circuit/short circuit detector and its detection method
JP2011022104A (en) * 2009-07-21 2011-02-03 Daikin Industries Ltd Method and device for inspecting opening/short-circuit of external terminal in integrated circuit
US10497670B2 (en) 2016-12-06 2019-12-03 Samsung Electronics Co., Ltd. Multi-chip package capable of testing internal signal lines

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209633A (en) * 1982-05-28 1983-12-06 Nippon Denso Co Ltd Lamp disconnection detection device
JPH03187236A (en) * 1989-12-07 1991-08-15 Texas Instr Inc <Ti> Test circuit which checks passive substrate for incorporating integrated circuit
JPH0643219A (en) * 1992-04-16 1994-02-18 Mega Chips:Kk Semiconductor device and its inspecting method
JPH1164428A (en) * 1997-08-27 1999-03-05 Hioki Ee Corp Component inspection device

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58209633A (en) * 1982-05-28 1983-12-06 Nippon Denso Co Ltd Lamp disconnection detection device
JPH03187236A (en) * 1989-12-07 1991-08-15 Texas Instr Inc <Ti> Test circuit which checks passive substrate for incorporating integrated circuit
JPH0643219A (en) * 1992-04-16 1994-02-18 Mega Chips:Kk Semiconductor device and its inspecting method
JPH1164428A (en) * 1997-08-27 1999-03-05 Hioki Ee Corp Component inspection device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100335910C (en) * 2001-12-31 2007-09-05 技嘉科技股份有限公司 Open circuit/short circuit detector and its detection method
JP2011022104A (en) * 2009-07-21 2011-02-03 Daikin Industries Ltd Method and device for inspecting opening/short-circuit of external terminal in integrated circuit
US10497670B2 (en) 2016-12-06 2019-12-03 Samsung Electronics Co., Ltd. Multi-chip package capable of testing internal signal lines

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