JP2006226908A - Method of inspecting multi-chip package - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of inspecting multi-chip package which can collectively inspect all of the sealed semiconductor integrated circuits, without increasing the number of external terminals. <P>SOLUTION: A first semiconductor integrated circuit 60 writes arbitrary data onto a second semiconductor integrated circuit 70. Thereafter, when data reading control on the second semiconductor integrated circuit 70 is conducted, the same value as the expected data is outputted from the first semiconductor integrated circuit 60, allowing each data to collide with each other. At this time, leakage current in an internal bus part is measured; and if an operation is performed as the expected value, the leakage current will increase, when the same data collide with each other. If an operation that is not of expected value is performed, the leakage current will increase, when different data collide with each other; and the occurrence of operation failure can be inspected easily. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an inspection method for a multi-chip package in which a plurality of semiconductor integrated circuits are sealed in one package.

  In recent years, the hardware configuration of electronic devices has become complicated, and is configured with a large number of semiconductor integrated circuits. On the other hand, there is a demand for downsizing and weight reduction of electronic devices, so that a multi-chip package in which a plurality of semiconductor integrated circuits are sealed in one package is used to reduce the number of mounted components. It is becoming. In the case of this multi-chip package configuration, it is necessary to inspect whether each semiconductor integrated circuit configured at the time of product shipment normally operates, and such a method has been proposed (for example, see Patent Document 1).

  FIG. 8 is an explanatory diagram of a conventional multi-package inspection method disclosed in Patent Document 1. In FIG. In this figure, a multi-chip package 10 is sealed with a first semiconductor integrated circuit (master device) 20 and a second semiconductor integrated circuit (slave device) 30. An external terminal 11 is connected to the first semiconductor integrated circuit 20, and the first semiconductor integrated circuit 20 and the second semiconductor integrated circuit 30 are connected by an internal connection bus 12. The internal connection bus 12 is connected to the test external terminal 13. The first semiconductor integrated circuit 20 that is a master device includes an output buffer 21 with tristate control, an input buffer 22, a test mode setting register 23, and an AND circuit 24 with one-side inverter input.

In this prior art, as a method of individually inspecting the second semiconductor integrated circuit 30 connected to the first semiconductor integrated circuit 20 by the internal bus 12, it is incorporated in the first semiconductor integrated circuit 20. By setting the test mode setting register 23 to the test mode (“1” in this figure), the output buffer 21 with tristate control is fixed to the tristate state. By inputting / outputting a signal from the test external terminal 13 in this state, the terminal of the second semiconductor integrated circuit 30 can be directly controlled and monitored, and the second semiconductor integrated circuit 30 can be easily inspected. .
JP 2002-372570 A (FIG. 1)

  However, in the conventional inspection method for a multi-chip package, a test external terminal (terminal indicated by reference numeral 13 in FIG. 8) is required as a component of the multi-chip package, and many signal lines are used for internal connection. In this case, it is necessary to output all of the signals flowing through the signal lines to the test external terminals, and many test external terminals are required. As a result, the total number of external terminals of the multichip package increases, resulting in an increase in package size and cost.

  In other words, when a plurality of semiconductor integrated circuits are sealed in one package, the sealed product is inspected to inspect for defective products that may occur during the packaging process. Due to restrictions and the like, the terminals of each semiconductor integrated circuit are often not external, and the difficulty of inspection is increasing.

  The present invention has been made in view of such points, and provides a multichip package inspection method capable of inspecting all of a plurality of sealed semiconductor integrated circuits without increasing the number of external terminals. Objective.

(1) In the inspection method for a multichip package of the present invention, a master semiconductor integrated circuit having a master device function and at least one slave semiconductor integrated circuit having a slave device function are sealed in one package, At least two semiconductor integrated circuits in which a bus interface for performing a master operation of the master semiconductor integrated circuit and a bus interface for performing a slave operation of at least one slave semiconductor integrated circuit are connected to the internal bus for each signal. In a multi-chip package inspection method for determining whether or not there is an abnormality in the slave semiconductor integrated circuit in a multi-chip package composed of circuits, any data can be read from the master semiconductor integrated circuit to the slave semiconductor integrated circuit The data is written in advance, and then the arbitrary data is read-accessed to the slave semiconductor integrated circuit, and at the same time, the same data as the arbitrary data is output from the master semiconductor integrated circuit, and the bus portion at that time Then, based on the value of the leak current, the presence or absence of a defect in the slave semiconductor integrated circuit is determined.

  According to this method, when the master semiconductor integrated circuit writes arbitrary data to the slave semiconductor integrated circuit and then performs data read control on the slave semiconductor integrated circuit, the same value as the expected data is obtained from the master semiconductor integrated circuit. The data is also output from the circuit, causing each data to collide. At this time, if the leakage current of the internal bus portion is measured and the operation is performed as expected, the leakage current does not increase even if the same data collides with each other, and the operation is performed as expected. However, when different data collide with each other, the leakage current increases and it can be easily inspected that a malfunction occurs.

(2) A multi-chip package inspection method according to the present invention is the multi-chip package inspection method according to (1), wherein a memory capable of reading and writing data is used as the slave semiconductor integrated circuit. Arbitrary data is written to all address areas, and then the read access to the memory is performed, and at the same time, the same data as the arbitrary data is output from the master semiconductor integrated circuit, and the leakage current of the bus portion is measured Whether or not there is an abnormality in the memory is determined by performing the process on all the address areas of the memory.

  According to this method, a memory capable of reading and writing data is used as a slave semiconductor integrated circuit, and processing is performed on the entire area of the memory by using the same method as in (1) above. It is possible to easily inspect all addresses and perform a complete inspection.

(3) The multi-chip package inspection method of the present invention is the multi-chip package inspection method according to the above (1), wherein when a memory dedicated to data reading is used as the slave semiconductor integrated circuit, all addresses of the memory are used. All addresses of the memory can be used to perform read access to the area and output the same data as expected memory output data corresponding to each address from the master semiconductor integrated circuit and measure the leak current of the bus portion. By determining whether or not there is an abnormality in the memory, the determination is made on the area.

  According to this method, a data read-only memory is used as the slave semiconductor integrated circuit, and data that is expected in advance when the master semiconductor integrated circuit reads data from the master semiconductor integrated circuit is also output from the master semiconductor integrated circuit. Then, by measuring the leakage current at that time and performing this on all the address areas of the memory, a complete inspection can be performed as in (1) above.

(4) The multi-chip package inspection method of the present invention is such that in the multi-chip package inspection method described in (1) above, arbitrary data can be read from the master semiconductor integrated circuit to the slave semiconductor integrated circuit. The data is written in advance to the slave semiconductor integrated circuit, and then the slave semiconductor integrated circuit performs read access to the arbitrary data and simultaneously outputs the output value of the slave semiconductor integrated circuit expected from the master semiconductor integrated circuit. The leak current of the bus portion at that time is measured, and it is determined whether or not the bus is normally connected based on the value of the leak current.

  According to this method, when the master semiconductor integrated circuit writes arbitrary data to the slave semiconductor integrated circuit and then performs data read control on the slave semiconductor integrated circuit, data opposite to the expected data is transferred to the master semiconductor. Output from the integrated circuit and collide each data. At this time, if the leakage current of the internal bus part is measured and the operation is performed as expected, different data will collide with each other and the leakage current will increase. For example, if an internal disconnection occurs Since the data do not collide with each other, the leakage current does not increase, and it can be easily inspected that a defect in the package sealing process is caused by the internal bus disconnection.

(5) In the multi-chip package inspection method of the present invention, a master semiconductor integrated circuit having a master device function and at least two slave semiconductor integrated circuits having the same slave device function are sealed in one package, and At least three bus interfaces that perform master operation of the master semiconductor integrated circuit and bus interfaces that perform slave operation of at least two slave semiconductor integrated circuits are connected to the internal bus for each signal in the package. In the multi-chip package inspection method for determining whether or not there is an abnormality in the slave semiconductor integrated circuit in the multi-chip package composed of the semiconductor integrated circuits, the same arbitrary value is applied from the master semiconductor integrated circuit to all the slave semiconductor integrated circuits. Of data The data is written in advance so that the data can be read out, and then the arbitrary data is read and accessed simultaneously for all the slave semiconductor integrated circuits. At that time, the leakage current of the bus portion is measured and the leakage current is measured. Based on this value, it is determined whether all the slave semiconductor integrated circuits are normal or defective.

  According to this method, the master semiconductor integrated circuit writes arbitrary data to each of at least two slave semiconductor integrated circuits, and then performs data read control on each slave semiconductor integrated circuit at the same time. The output data of the integrated circuits collide with each other. At this time, if the leakage current of the internal bus part is measured, if the operation is performed as expected, the leakage current does not increase even if the same data collides with each other, and the operation is as expected. If different data collide with each other, the leakage current increases and it can be easily inspected that a malfunction occurs.

(6) The multi-chip package inspection method according to the present invention is the multi-chip package inspection method according to (5), wherein all the slave semiconductor integrated circuits are composed of a memory capable of reading and writing data with the same configuration and the same capacity. The same arbitrary data is written to the same memory address from the master semiconductor integrated circuit to all the memories, and this writing is repeated for all the memory areas, and then for all the memories. By reading the same address at the same time and measuring the leakage current on the bus while reading the entire address, it is determined whether all the memories are normal or defective.

  According to this method, a data readable / writable memory having the same capacity and the same configuration is used as at least two slave semiconductor integrated circuits. By using the same method as the above (5), the entire area of each memory is used. The processing can be performed on all addresses, and all addresses can be easily inspected and a complete inspection can be performed.

(7) The multi-chip package inspection method of the present invention is the multi-chip package inspection method according to (5), wherein any data different from the master semiconductor integrated circuit to all of the slave semiconductor integrated circuits is recorded. Data is written in advance so as to be able to be read, and then, the read access of the arbitrary data is simultaneously performed on all the slave semiconductor integrated circuits at the same time, the leakage current of the bus portion at that time is measured, and the leakage current Whether or not the bus is normally connected is determined based on the value of.

  According to this method, the master semiconductor integrated circuit writes arbitrary different data to at least two slave semiconductor integrated circuits, and then simultaneously reads data from each of the slave semiconductor integrated circuits. Collide. At this time, if the leakage current of the internal bus part is measured and the operation is performed as expected, different data will collide with each other and the leakage current will increase. For example, if an internal disconnection occurs Since the data do not collide with each other, the leakage current does not increase, and it can be easily inspected that a defect in the package sealing process is caused by the internal bus disconnection.

  According to the present invention, by measuring the leakage current on the internal connection bus sealed with the multi-chip package, it is possible to easily inspect whether there is a device defect and whether a defect has occurred in the package sealing process. In addition, since it is not necessary to output the internal connection bus as an external terminal, it is not necessary to increase the total number of terminals of the multichip package, and the package can be reduced in size and cost.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a block diagram showing a schematic configuration of a multichip package according to Embodiment 1 of the present invention. In this figure, a multi-chip package 50 is sealed with a first semiconductor integrated circuit (master device) 60 and a second semiconductor integrated circuit (slave device) 70. Two semiconductor integrated circuits 70 are connected via the internal bus 12, and the external terminal 11 is connected to the first semiconductor integrated circuit 60. In the present invention, the internal bus 12 is not connected to the external terminal 13 (see FIG. 8). FIG. 2 is a circuit configuration diagram showing in detail one signal portion of the bus connection portion of the first semiconductor integrated circuit 60 and the second semiconductor integrated circuit 70, and the output buffer 21 with tristate control is provided in each bus interface portion. Are connected to the input buffer 22. FIG. 3 shows an example of a transistor level circuit.

  The first semiconductor integrated circuit 60 has a current detection unit 601 that detects a leak current flowing through the internal bus 12, and this current detection unit 601 is used when the second semiconductor integrated circuit 70 is inspected. The inspection of the second semiconductor integrated circuit 70 is performed according to a control program supplied from the inspection apparatus 100 connected to the external terminal 11. This control program includes the following steps.

A step of writing arbitrary data from the first semiconductor integrated circuit 60 to the second semiconductor integrated circuit 70. A data written to the second semiconductor integrated circuit 70 simultaneously with the reading of the data written to the second semiconductor integrated circuit 70. The step of reading the same data as the step of measuring the leakage current of the bus portion at the time of data reading and the step of determining the presence or absence of a defect in the second semiconductor integrated circuit 70 based on the measured leakage current value

First, the second semiconductor integrated circuit 70 is set so that arbitrary data can be read via the internal bus 12, and then the second semiconductor integrated circuit 70 is subjected to read control using the data as an expected value. . At this time, the first semiconductor integrated circuit 70 outputs the same data as the expected value at the same time. For example, in FIG. 3, if the output data expected at a connection portion of a certain signal is “1”, the tristate control in the output buffer 21 with tristate control of the first semiconductor integrated circuit 60 is in the output enable state. And “1” is output as an output signal. At this time, the state of the four transistors 210 to 213 connected in series from the V _DD side to the GND side is “ON-ON-OFF-ON” in order from the V _DD side.

On the other hand, when the second semiconductor integrated circuit 70 side is also operating as expected, the states of the four transistors 210 to 213 connected in series from the V _DD side to the GND side are changed from the V _DD side. It becomes "ON-ON-OFF-ON" in order. At this time, when the leakage current on the internal bus 12 is measured, a large leakage current does not occur because only the off-state transistor 212 exists on the path from the V _DD side to the GND side (only the OFF leakage current is generated). Not flowing).

However, on the other hand, if some trouble occurs in the second semiconductor integrated circuit 70 and data “0” opposite to the expected value is output, the output buffer 21 with tristate control of the second semiconductor integrated circuit 70. Then, the states of the four transistors 210 to 213 connected in series from the V _DD side to the GND side are “ON-OFF-ON-ON” in order from the V _DD side. As In such a state, via the internal bus 12, the internal bus 12 from the V _DD side of the path (the first semiconductor integrated circuit 60 the transistor on a path from V _DD side to GND side are all ON Since there is a path to the GND side of the second semiconductor integrated circuit 70, a large leak current is generated on the internal bus 12 (an ON current of the transistor is generated).

Similarly, if the expected output data is “0” and the operation is as expected, the output buffer 21 with tristates of the first semiconductor integrated circuit 60 and the second semiconductor integrated circuit 70 is used. The state of the four transistors 210 to 213 connected in series from the V _DD side to the GND side of each of the transistors becomes “ON-OFF-ON-ON” in order from the V _DD side, and a large leak current does not occur. When the output of the second semiconductor integrated circuit 70 becomes “1” output opposite to the expected value, the output buffer 21 with tristate of the second semiconductor integrated circuit 70 is connected in series from the V _DD side to the GND side. DOO four states of transistors 210-213 _{is, "oN-oN-OFF-} oN" next in order from the _{V DD} side, via the internal bus _12, on the path from the _{V DD} side to GND side who are Njisuta is (as the internal bus 12 from the V _DD side of the second semiconductor integrated circuit 70, the path to the GND side of the first semiconductor integrated circuit 60) every path to be ON for the presence, on the internal bus 12 A large leak current is generated. The first semiconductor integrated circuit 60 determines that there is an abnormality in the second semiconductor integrated circuit 70 when a large leak current occurs.

  As described above, when the first semiconductor integrated circuit 60 writes arbitrary data to the second semiconductor integrated circuit 70 and then performs data read control on the second semiconductor integrated circuit 70, the expected data The same value is output from the first semiconductor integrated circuit 60, and the respective data collide with each other. At this time, if the leakage current of the internal bus portion is measured and the operation is performed as expected, the leakage current does not increase even if the same data collides with each other, and the operation is performed as expected. However, when different data collide with each other, the leakage current increases and it can be easily inspected that a malfunction occurs.

  In addition, there is no need to output the connection bus inside the multichip package as an external terminal for the purpose of inspection, and the device can be inspected by measuring leakage current. Useful for cost reduction.

  Here, when a memory capable of reading and writing data such as a RAM (Random Access Memory) is used as the second semiconductor integrated circuit 70, arbitrary data is written to all the memory addresses, and all the memory While reading out the area, the expected output data is sequentially output from the first semiconductor integrated circuit 60 to collide with the data, and the leakage current on the internal bus 12 at that time is measured, thereby the RAM or the like. It is possible to completely check the memory that can read and write data.

  When a data read-only memory such as a ROM (Read Only Memory) is used as the second semiconductor integrated circuit 70, the expected output data is output to the first memory while reading all the memory addresses. By sequentially outputting the data from the semiconductor integrated circuit 60 to collide the data and measuring the leakage current on the internal bus 12 at that time, the data read-only memory such as the ROM can be completely inspected.

(Embodiment 2)
FIG. 4 is a block diagram showing a schematic configuration of a multichip package according to Embodiment 2 of the present invention. 5 is a circuit diagram showing in detail one signal of the bus connection portion of FIG. 4, and FIG. 6 is a circuit diagram showing a transistor configuration example of the bus connection portion of FIG. 4 to 6, the same components as those in FIGS. 1 to 3 described above are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 4, a first semiconductor integrated circuit (master device) 60 and second and third semiconductor integrated circuits (slave devices) 70 and 90 are connected via an internal bus 12 in a multichip package 80. Connected. The internal bus 12 is not connected to the external terminal 13 (see FIG. 8) as in the first embodiment. Further, as shown in FIG. 5, the output buffer 21 with tristate control and the input buffer 22 are provided in the bus interface portions of the first semiconductor integrated circuit 60, the second semiconductor integrated circuit 70, and the third semiconductor integrated circuit 90, respectively. It is connected.

  The first semiconductor integrated circuit 60 inspects the second and third semiconductor integrated circuits 70 and 90 in accordance with a control program supplied from the inspection apparatus 100 connected to the external terminal 11. In this case, the current detection unit 601 is used as in the first embodiment. The inspection of the second and third semiconductor integrated circuits 70 and 90 is performed according to a control program supplied from the inspection apparatus 100 connected to the external terminal 11. This control program includes the following steps.

A step of writing arbitrary same data from the first semiconductor integrated circuit 60 to the second and third semiconductor integrated circuits 70 and 90. Data written to the second and third semiconductor integrated circuits 70 and 90, respectively. A step of measuring the leakage current of the bus portion at the time of data reading and a step of determining whether or not the second and third semiconductor integrated circuits 70 and 90 are defective based on the measured leakage current value

  First, each of the second and third semiconductor integrated circuits 70 and 90 is set so that arbitrary data can be read from the first semiconductor integrated circuit 60 via the internal bus 12. Next, the second and third semiconductor integrated circuits 70, 90 are subjected to read control from the first semiconductor integrated circuit 60 to the second and third semiconductor integrated circuits 70, 90 simultaneously with an arbitrary data as an expected value. 90 output signals collide with each other. At this time, unlike the first embodiment, data is not output from the first semiconductor integrated circuit 60.

Here, for example, in the connection portion of a certain signal shown in FIG. 6, if the expected output data is “1”, the output buffer 21 with tristate control of the second semiconductor integrated circuit 70 performs tristate control. Are in the output enable state and “1” is output as the output signal. The state of the transistors at this time, that is, the state of the four transistors 210 to 213 connected in series from the V _DD side to the GND side becomes “ON-ON-OFF-ON” in order from the V _DD side.

On the other hand, when the third semiconductor integrated circuit 90 side is also operating as expected, the states of the four transistors 210 to 213 connected in series from the V _DD side to the GND side are changed from the V _DD side. It becomes "ON-ON-OFF-ON" in order. At this time, when the leakage current on the internal bus 12 is measured, there is a transistor in the OFF state (the transistor 212 of the third semiconductor integrated circuit 90) on the path from the V _DD side to the GND side. Does not occur (that is, only the OFF leakage current flows).

However, on the other hand, if some trouble occurs in the second semiconductor integrated circuit 70 and data “0” opposite to the expected value is output, the output buffer 21 with the tristate of the second semiconductor integrated circuit 70 is not connected. The state of the four transistors 210 to 213 connected in series from the V _DD side to the GND side is “ON-OFF-ON-ON”. In this case, a path in which all transistors on the path from the V _DD side to the GND side are turned on via the internal bus 12 (the second bus from the V _DD side of the third semiconductor integrated circuit 90 through the internal bus 12 and the second bus Since there is a path to the GND side of the semiconductor integrated circuit 70, a large leak current is generated on the internal bus 12 (that is, an ON current of the transistor is generated).

Similarly, when the expected output data is “0” and the operation is as expected, the output buffers with tristates of the second semiconductor integrated circuit 70 and the third semiconductor integrated circuit 90 are used. The state of the four transistors 210 to 213 connected in series from the V _DD side to the GND side of the 21 part is both “ON-OFF-ON-ON”, and no large leak current is generated, but the second semiconductor integrated circuit When the output of 70 becomes “1” output opposite to the expected value, four transistors 210 to 213 connected in series from the V _DD side to the GND side of the output buffer 21 with tristate of the second semiconductor integrated circuit 70. state "oN-oN-OFF-oN " the next path on the transistor are all turned oN path to GND side from _{V DD} side through the internal bus 12 (the Through the internal bus 12 from the V _DD side of the semiconductor integrated circuit 90, because the path to the GND side of the second semiconductor integrated circuit 70) is present, a large leakage current on the internal bus 12 occurs.

  As described above, the read operation for which the same output is expected is simultaneously performed on the second and third semiconductor integrated circuits 70 and 90, and the leakage current at that time is measured, so that it is easy to determine whether the multichip package 80 is good or defective. Can be determined.

  In the second embodiment, an example in which the expected value of the second semiconductor integrated circuit 70 is inverted is described. However, even if the expected value of the third semiconductor integrated circuit 90 is inverted, the same principle is applied to It is possible to easily determine whether the chip package 80 is good or bad.

  In the second embodiment, the three configurations of the first semiconductor integrated circuit 60 and the second and third semiconductor integrated circuits 70 and 90 are described. The semiconductor integrated circuit which is M slave devices. Even if is connected, it is possible to easily discriminate between non-defective products and defective products between devices that collide data by the same principle.

  In the second embodiment, the second and third semiconductor integrated circuits 70 and 90 that are slave devices are read simultaneously, and the first semiconductor integrated circuit 60 that is a master device is described as not outputting data. However, regardless of whether the device is a master device or a slave device, when the leakage current at that time is measured while colliding the buses of the semiconductor integrated circuits connected to two or more internal buses 12, all of the output states at the time of measuring the leakage current In any one or more of the semiconductor integrated circuits, an operation failure exists (abnormal leakage occurs), or all semiconductor integrated circuits in the output state at the time of leakage current measurement are operating normally (abnormal leakage current) None) can be easily determined.

(Embodiment 3)
FIG. 7 shows a multi-chip package configuration when a disconnection occurs in the internal bus portion. The same components as those in FIG. 6 described above are denoted by the same reference numerals, and the description thereof is omitted.

  The third embodiment inspects whether or not the internal bus 12 sealed inside the multichip package is normally connected in the multichip package configuration shown in FIG. This is performed according to a control program provided from the connected inspection apparatus 100. This control program includes the following steps.

Step of writing arbitrary different data from the first semiconductor integrated circuit 60 to the second and third semiconductor integrated circuits 70 and 90 Data written to the second and third semiconductor integrated circuits 70 and 90 A step of measuring the leakage current of the bus portion at the time of data reading a step of determining whether or not the internal bus 12 is normally connected based on the measured leakage current value

  First, each of the second and third semiconductor integrated circuits 70 and 90 is set so that arbitrary data can be read from the first semiconductor integrated circuit 60 via the internal bus 12. However, at this time, the expected value of data set in the second semiconductor integrated circuit 70 and the expected value set in the third semiconductor integrated circuit 90 are set to be inverted data.

Next, the first and second semiconductor integrated circuits 60 and 90 perform read control with an arbitrary data as an expected value at the same time, and the second and third semiconductor integrated circuits 70 and 90. 90 output signals collide with each other. At this time, since the expected output values of the second and third semiconductor integrated circuits 70 and 90 are inverted, if the output is as expected, the GND from the V _DD side of the second semiconductor integrated circuit 70 The state of the four transistors 210 to 213 connected in series to the side is “ON-ON-OFF-ON” when the expected value is “1” (“ON-OFF- when the expected value is“ 0 ”). ON-ON "), and the state of the four transistors 210-213 connected in series from the V _DD side to the GND side of the third semiconductor integrated circuit 90 is" ON-OFF "when the expected value is" 0 " -ON-ON "(" ON-ON-OFF-ON "when the expected value is" 1 "), all the transistors on the path from the _VDD side to the GND side via the internal bus 12 Because there is a path that turns ON, internal bus 1 Large leakage current is generated in the above.

However, when a disconnection occurs on the bus path connected to the second semiconductor integrated circuit 70, there is no path in which all the transistors on the path from the _VDD side to the GND side are turned on via the internal bus 12. Therefore, a large leak current does not occur on the internal bus 12.

  In this way, the second and third semiconductor integrated circuits 70 and 90 are simultaneously subjected to a read operation in which an inverted output is expected, and at that time, the leakage current at that time is measured, thereby disconnecting the internal bus 12. The presence or absence of can be easily determined.

  In the third embodiment, a description is given for a multi-chip package constituted by three semiconductor integrated circuits of the first semiconductor integrated circuit 60 and the second and third semiconductor integrated circuits 70 and 90. Even when the first semiconductor integrated circuit 60 and the second semiconductor integrated circuit 70 described in the first embodiment are used, the first semiconductor integrated circuit 60 to the second semiconductor integrated circuit are used. When performing the read operation of 70, expected output data and inverted data are output simultaneously, and the leakage current at that time is measured, so that the occurrence of disconnection can be easily inspected based on the same principle. . The control program in this case includes the following steps.

The step of writing arbitrary data from the first semiconductor integrated circuit 60 to the second semiconductor integrated circuit 70 The second semiconductor integrated circuit 70 simultaneously with the reading of the data written to the second semiconductor integrated circuit 70 A step of reading data obtained by inverting the data written in the step of measuring a leak current of the bus portion at the time of reading data. Whether or not the internal bus 12 is normally connected based on the measured leak current value. Judgment step

  Further, even when M slave devices are connected, it is possible to easily inspect the occurrence of a disconnection on the bus between devices colliding with data by the same principle.

  The present invention is suitable for inspection at the time of product shipment of a multichip package in which a plurality of semiconductor integrated circuits are sealed in one package.

1 is a block diagram showing a schematic configuration of a multichip package according to a first embodiment of the present invention. The figure which shows the detailed structure of the bus connection of the multichip package which concerns on Embodiment 1. FIG. The figure which shows the transistor structure of the bus connection of the multichip package which concerns on Embodiment 1 FIG. 3 is a block diagram showing a schematic configuration of a multichip package according to a second embodiment of the present invention. The figure which shows the detailed structure of the bus connection of the multichip package which concerns on Embodiment 2. FIG. The figure which shows the transistor structure of the bus connection of the multichip package which concerns on Embodiment 2. The figure which shows the case where the disconnection has generate | occur | produced in the bus part with the transistor structure of the bus connection of the multichip package which concerns on Embodiment 3 of this invention. Block diagram showing schematic configuration of conventional multi-chip package

Explanation of symbols

DESCRIPTION OF SYMBOLS 11 External terminal 12 Internal bus 21 Output buffer with tristate control 22 Input buffer 50, 80 Multichip package 60 1st semiconductor integrated circuit 70 2nd semiconductor integrated circuit 90 3rd semiconductor integrated circuit 100 Inspection apparatus 210-213 Transistor 601 Current detector

Claims (7)

A bus interface in which a master semiconductor integrated circuit having a master device function and at least one slave semiconductor integrated circuit having a slave device function are sealed in one package, and a master operation of the master semiconductor integrated circuit is performed inside the package The slave semiconductor integrated circuit in a multi-chip package composed of at least two semiconductor integrated circuits, wherein a bus interface for performing a slave operation of the at least one slave semiconductor integrated circuit is connected to the internal bus for each signal In the multi-chip package inspection method to determine the presence or absence of abnormalities,
Data is written in advance so that arbitrary data can be read from the master semiconductor integrated circuit to the slave semiconductor integrated circuit, and then the read access of the arbitrary data is performed on the slave semiconductor integrated circuit. Output the same data as the arbitrary data from the master semiconductor integrated circuit, measure the leakage current of the bus portion at that time, and based on the value of the leakage current, whether there is a defect in the slave semiconductor integrated circuit at that time Multi-chip package inspection method to discriminate.   When a memory capable of reading and writing data is used as the slave semiconductor integrated circuit, arbitrary data is written to all address areas of the memory, and then the read access to the memory is performed simultaneously with the master semiconductor integrated circuit 2. The multichip package according to claim 1, wherein the same data as the arbitrary data is output from and the leakage current of the bus portion is measured for all address areas of the memory to determine whether there is an abnormality in the memory. Inspection method.   When a data read-only memory is used as the slave semiconductor integrated circuit, read access is made to all address areas of the memory, and at the same time, expected memory output data corresponding to each address from the master semiconductor integrated circuit The multi-chip package inspection method according to claim 1, wherein the same data is output and the leakage current of the bus portion is measured for all address areas of the memory to determine whether there is an abnormality in the memory.   Data is written in advance so that arbitrary data can be read from the master semiconductor integrated circuit to the slave semiconductor integrated circuit, and then the master semiconductor integrated circuit is read-accessed to the arbitrary data and simultaneously the master Output the slave semiconductor integrated circuit output value expected from the semiconductor integrated circuit and inverted data, measure the leakage current of the bus portion at that time, and the bus is normally connected based on the value of the leakage current The multi-chip package inspection method according to claim 1, wherein it is determined whether or not it is present. A master semiconductor integrated circuit having a master device function and at least two slave semiconductor integrated circuits having the same slave device function are sealed in one package, and the master operation of the master semiconductor integrated circuit is performed inside the package. A slave semiconductor in a multi-chip package composed of at least three semiconductor integrated circuits, wherein a bus interface for performing a slave operation of at least two slave semiconductor integrated circuits is connected to an internal bus for each signal In the inspection method of a multi-chip package for determining whether there is an abnormality in an integrated circuit,
Data is written in advance so that the same arbitrary data can be read from the master semiconductor integrated circuit to all the slave semiconductor integrated circuits, and then the arbitrary data is simultaneously read from all the slave semiconductor integrated circuits. A method for inspecting a multi-chip package, wherein access is performed simultaneously, the leakage current of the bus portion is measured at that time, and whether all the slave semiconductor integrated circuits are normal or defective is determined based on the value of the leakage current.   When all the slave semiconductor integrated circuits are configured with a memory capable of reading and writing data with the same configuration and the same configuration, the same arbitrary data is written to the same memory address from the master semiconductor integrated circuit to each of the memories, By repeating this writing for all the memory areas, and then simultaneously reading the same address for each of all the memories and measuring the leakage current on the bus while performing the reading for all the areas, The multi-chip package inspection method according to claim 5, wherein it is determined whether the memory is normal or defective.   Data is written in advance so that different arbitrary data can be read from the master semiconductor integrated circuit to all of the slave semiconductor integrated circuits, and then the arbitrary data is simultaneously written to all of the slave semiconductor integrated circuits. 6. The multi-chip package according to claim 5, wherein read access is performed simultaneously, the leakage current of the bus portion at that time is measured, and whether or not the bus is normally connected is determined based on the value of the leakage current. Inspection method.

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