JPS58158740A - Pipeline type multiplier - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a pipeline type multiplier remarkably, by connecting an injector of the preceding stage to a ground terminal of the succeeding stage and transmitting a signal to the function block of the succeeding stage from the function block of the preceding stage. CONSTITUTION:Shift registers 1, 2, decoders 5, 6 and selectors 11, 12 delaying a Y input signal are arranged between an injector 52 at the lowermost stage and a ground 51. An adder 15 is arranged between an injector 53 of the 2nd stage and the ground 52. Further, a decoder 7, a selector 13, a shift register 9, and a register 18 are arranged between an injector 54 of the 3rd stage and a ground 53. Similarly, an adder 16 is arranged, a decoder 8, a selector 14, a shift register 10 and a register 19 are arranged on the adder 16, and an adder 17 and a register 20 are arranged finally and an injector 58 of the register 20 is connected to a constant voltage source 56.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is an integrated inj.
This invention relates to a pipeline type multiplier with a low power consumption structure.

FIG. 1 shows the configuration of a pipelined multiplier based on Booth's algorithm. First, I will briefly explain Booth's algorithm. The 8-bit two's complement signals x and Y to the multiplier are transformed as follows.

Y knee, V, 27+,! /626+W525+! /4
2'+, Y323+ff222+, Y, 2'+, Vo=
(y5+,!/6-2y,)26+(y3+,!/4-
2. ! 15) 2'+(y, +y2-2!/3)22+
(y, +yo-2y,)-Σ (y2□-4+y
2. -2y2l+1)・221 (1)i=Q The product P obtained by multiplying this YVcX is as follows. (y2t-1+y2.-2y2l+1)・22
i−x is a partial product, and as is clear from equation (2), the product P can be obtained by shifting and adding four partial products.

(y2 i-1+'2 i-2'21-1-1) is 0. ±1. Takes a value of ±2. Therefore, the partial product is 0. The value will be either ±X or ±2x.

Here, the partial product can be easily generated by shifting 2x by 1 foot and adding 1 to the inverted values of -X, -2X1dX, and 2X. FIG. 1 shows a configuration according to this algorithm. 1 to 2 are shift registers that create consecutive 3-bit values, and 5 to 8 are 'zi-+"2i"zi. The decoder 5 outputs the value of (,!/-1+
yo-2. ! /, )l decoder 6 is (W, +!/2
2 ys ) l decoder 7 is (y, +, y4-2yJ
5).

The decoder 8 outputs (y5+y6-2y7), respectively.

9 to 10 are shift registers for signal X, and 11 to 14 are ('
Selectors 15 to 17 output selectors 2i +y2i'', 2i-1-2).X, and adders 15 to 17 add partial products. The outputs of selectors 11-14 are shifted by 0 bits, 1 bit, 2 bits, and 3 bits according to weight 2, respectively, and applied to adders 16-17. 18-20
is a register. 21 is a Y signal input terminal, 22 is an X signal input terminal, and 23 is a terminal for outputting the product P.

First, for every 3 bits from the signal Y input from the terminal 21, (to+y(1,,!/1) and (!1+y2+y3
) are created and each input to a decoder 6.6.

y-1 is always 0. From decoders 5 and 6 respectively (
y, +yo−2,! /, ) and (3/, +412-2
．． ! /3) is output and input to selectors 11 and 12.

On the other hand, signal X is input from terminal 22 and selector 11 and 1
2. Here, depending on the signal from the decoder 6°6, the power 2x is shifted to O9±X or 1 bit to the left.
One of the partial products of is output. The partial product of selector 11 and the partial product of selector 12 shifted one bit to the left are applied to adder 16 and added, and this result is latched in register 18. The above operations are executed during one clock.

In the next clock, first start with the Y signal (!5, y4 t
y5) by one clock in shift register 1, and input this signal to decoder 7. /3+,!
/4-2. ! 15). This output is selector 1
3 is input.

On the other hand, the input signal 16. Here, it is added to the output of register 18 and latched in register 19.

In the next clock, first start with the Y signal (W5 J6 + W
The bits in a) are delayed by two clocks in the shift register 2 and input to the decoder 8. Here (y5+y6-2y7
) is input to the selector 14.

On the other hand, the input signal X further delayed by one clock in the shift register 1o is input to the selector 14, and according to the signal from the decoder 8, the signal is outputted as O,X.

”-2x is output, shifted by 3 bits, and inputted to the adder 17.

Here, it is added to the output of register 19 and latched in register 2o. This output is the product of input signals X and Y, and is output to the output terminal 23 at the next clock. The above is the operation of a pipeline multiplier using Booth's algorithm.

FIG. 2 shows a full adder with an IIL configuration used in this multiplier. What is shown in the figure shows 1 bit.
．． 32.33 is a 2-output IIL gate, 34-4o is 1
Output IIL gate, 41° 42 is an IIL gate with 5 outputs. In IIL, the outputs are independent, so wired AN
D is completed, and wired AND is performed as appropriate as shown in FIG.

Each input consists of a partial product input terminal (denoted as x + y) and a carry signal input terminal (denoted as C), and the output is 3.
It consists of two outputs: a sum signal output terminal (indicated by 8) which outputs the result of adding two input signals from the IIL gate 41, and a carry signal output terminal (indicated by c/) which outputs the presence or absence of carry from the IIL gate 42.

The SUM signal signal is a partial product signal.

If the input SUM signal is represented by B and the carry human input signal is represented by C, then 5 = ABC + ABC + ABC + MBO, (3), and the logic connection in Figure 2 also expresses equation (1), and the output from gate 41 be done.

Since the logic formula for the carry signal C' is expressed as C'=A B-4-B C0A C (4), the logic connections also represent two formulas. The reason why there are six output terminals is that the required number of outputs of the IIL structure are provided independently. Since this carry is input to the five IIL gates of the upper bits, there are also five outputs. The adder in FIG. 1 is composed of the full adder in FIG. 2 for the number of bits.

On the other hand, the operating voltage of IIL is approximately o, s'v and TTL.

Compared to KCL, etc., the current per gate is also low, resulting in low power consumption. Furthermore, since the IIL can be manufactured in the process of manufacturing bipolar transistors, the degree of integration can be increased by combining the IIL with a small element area and the bipolar transistor. By the way, in a normal semiconductor integrated circuit (IC) using bipolar transistors, it is difficult to operate when the voltage is O or SV, and in general, TTL is s
V.

For linear ICs, it is around 1ov. Therefore, a compound IC that integrates a normal bipolar transistor and an IIL requires two power supply systems. However, since IIL is a constant current drive, it is not enough to just apply 0.8V, but a low current power supply or a resistor must be connected in series to limit the current.

Generally, in a composite IC, a resistor is often connected in series with the power supply used in the bipolar transistor circuit. In this case, most of the power is consumed by this series resistor, and the advantage of low power consumption of IIL is not utilized.

Let's find the current in the pipeline multiplier shown in Figure 1. The full adder shown in FIG. 2 represents 1 bit and has 31 to 42.12 gates, so if it is a 16-bit adder, 12.times.16=192 gates are required.

Similarly, the number of gates for other blocks is calculated, and the total number is about 1100 gates. If the current per gate is 0.1 mA, the total current consumption is I, = o, 1 xl 100 = 110 mA, which becomes a very large value if the current of the peripheral circuit of the multiplier is included. If the power supply voltage is 6V, the power will be approximately 550 mW.

The multiplier of the present invention is concerned with a pipeline multiplier that significantly reduces circuit current and achieves low power consumption in view of the drawbacks of the conventional configurations described above. That is, by utilizing the fact that the signal transmission inside the multiplier is only unidirectional and there is no feedback, the circuit configuration is made by stacking up blocks made up of IIL, which greatly reduces the number of current buses from the power supply to the ground.

A third embodiment of the pipeline type 8-bit multiplier of the present invention is described below.
As shown in the figure.

FIG. 3 shows a multiplier with the same function as that in FIG. 1, and has a circuit structure stacked in seven stages. In this figure, the same numbers as in FIG. 1 indicate the same parts, and 51 to 58 indicate common lines.

When IILs are stacked, the output signal is easily transmitted to the upper stage, so the signal flow in FIG. 3 is from bottom to top, which is the opposite of FIG. 1. The ground 51 at the bottom is connected to the overall ground, and the injector 52 is connected to the ground of the adder 16. Similarly, injector 5 of adder 15
3 is connected to the ground 64 of the stage above it, and the injector 68 of the last resistor 20 is connected to the power supply.It is necessary to match the number of gates in each stage as much as possible to make the current per gate uniform. . Therefore, in this embodiment, the only adder stage having a large number of gates is the adder, and since the register 20 at the top stage is an output stage, one stage is composed of only the register 2o so that the gate current is large. Shift registers 1 and 2 for delaying the Y input signal, a decoder 6.6, and a selector 11.12 are arranged between the lowest injector 52 and the ground 61. An adder 16 is placed between the injector 63 and the ground 620 in the second stage.

, a decoder 7, a selector 13, a shift register 9, and a register 18 are arranged between the third-stage injectors 5 and 4 and the ground 63. Similarly, next time, adder 16 only.
On top of that, decoder 8, selector 14, shift register 1
0, place register 179, and finally place adder 1 and register 2o! The injector 68 of this resistor 2o is connected to a constant current source 66.

Next, each block will be explained in more detail.

FIG. 4 shows the configuration of shift registers 1 and 2 for Y input signals. Shift registers 1-2 in FIG. 3 are indicated by dotted lines in FIG. 61 is a 1-bit shift register. ,yO
~y7 represents each bit of the input signal Y, and the output, y, .
,y′4. , y; are delayed by the thick lock by the shift register 61, and y51, y61゛y7 are 2
This is a signal delayed by 7 clocks. yo to y3 are used directly without delay. y-4 is always 0. 6. The reason why the Y signal is delayed is that the additions in the adders 15 and 16 are performed sequentially according to the weight 22i in equation (2).

FIG. 5 shows one decoder among decoders 1-4.

IIL allows wired OR, so each bit can be input by four people. 71, 72, and 73° are 3-output inverters, and 74.75.76° and 77.78.79 are 1-output inverters.
This is an output inverter.

With this logic, ('2i-1+y2i
-2y214-+) and output terminals 80, 81.8
1 and 2 on 2.83 respectively. -2. -1 signals are obtained. That is, if it is 1, the terminal 80 is "H", if it is 2, the terminal 81 is "H"
If all, -2, the terminal 82 goes high; if -1, the terminal 83 goes high.

FIG. 6 shows one of the selectors 11.12, 13.14. Terminals 91.92.93.94 are input terminals for each bit of the input signal X, respectively. , x, , x2°I7 are input. , 95, 96, 97, 98 are gate signal input terminals from the decoder shown in FIG. 6, respectively. -2
．． -1 is input, the internal symbol is IIL of outputs 1 to 3
Inverter, output terminals 99, 100, 101.102,
103 is a partial product output terminal. Further, 104 is an inverter circuit.

Each bit x of input signal X. -x7 are each powered by three people, and one is an inverter 104 that generates two to three inverted signals.

It is controlled and output by a gate signal made from these Xi times signal Y signal. That is, if the gate signal is 1, the xi-fold signal is output as is, and if the gate signal is 2, the xi-fold signal is shifted to the left by 1 bit and output, and a partial product obtained by doubling the input signal X is output.

FIG. 7 shows a shift register for input signal X.

The parts indicated by dotted lines are the shift register 9 and the shift register 9 in FIG.
It is 10. Symbol 106 is a shift register. Each bit of the input signal type is delayed by one clock by the shift register 105, then further delayed by one clock by the selector 13 of FIG. 3, and then input to the selector 14 of FIG.

The above is the configuration of the present invention. Next, let us consider the power of this pipeline multiplier. The injector current in the upper stage passes through the ground terminal of this stage and becomes the injector current in the lower stage, so the current is equal in each stage. Now Adder 15,
If the injector current for 16 and 17.1 months is l1nj and the voltage applied to each stage is Vinj, the total power consumption Pd is Pd = 7 X Itnj XVinj = 7
l1nj mVinj. If Mini = 0.8, the voltage of the top injector is 7 Vinj
=5.6V. Generally, the power source is Vcc, and if a series resistor is connected to this to create a constant current, then
When Vcc = 7 V, the total power consumption Pd is Pd = Vcc X l1nj = 71inj. Now, assuming that there is no stacking like in the conventional IIL configuration, when Vcc = 5V, the power consumption P2 is P 2 = V
cc X 7 l1nj = 35 l1nj.

Therefore, the power consumption of the present invention is almost the same as that of the conventional configuration, and a significant reduction in power consumption can be achieved.

Next, a method of transmitting signals from the lower stage to the upper stage will be explained using the signal transmission from the selector to the adder in FIG. 8 as an example. This figure shows one bit of signal transmission from the selector 13 to the adder 16 in FIG. 53, 54.55 is the third
As shown in the figure, these are the injectors of the second, third, and fourth stages, and are also the grounds of the third, fourth, and fifth stages, respectively.

A constant current source having a PNP l-transistor configuration for each gate is omitted. As an example, a constant current source 106 of a PNP transistor is shown at the gate 31 of the full adder 16. Here, the numbers for the gates 31 to 42 of the adder 16 correspond to the gates in FIG. 2, and are assigned accordingly. Similarly, the gates 104a to 104d of the selector 13 are numbered to correspond to the gates in FIG.

107 is a control signal input terminal created from the human input signal Y, 108 is an input terminal for i bit and i+1 bit of the X input signal, gate 109 is an output gate of a selector,
110 is an output gate of the register 18, 111 is a carry input terminal from the lower bit, 112 is a carry output terminal to the upper bit, and 113 is a SUM output terminal of the adder. The carry input gate 42 is a carry output gate for the lower bit.

By connecting the collector of the output gate 109 of the selector to the bases of the gates 31, 33, 34, 38, and 40 of the full adder, a signal can be transmitted to the upper stage. To invert a gate, its base should be at ground or emitter potential.

Therefore, in this IIL configuration, when the transistor of gate 109 is turned on, the base of gate 31 is l'L
Since the potential is almost the same as that of the third stage ground 53, the transistor of the gate 31 is completely cut off. At this time, the base voltage of the gate 31 is 10, S with respect to the emitter.
It will be about V. Therefore, the amplitude of the base is twice the normal amplitude.

Therefore, the time required to charge the parasitic capacitance becomes longer, and the switching time becomes proportionally longer. If switching time becomes a problem, insert a diode between the collector of gate 109 and the base of gate 31, etc.
A circuit configuration that reduces the base amplitude may be used.

As described above, the multiplier of the present invention utilizes the fact that there is no feedback in the signal transmission of the multiplier and the fact that the circuit for upward transmission of the signal is simple in the stacked IIL structure, and the multiplier is a pipeline type multiplier. It has high industrial value because it can significantly reduce power consumption.

Although the above embodiment is a seven-stage multiplier, if the power supply voltage is as low as about 5 V, the number of stacked stages can be reduced by changing the combination in the configuration shown in FIG.

It goes without saying that it is also possible to weight the injector current flowing through each gate and speed up the overall process with the same current.

[Brief explanation of drawings]

Figure 1 is a conventional configuration diagram of an 8-bit pipelined multiplier, Figure 2 is a full adder diagram of an IIL configuration, Figure 3 is a circuit diagram of a pipelined multiplier with a stacked IIL configuration of the present invention, and Figure 4. is a shift register configuration diagram for X input signal delay, FIG. 5 is a Tecoder configuration diagram, FIG. 6 is a configuration diagram of a selector circuit, FIG. 7 is a shift register configuration diagram for X input signal delay, and FIG. 8 is a diagram of the shift register configuration diagram of the present invention. A specific circuit diagram of a stacked NIL configuration is shown. 1-2...Shift register, 6-8...
・Decoder, 9-1o...Shift register, 1
1-14...Selector, 16-17...
・Adder, 18-20...Register, 21...
...Y input terminal, 22...X input terminal, 23.
...Multiply output terminal, 51-58...Common line. Name of agent: Patent attorney Toshio Nakao and 1 other person11
Figure 2 4j Figure 4-N ~ ~

Claims (1)

[Claims] It has a structure in which functional blocks of IIL configuration are stacked in multiple stages, the injector of the previous stage is connected to the ground terminal of the next stage, and the signal is transmitted from the functional block of the previous stage to the functional block of the next stage. A parve line multiplier with .