JPS6170634A - Shifting circuit - Google Patents

Abstract

PURPOSE:To obtain a shifting circuit of simple circuit constitution which operates at a high speed by connecting basic cells into array constitution based upon a two-input one-output type data selector. CONSTITUTION:Opposite-polarity signals are inputted to control lines 206 and 207 of a basic cell to select an input signal line 204 and sends an output to an output line 208 when the control line 206 is at '1'. When a 16-input 8-output parallel shifter is composed of basic cells, data to be shifted is inputted from 350, base cells of the 1st stage are controlled through control lines 321 and 322 and send their output to the 2nd stage, and sequential shift control up to the 4th stage is performed, thereby obtaining an output. Control lines of each stage are supplied with outputs of respective bits of the shift data (four bits) and outputs having the opposite polarities in pairs and -3 corresponds to 1101 (complementary number), so each control input is 10100110.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a shift circuit, and in particular, shift data and shifted data are expressed in two's complement representation, and the shifted data has many pits. It is suitable for implementing a high-speed shift circuit with many bits on a single-chip integrated circuit.

Structure of a conventional example and its problems An example of a conventional shift circuit (hereinafter, the shift circuit according to the present invention will be referred to as a barrel shifter) is shown in FIG. The barrel shifter shown in FIG. 1 has a transistor matrix configuration in which the data to be shifted is 16 bits, the shift data is 14 bits, and the output is 8 bits. 10 in Figure 1
1 to 116 are shifted data input signal lines, 131 and 138 are output signal lines, and 140 to 163 are shift control signal lines. In the barrel shifter with the transistor matrix configuration shown in FIG. 1, the number of bits of the data to be shifted is
As the number of bits of shift data increases, the number of transistors is proportional to the product of the number of bits of shifted data and the number of bits of shift data, resulting in a very large circuit scale.

Furthermore, the number of transistors connected to one input signal line and one output signal line increases, the source capacitance and drain capacitance of the transistors parasitic to each input/output signal line become large, and the operating speed of the circuit decreases. Become slow.

Further, as can be seen from FIG. 1, three layers of wiring are required for input, output, and control signals, making the wiring layout difficult. The control signal must be generated by decoding the input shift data in two's complement representation, and a decoding circuit is required.

OBJECTS OF THE INVENTION The present invention solves the above-mentioned problems and provides a shifter circuit with a simple circuit configuration and capable of high-speed operation.

Structure of the Invention The present invention uses a 2-input, 1-output type data selector as a basic cell, arranges the basic cells in a number based on the number of bits of shifted data to form a unit cell string, and uses this unit cell string as a shift data bit. A shift circuit is provided in the same number of stages as the number of bits, and has a circuit configuration in which the output of the basic cell is coupled to the input of the basic cell in the next stage, thereby forming a unit cell column with an array configuration of basic cells. This makes it possible to simplify the configuration and arrangement, and further improve high-speed operation performance.

DESCRIPTION OF EMBODIMENTS Next, the present invention will be explained using an embodiment. FIG. 2 is an example of a basic cell of a 2-input 1-output data selector constituting a barrel shifter, 201 and 202 are AND circuits, 20
3 is an OR circuit, 204 and 205 are input signal lines, 206.
207 is a control signal line, and 208 is an output signal line. When configuring this basic cell, the control lines 206 and 207 are connected to each other when the basic cells are arranged horizontally. A signal of opposite polarity is input to the control lines 206 and 207. When the control line 206 is at the no-y level (hereinafter, according to the positive logic rules of binary arithmetic, the high level is expressed as 1" and the low level is expressed as "\"), the signal on the input signal line 204 is selected and the signal is sent to the output signal line 208. When the control line 207 is n11+, the signal on the input signal line 205 is selected and output to the output signal line.

Figure 3 shows a cell system constructed by the basic cells shown in Figure 2.
This is an example of a 6-input, 8-output barrel lid, with MSB
Using the bits as a reference, it is possible to shift by 1,003 bits or 1,12 bits, and after the shift, the upper 6 bits and lower 2 bits are discarded, and an 8-bit output is performed.

Let us now assume that the shifted data is a person and the shifted data is B. If the shifted data and shift data B are expressed in two's complement numbers, then the shifted data A and shift data B are expressed as formula (1),
It is expressed as (2).

A -Hea ・2 +a ・2 +
・・・・・・＋a ・2+a ・・・－・・・・・・
...(1) B: *b・23+b・22+b・2+
b ... Song... (2) (*a, *b are sign bits) As an example of the explanation, B:1101 (-3) and B-
Consider the case of 0111(7). 4 and 5 are tables showing the input of the barrel shifter shown in FIG. 3 and the output of the basic cells in each stage. The output of the 1st stage of the basic cell of the barrel shifter is 351. The 3rd stage is the output of the 2nd stage of the basic cell of the barrel shifter 352. The 4th stage is the output of the 3rd stage of the basic cell of the barrel shifter 363. The 5th stage is the output of the barrel/lid. It represents 354. Figure 4 shows 7 when the number of shifts is -3.
The signals on the :1 control lines 321 to 328 in FIG.

Pa1″, “1”, pa\″, “′\” 11, 11,
111”.

It is “＼”. In the barrel shifter shown in FIG. 3, when a positive shift is performed, a \ is added to the lower bits, and when a negative shift is performed, a sign bit is corrected to the upper bits. -3 with the barrel shifter in Figure 3
When this shift is performed, the upper two bits of the output become sign bits, and the subsequent bits are a total of 8 bits, 7 bits from the lower 12 bits of the input.

When performing 17 shifts with the barrel shifter shown in FIG. 3, the control signals 321 to 328 are \11 and 1+, respectively.
,”,”\IT, II IT, II\”.

“°1”, \”, 1”. The state of the software in this case is as shown in FIG. 5, where the lower 3 bits of the input are output to the upper 3 bits of the output of the barrel shifter, and °C is output to the lower 6 bits of the output.

Figure 6 shows the circuits 601 to 6 that control the barrel/lid.
04 is an inverter circuit, 611 to 614 are /ft data input signal lines, and 321 to 328 are control signal lines for the barrel 7 lid shown in FIG. In the circuit shown in Figure 6, shift data can be input in two's complement representation, with the MSB being 614 and L
Input SB to 611. In this case no special decoding is required.

As described in detail, according to the present invention, a nofter circuit can be constructed from only basic cells, and the basic cells can be connected in an array configuration, allowing for efficient design, and shifting can be done in several stages of basic cells. It can be done fast. Also,
When the shifted data and shift data are expressed in two's complement, control is very easy, no decoding circuit is required, and the system is suitable for semiconductor integration.

[Brief explanation of the drawing]

, Fig. 1 is a diagram of a conventional 16-input 8-output barrel shifter, Fig. 2 is a basic cell circuit diagram constituting a barrel shifter according to an embodiment of the present invention, and Fig. 3 is a diagram of a 16-input 8-output barrel shifter according to an embodiment of the present invention. Output barrel lid configuration diagram, Figure 4 is an output state diagram showing the input/output of the barrel shifter shown in Figure 3 and the output of each stage of the basic cell, the state diagram when -3 is entered as the shift number, Figure 5 is the shift diagram. State diagram when +7 is entered in the number,
FIG. 6 is a control signal forming circuit diagram of the barrel shifter shown in FIG. 3. 101 to 116...--Shifted number input signal line, 1
31-138...Output signal line, 140-153.
...Shift control signal line, 201.202...
...AND circuit, 203...○R circuit, 204.
205... Input signal line, 206.207...
...Control signal line, 208...Output signal line, 30
1~316...Shifted number input signal line, 321~
328...Control signal line, 331-338...
...Output signal line, 350...Input signal, 351
...1st stage output, 362...2nd stage output, 353...3rd stage output, 354...
・Output, 601 to 604...Inverter circuit,
611 to 614...Shift number input signal lines. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3jJIJJ7. ．． 1jl Yugeto 4 Yo Illusion JJI dJ/
j Hiroshi Figure 6 1. o4 32 otsu

Claims (1)

[Claims] A 2-input 1-output data selector is used as a basic cell, and the basic cells are arranged in a number based on the number of bits of the data to be shifted to form a unit cell string, and this unit cell string is provided in the same number of stages as the number of bits of the shifted data. A shift circuit with a circuit configuration in which the output of a basic cell is coupled to the input of the next basic cell.