JPH01237823A - Shift circuit - Google Patents

Abstract

PURPOSE:To simplify circuit constitution and to perform fast shift in both positive and negative directions by setting a three-input/one-output data selector as a basic cell, and constituting a unit cell by setting the same number of those cells as that of data bits in parallel. CONSTITUTION:The basic cell of the three-input/one-output data selector comprising a shift circuit is constituted of three AND circuits, an OR circuit, control signal lines, and an output signal line. The control signal lines 108, 109, and 110 connect the basic cells arranged in a lateral direction. A high level signal is inputted to either the control signal lines 108, 109, and 110. When the control signal line 108 is '1', the signal of an input signal line 105 is selected, and is outputted to the output signal line 111. When the control signal line 109 is '1', an input signal line 106 is selected and outputted to the output signal line 111. When the control signal line 110 is '1', an input signal line 107 is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a shift circuit, and particularly a shift circuit in which shift data and shifted data are expressed in two's complement representation.
It is suitable for realizing a high-speed shift circuit having a shift function in both positive and negative directions with a single-chip integrated circuit.

(Prior Art) Conventionally, this type of shift circuit has been configured with a matrix of transistors. An example of a conventional shift circuit is shown in FIG. The shift circuit shown in FIG. 3 is composed of a transistor matrix having 8 bits of shifted data, 8 bits of shift data, and 8 bits of output. In FIG. 3, 301-308 are shifted data input signal lines, 311-318 are output signal lines, and 321-328 are shift control signal lines.

The operation of this circuit will be explained below. Shifted data in two's complement representation is input to the shifted data input signal lines 301 to 308. The shift data is input to a decoding circuit (not shown), decoded, and one of the shift control signal lines 321 to 328 is selected. The decoding circuit has a function of decoding shift data and selecting one of the shift control signals. Shift control signal line 3
When one of 21 to 328 is selected, the transistor connected to the selected shift control signal line becomes conductive, and the shifted data input signal line 30 is connected to the output signal lines 311 to 318.
The shifted data 1 to 308 are shifted and output. In the shift circuit shown in Fig. 3, the data on the output signal line is two's complement data; in a positive shift, the lower bit becomes 0, and in a negative shift, the upper bit becomes a sign bit (shifted data input signal line 308 data).

(Problem to be Solved by the Invention) In such a conventional configuration, as the number of bits of the shifted data and the number of bits of the shifted data increase, the number of transistors becomes larger than the number of bits of the shifted data and the number of bits of the shifted data. Since it is determined in proportion to the product, the circuit size becomes extremely large. Additionally, one shifted data input signal line, 1
The number of transistors connected to each output signal line increases, the source capacitance and drain capacitance ff (in the case of MOS transistors) of the transistors parasitic to each input/output signal line become large, and the operating speed of the circuit becomes slow.

Furthermore, regarding a decoding circuit that decodes shift data and outputs a shift control signal, the circuit scale increases in proportion to a power of two as the number of bits of shift data increases.

To realize the circuit shown in Figure 3 with an integrated circuit, input.

Three layers of wiring are required for each output and control signal.
Wiring layout is difficult.

The present invention solves these problems.

The present invention provides a shift circuit having a simple circuit configuration, capable of high-speed operation, and having a shift function in both positive and negative directions.

(Means for Solving the Problems) In order to achieve the above object, the present invention uses a 3-input 1-output data selector as a basic cell, and arranges the basic cells into a unit cell string in a number based on the number of bits of data to be shifted. , the unit cell string is provided with one stage less than the number of bits when the shift data is expressed as two's complement, and the circuit configuration is such that the output of the basic cell is connected to the input of the next basic cell, and .

This is a shift circuit that has a shift function in both negative directions.

(Function) With the above configuration, the present invention is composed of only the basic cell of the 3-input 1-output data selector, so the circuit configuration is simple and the shift function in both the positive and negative directions enables high-speed operation. A shift circuit having the following can be realized.

(Example) A shift circuit of the present invention will be explained using an example. 1st
The figure shows an example of a basic cell of a 3-input, 1-output data selector that constitutes a shift circuit, and 101°, 102, and 103 are A
ND circuit, 104 is OR circuit, 105° 106, 107
is the input signal line, 108.109.110 is the control signal line,
111 is an output signal line. Control signal line 108°109
, 110 are connected to each other when the basic cells are arranged horizontally. Control signal line 108°109,
110, one of them is high level (hereinafter, according to the binary arithmetic positive logic rule, high level is 1''').

A low level signal (indicated by "0") is input. When the control signal line 108 is It L II, the input signal line 1
The signal 05 is selected and output to the output signal line 111. When the control signal line 109 is "1", the input signal line 106
is selected and output to the output signal line 111. When the control signal line 110 is 1'', the signal on the input signal line 107 is selected and output to the output signal line 111.

FIG. 2 shows an example of an 8-input, 8-output shift circuit composed of the basic cells shown in FIG.
Based on the bits of B, it is possible to shift from 4 bits in the positive direction to 4 bits in the negative direction, that is, from +4 bits to 14 bits, and in the case of a shift in the negative direction, the sign of the MSB bit of the input data Bits enter the upper bits that are emptied by a negative shift. In the case of a positive shift, “
O” is inserted.

In FIG. 2, 201 to 208 are shifted data input signal lines, 211 to 219 are shift control signal lines, and 221 to 228 are shift control signal lines.
is the output signal line.

The basic cell in FIG. 2 is the three-input, one-output data selector shown in FIG. 1, and the input and output positions of each signal line match. The first row of unit cells in which eight basic cells are arranged horizontally has +1 bit and 0 bit.

This is a circuit that performs a -1 bit shift, and the unit cell string in the second stage shifts +2 bits, 0 bits, and -2 bits, and the unit cell string in the third stage shifts +4 bits, O bits, and -4 bits.
Shift bits. Three shift control signal lines 211 to 213 and 214 to each connected to the unit cell column of each stage
216, 217 to 219 are decoded by a decoding circuit (not shown) that decodes the shift data.
In the unit cell column of the 6 first stage where a book is selected, when the shift control signal line 211 is selected, a shift of 11 bits is performed, and when the shift control signal line 212 is selected, a shift of 0 bits is performed.
When shift control signal line 213 is selected, a +1 bit shift is performed. In the second stage unit cell column, when the shift control signal line 214 is selected, a 12-bit shift is performed, when the shift control signal line 215 is selected, a 0-bit shift is performed, and when the shift control signal line 216 is selected, a 0-bit shift is performed. In the third stage unit cell column that performs a +2-bit shift, when the shift control signal line 217 is selected, a 14-bit shift is performed, and when the shift control signal line 218 is selected, an O-bit shift is performed, and the shift control signal When line 219 is selected, a shift of +4 pits 1.about. is performed.

The shift result of the sum of the shift numbers of the unit cell columns in each stage is output to the output signal lines 221 to 228.

In the shift circuit shown in FIG. 2, by performing a shift operation in three stages of unit cell columns, it is possible to shift any bit between +7 bits and 17 bits.

(Effects of the Invention) According to the shift circuit of the present invention, the shift circuit can be constructed only from basic cells, and the basic cells can be connected in an array, allowing for efficient design, and moreover, shifting can be performed in several stages of basic cells. It is fast because it can be done. Furthermore, the circuit for decoding shift data can be simpler than the decoding circuit of a shift circuit having a matrix structure of transistors, and is suitable for semiconductor integration.

[Brief explanation of the drawing]

FIG. 1 is a basic cell circuit diagram constituting a shift circuit according to an embodiment of the present invention, FIG. 2 is a configuration diagram of an 8-input 8-output shift circuit according to an embodiment of the present invention, and FIG. 3 is a diagram of a conventional 8-input shift circuit. FIG. 2 is a configuration diagram of an input 8 output shift circuit. 101-103...AND circuit, 104...OR
Circuit, 105~107... Input line 4g, 108~
110... Control signal line, 111... Output signal line,
201 to 208...shifted data input signal lines,
211-219...Shift control signal line, 221-2
28... Output signal line, 301-308... Shifted data input signal line, 311-318... Output signal line, 321-328... Shift control signal line. Patent Applicant: Matsushita Electric Industrial Co., Ltd. Figure i Go to 101 103゛・AND times 104・・OR times 05~107 ・・Input 3 squares 108~+10・louis 11−・bu jj〦8 relationship

Claims (1)

[Claims] The number of bits when a 3-input 1-output data selector is used as a basic cell, the basic cells are arranged in a number based on the number of bits of the data to be shifted to form a unit cell string, and the unit cell string is expressed as a two's complement of the shifted data. 1. A shift circuit characterized in that the circuit is configured such that the basic cell has one less stage, the output of the basic cell is coupled to the input of the next basic cell, and has a shift function in both the positive direction and the negative direction.