JP2563519B2 - Shift circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift circuit, and in particular, shift data and shifted data are represented by a two's complement representation, and the shift data has a large number of shifts and the forward direction. , It is suitable for realizing a high-speed shift circuit having a negative-direction shift function and a bit reverse order function with a one-chip integrated circuit.

2. Description of the Related Art Conventionally, this type of shift circuit has a structure of a matrix of transistors. An example of a conventional shift circuit is shown in FIG. The shift circuit of FIG. 4 is a shift circuit having a transistor matrix configuration having a bit reverse order function of 8 bits for data to be shifted, 9 bits for shift control signal, and 8 bits for output. In FIG. 4, 101 to 108 are shifted data input signal lines, 121 to 129 are shift control signal lines,
111 to 118 are output signal lines.

Hereinafter, the operation of this circuit will be described. To the shifted data input signal lines 101 to 108, shifted data represented by two's complement is input. The shift data is input to a decoding circuit (not shown) and is decoded to select one of the shift control signal lines 121 to 129. The decoding circuit has a function of decoding shift data and selecting one shift control signal line. In the shift control signal lines 121 to 129, when the shift control signal lines 121 to 124 are selected, a positive shift is performed, and when the shift control signal line 125 is selected, a 0 bit shift is performed, and the shift control signal line 126. If .about.128 is selected, negative shift is performed, and if the shift control signal line 129 is selected, reverse bit order is performed. When one of the shift control signal lines 121 to 129 is selected, the transistor connected to the selected shift control signal line becomes conductive and the output data lines 111 to 118 are connected to the shifted data input signal line 10.
The shifted data of 1 to 108 is shifted or output in bit reverse order. In the shift circuit of FIG. 4, the data on the output signal lines 111 to 118 is 2's complement data, and the lower bit is 0 in the positive shift, and the upper bit is the sign bit (shifted bit) in the negative shift. Data on the data signal line 108).

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In such a conventional configuration, when the number of bits of the shifted data and the number of bits of the shift data (the number of bits of the shift control signal) increase, the number of transistors in the transistor matrix becomes larger than that of the shifted data. Since it is determined in proportion to the product of the number of bits and the number of bits of shift data, the circuit scale becomes very large. Furthermore, the number of transistors connected to one shifted data input signal line and one output signal line increases, and the source capacitance and drain capacitance of the transistor parasitic on each input / output signal line (in the case of a MOS transistor, ) Is large, the operation speed of the circuit becomes slow.

Also, in the decoding circuit that decodes shift data and outputs a shift control signal, the circuit scale increases in proportion to a power of 2 as the number of bits of shift data increases.

In order to realize the circuit of FIG. 4 with an integrated circuit, wiring of three layers is necessary for each signal of input, output, and control, and the wiring layout is difficult. Regarding the transistors, the layout is difficult because the transistors connected to the shift control line 129 that perform the bit reverse order differ from the rules of the array of transistors that perform other shifts.

The present invention solves such a problem, has a simple circuit configuration, and has a shift function in both positive and negative directions capable of high-speed operation. A shift circuit that performs reverse order is provided.

Means for Solving the Problems In a shift circuit of the present invention, a 3-input 1-output data selector is used as a basic cell, and the basic cells are arranged in a number based on the number of bits of data to be shifted to form a unit cell row. The column is provided with one stage less than the number of bits when the shift data is represented by 2's complement, and the circuit configuration in which the output of the basic cell is coupled to the input of the basic cell of the next stage is provided in both positive and negative directions. A shift circuit having a shift function and performing a reverse bit order by utilizing the shift function in both directions.

Operation With this configuration, the shift circuit is configured with only the basic cells of the 3-input 1-output data selector, has a simple circuit configuration, has a shift function in both the square direction and the negative direction that can operate at high speed, and has a bit reverse order function. A circuit can be realized.

Embodiment A shift circuit according to the present invention will be described with reference to an embodiment. FIG. 1 is an example of a basic cell of a 3-input 1-output data selector that constitutes a shift circuit. 201, 202, 203 are AND circuits, 20
4 is an OR circuit, 205, 206 and 207 are input signal lines, 208, 209 and 210 are control signal lines, and 211 is an output signal line. Control signal line 208,2
A high level signal (hereinafter, a high level is represented by "1" and a low level is represented by "0" according to the binary logic positive logic rule) is input to any one of 09 and 210. When the control signal line 208 is “1”, the signal of the input signal line 205 is selected and output to the output signal line 211. When the control signal line 209 is “1”, the signal of the input signal line 206 is selected and output to the output signal line 211. Input signal line 2 when control signal line 210 is "1"
The signal 07 is selected and output to the output signal line 211.

FIG. 2 shows an embodiment of an 8-input, 8-output shift circuit composed of the basic cells shown in FIG.

The input signal line 205 shown in FIG. 1 is the first input signal line, the input signal line 206 is the second input signal line, and the input signal line 207 is the third input signal line.

As shown in FIG. 2, eight basic cells each having three inputs and one output are arranged to form a unit cell row, and an output signal line of the unit cell row is connected to an input signal line of the unit cell row of the next stage to form a unit cell row of three stages. Are configured.

Then, the first basic cell of the unit cell row in the first row is
The first-bit shifted data input signal line 308 is coupled to the first input signal line, and the eighth basic cell has the ground electrode coupled to the third input signal line.

Then, the first input signal line of the first basic cell of the unit cell row of the first stage to which the shifted data input signal line 308 is coupled and the shifted data input signal line 301 are coupled to 1 Of the input signal lines of the first to eighth basic cells, excluding the third input signal line of the eighth basic cell of the unit cell row in the tier, the first, second, and
Shifted data input signal lines 308 and 30 are connected to the third input signal line.
7 and 306 are connected respectively. In the third basic cell, the shifted data input signal lines 307, 306, 305 are coupled to the first, second, and third input signal lines, respectively. The same applies to the third to seventh basic cells. For the first basic cell, the shifted data input signal lines 308, 308, 307 are connected to the first, second and third input signal lines.
In the eighth basic cell, the shifted data input signal lines 302 and 301 and the ground electrode are connected to the first, second and third input signal lines, respectively.

The 1st to 2nd basic cells of the unit cell row of the 2nd stage are formed by connecting the output signal lines of the 1st basic cell of the 1st stage to the 1st input signal line. In the 7th to 8th basic cells, the ground electrode is coupled to the third input signal line.

Further, the first to fourth basic cells in the unit cell row in the third stage are formed by connecting the output signal lines of the first basic cells in the second stage to the first input signal lines. In the fifth to eighth basic cells of No. 3, the ground electrode is coupled to the third input signal line.

Then, among the unit cell columns excluding the first stage (second stage to third stage), the second stage 1-2 (= 2 ^(x-1) ) third stage 1-4 (= The first input signal line of the 2 ^(3-1) ) th basic cell and 7 (= 2 ³ −2 ^(2-1) +1) to 8 (=
2 ³ ) th, 3rd stage 5 (= 2 ³ -2 ^(3-1) +1) to 8 (=
Regarding the input signal lines of the basic cells except the third input signal line of the 2 ³ ) th basic cell, the output signal lines of the preceding basic cells are combined as follows.

Explaining with a specific example, 3 of the unit cell row in the second stage
Regarding the second basic cell, the output signal lines of the second, third and fourth basic cells of the unit cell row of the first stage are respectively coupled to the first, second and third input signal lines. .

Then, five control signal lines are connected to each unit cell row, and the control signal lines are connected as follows.

The unit cell sequence in the third row will be described as an example. If the basic cells of the unit cell sequence are set to a basic cell group in units of 8 (= 2 ³ ) bits, the first to fourth cells of the basic cell group of each unit cell sequence will be described. {= (1/2) · 2 ^3} to th basic cell, the control signal line 32
1, 323 and 324 are connected, and control signal lines 322, 323 and 325 are connected to the remaining basic cells (5th to 8th basic cells). Then, when the control signal line 321 or 322 is selected, the basic cell selects the first input signal line, and when the control signal line 323 is selected, the second input signal line is selected.
When the control signal 324 or 325 is selected, the third input signal line is selected.

The shift circuit configured as described above can shift from 7 bits in the positive direction to 7 bits in the negative direction, that is, from +7 bits to -7 bits based on the MSB bit, and shifts in the negative direction. In the case of shift, the sign bit of the MSB bit of the input data enters the upper bit which becomes empty by the negative shift. In the case of positive shift, "0" is put in the lower bit that is emptied by positive shift.

In FIG. 2, 301 to 308 are shifted data input signal lines, 311
325 are shift control signal lines, and 331 to 338 are output signal lines.

In the above embodiment, the shifted data input signal line 30
8 is the first shifted data input signal line, the shifted data input signal line 307 is the second shifted data input signal line, ..., and the shifted data input signal line 301 is the eighth shifted data input signal line. It is used as a data input signal line.

The basic cell in FIG. 2 is the 3-input 1-output data selector shown in FIG. 1, and the input / output positions are the same. The unit cell row of the first stage in which eight basic cells are arranged in the horizontal direction is shifted by +1 bit, 0 bit, −1 bit, and adjacent two.
Bits are swapped. The unit cell row in the second stage has +2 bits, 0 bits, -2 bits of shift, and continuous 4 bits, with the upper 2 bits and the lower 2 bits.
Swap bits. The unit cell row in the third stage is +4 bits, 0 bits, -4 bits shift, and 8 consecutive
Regarding the bits, the upper 4 bits and the lower 4 bits are exchanged. Each of the five shift control signal lines 311 to 315, 316 to 320, 321 to 325 connected to the unit cell row of each stage is one or two of the five shift control signal lines 311 to 315, 316 to 320, 321 to 325 by a decoding circuit (not shown) for decoding shift data. Is selected. In the unit cell row of the first stage, if the shift control signal lines 311 and 312 are selected, -1 bit shift is performed, and if the shift control signal line 313 is selected, 0 bit shift and shift control signal lines 314 and 31 are performed.
When 5 is selected, +1 bit shift is performed. Further, when the shift control signal lines 312 and 315 are selected, the bits of the adjacent two bits are exchanged. When the shift control signal lines 316 and 317 are selected in the unit cell row of the second stage, -2
When the bit shift / shift control signal line 318 is selected, 0 bit shift is performed, and when the shift control signal lines 319 and 320 are selected, +2 bit shift is performed. Also, when the shift control signal lines 317 and 320 are selected, for consecutive 4 bits,
The upper 2 bits and the lower 2 bits are exchanged. In the unit cell row of the third stage, when the shift control signal lines 321 and 322 are selected, -4 bit shift is performed, and when the shift control signal line 323 is selected, 0 bit shift and shift control signal lines 324 and 32 are performed.
When 5 is selected, +4 bit shift is performed. When the shift control signal lines 322 and 325 are selected, the upper 4 bits and the lower 4 bits of the 8-bit output of the unit cell row in the second stage are switched. In the shift circuit of FIG. 2, the shift control signal lines 312, 315, 317, 320,
322 and 325 are selected, and during the shift operation, the shift control signal lines 311 and 312 or 313 or 314 and 315 are selected for the shift control of the unit cell row of the first stage, and the shift control signal line 316 is selected.
And 317 or 318 or 319 and 320 are selected for shift control of the second unit cell row, and shift control signal lines 321 and 322 or 323 or 324 and 325 are selected for shift control of the third unit cell row. It In the shift circuit of FIG. 2, during the shift operation, the shift result of the total number of shifts in the unit cell row of each stage is output to the output signal lines 331 to 338. As described above, the shift circuit shown in FIG. 2 can perform the shift operation of any bit between +7 bit and -7 bit and the bit reverse order operation.

FIG. 3 is a state diagram showing the states of the input / output signals of the unit cell row of each stage when the bit reverse operation is performed in the shift circuit of FIG. 2, and 401 to 404 are the unit cell row bit states.
Reference numeral 401 shows the state of each signal line of the shifted data input signal line in FIG. Reference numeral 402 shows the output state of the unit cell row of the first stage of FIG. 2, and 403 shows the output state of the unit cell row of the second stage of FIG. Reference numeral 404 indicates the output of the unit cell row at the third stage in FIG. 2, that is, the state of the output signal lines 331 to 338. Between 401 and 402 in the state diagram of FIG. 3, that is, in the first unit cell row of FIG. 2, a shift function of +1 bit and −
Adjacent two by the combination of 1-bit shift function
Swap bits with respect to each other. Between 402 and 403 in the state diagram of FIG. 3, that is, in the unit cell row in the second stage of FIG. 2, by combining the +2 bit shift function and the −2 bit shift function, the upper 2 bits of the continuous 4 bits are combined. And the lower 2 bits are exchanged. Between 403 and 404 in the state diagram of FIG. 3, that is, in the unit cell string of FIG. 2, by combining the +4 bit shift function and the -4 bit shift function, the upper 4 bits and the lower 4 bits can be set for consecutive 8 bits. Replace. By using the above shift functions in combination, the bit reverse order function can be realized as shown in the unit cell column bit state 404.

In the above embodiment, only the shift circuit for shifting the 8-bit shifted data has been described, but it goes without saying that the same effect can be obtained even if the shifted data is 2 ^n- bit data.

EFFECTS OF THE INVENTION According to the shift circuit of the present invention, the shift circuit can be configured only by the basic cells, the basic cells can be connected in array, and the design can be efficiently performed. It is fast because it can implement the reverse order function. It also controls the shift circuit. Also in the circuit for decoding the shift data, the circuit can be simplified as compared with the decode circuit of the shift circuit having a matrix structure of transistors, and there is an effect that it is suitable for semiconductor integration.

[Brief description of drawings]

FIG. 1 is a basic cell circuit diagram which constitutes a shift circuit according to an embodiment of the present invention, FIG. 2 is a configuration diagram of an 8-input 8-output shift circuit according to an embodiment of the present invention, and FIG. 3 is a shift shown in FIG. FIG. 4 is a state diagram when the circuit performs the bit reverse order operation, and FIG.
It is a block diagram of an input 8-output shift circuit. 101 to 108 …… Shifted data input signal line, 111 to 118 ……
Output signal lines, 121 to 129 ...... Shift control signal lines, 201 to 203
…… AND circuit, 204 …… OR circuit, 205 to 207 …… input signal line, 208 to 210 …… control signal line, 211 …… output signal line, 301
~ 308 …… Shifted data input signal line, 311 ～ 325 …… Shift control signal line, 331 ～ 338 …… Output signal line, 401 ～ 404…
... Unit cell column bit state.

Claims (1)

(57) [Claims] 1. A shift circuit for shifting 2 ⁿ (n is a natural number of 2 or more) bits of shifted data, 2 ⁿ basic cells each having 3 inputs and 1 output are arranged to form a unit cell row,
The output signal line of the unit cell row is connected to the input signal line of the unit cell row of the next stage to form an n-stage unit cell row, and the first basic cell of the first-stage unit cell row is the first bit. The shifted data input signal line is connected to the first input signal line, the 2 ^nth basic cell is connected to the ground electrode to the third input signal line, and the first basic cell of the unit cell row of the first stage is connected. a first input signal line of the cell, and, for an input signal line of the 2 ⁿ th third y except input signal lines (y is a natural number of less than 2 ⁿ⁾ th basic cell of the basic cell, the first , (Y−1), y, and (y + 1) th bit shifted data input signal lines are respectively coupled to the second and third input signal lines, and x (x is 2 or more and x ≦ n is satisfied. The 1st to 2 ^(x-1) th basic cells in the unit cell row of the ⁽ natural number) stage are connected to the first input signal line of the first basic cell of the preceding stage. The output signal line is coupled, and the (2 ⁿ −2 ^(x−1) +1) to 2 ⁿ th basic cell of the unit cell row of the ^{x- th} stage is coupled with the ground electrode to the third input signal line, 1 to 2 ^{(x-1) of the} unit cell row excluding the first row
The first input signal line of the th basic cell and the (2 ⁿ −
The input signal line of the y-th basic cell excluding the third input signal line of the 2 ^n- th basic cell from 2 ^(x-1) +) is
The second and third input signal lines have (y-2 ^(x-1) ), y, and
The output signal lines of the (y + 2 ^(x-1) ) th basic cell are connected to each other, and five control signal lines are connected to the unit cell row, and the basic cell of the ^x-th unit cell row is connected to the ^2x When the basic cell group is defined in bit units, the first, third, and fourth control signal lines are connected to the first to (1/2) · 2 ^xth basic cells of the basic cell group of each unit cell row. The second, third, and fifth control signal lines are connected to the remaining basic cells, and when the first or second control signal line is selected, the basic cell selects the first input signal line. A shift circuit characterized by selecting the second input signal line when the third control signal line is selected and selecting the third input signal line where the fourth or fifth control signal is selected. .