JP2771687B2 - Decoding circuit - Google Patents

Description

The present invention relates to a decoding circuit used in a semiconductor memory device.

(B) Conventional technology Generally, in a memory device having a semiconductor configuration, memory cells each including one to an appropriate number of transistors are arranged in a matrix, and rows and memory cells of the memory cells are arranged in accordance with address information from the plurality of memory cells. A column is specified. The specification of the memory mole row and the memory column is performed by selectively turning on the switching transistor in accordance with a selection signal obtained by decoding the address information.

FIG. 2 is a logic diagram of a row decoder for selecting a memory cell row.

A plurality of units (1) provided in parallel form a pair
It comprises NOR gates (2) and (3), and the outputs of these NOR gates (2) and (3) are output as selection signals RS ₁ and RS ₂ via inverters (4) and (5), respectively. Each unit (1) is associated with a data line (6) having a bit number corresponding to the number of units (1) on a one-to-one basis, and each data line (6) is associated with each NOR gate (2) (3). ) Is connected to the input side. The data line (6) is supplied with a first address decode signal AD ₁ for selecting unit (1), and therefore one of a plurality of units (1) are specified. Further, a 2-bit data line (7) is associated with each unit (1), and the 2-bit data line (7) is connected to the input sides of the NOR gates (2) and (3), respectively. The data line (7), a second address decode signal AD ₂ of the 2-bit configuration is given, the first address decode signal AD ₁
Signals RS ₁ and RS _{2 of the} unit (1) selected according to
Is selected. Therefore, in such a row decoder, n-bit + 2-bit data lines (6) (7)
Allows 2n rows to be specified.

 FIG. 3 is a circuit diagram of the unit (1).

Each of the NOR gates (2) and (3) includes two P-channel MOS transistors (T _P1 ) (T _P2 ) connected in series between the power supply and the output side, and a parallel connection between the output side and the ground. Two connected N-channel MOS transistors (T _N1 )
(T _N2 ), the gates of P-channel and N-channel MOS transistors (T _P1 ) and (T _N2 ), and the P-channel and N-channel MOS transistors (T _P2 )
The input signal is supplied to the gate of (T _N1 ). Therefore,
One unit (1) is composed of four P-channel MOS transistors and four N-channel MOS transistors.

(C) Problems to be solved by the invention By the way, it is desired that the row decoder provided for each memory cell row has a simplified circuit configuration in order to reduce the arrangement pitch of the memory cells. Particularly, in a read-only memory having a simple memory cell configuration, since the size of the memory cell is reduced, it is important to save space in the row decoder.

Accordingly, it is an object of the present invention to reduce the number of necessary elements and simplify the circuit configuration of a decoding circuit.

(D) Means for Solving the Problems The present invention is for solving the above-mentioned problems, and is characterized in that one of a plurality of circuit units provided in parallel is provided with a first decode signal. And one of two outputs of the designated circuit unit is selected in accordance with a second decode signal in a first and second N-channel type whose source side is grounded. A MOS transistor, first and second P-channel MOS transistors connected in series to the first and second N-channel MOS transistors, respectively, and a source of the first and second P-channel MOS transistors. A third P-channel MOS transistor connected between the first side and the power supply, and a connection point of the first N-channel and P-channel MOS transistors. A third N-channel MOS transistor connected between a connection point of the second N-channel and P-channel MOS transistors; and a third N-channel and P-channel MOS transistor. The gate of the transistor receives the first decode signal and the first decode signal.
Receiving the second decode signal at the gates of the N-channel and P-channel MOS transistors and the gates of the second N-channel and P-channel MOS transistors; Are configured to obtain an output according to the second decode signal from both sides of the second decode signal.

(E) Operation According to the present invention, the number of elements per circuit unit is reduced and the circuit scale is reduced by using a pair of logic gate MOS transistors constituting the circuit unit in common. .

(F) Embodiment One embodiment of the present invention will be described with reference to the drawings.

 FIG. 1 is a circuit diagram of the decoding circuit of the present invention.

Two P-channel MOS transistors are connected to the drain of a P-channel MOS transistor (T _P5 ) whose source is connected to the power supply.
Transistor (T _P6) (T _P7) are connected in parallel, each N-channel type MOS transistor between the drain and the ground of these P-channel type MOS transistor _{(T P6) (T P7)} (T N5) (T N6 ) Is connected. Further, P-channel and N-channel MOS transistors (T _P6 ) (T
_N5 ) connection point and P-channel type and N-channel type MO
An N-channel MOS transistor (T _N7 ) is connected between the connection point of the S transistor (T _P7 ) and (T _N6 ), and a P-channel connected to the gate of the N-channel MOS transistor (T _N7 ) and the power supply. type MOS transistor (T _P5) first address decode signal data lines AD ₁ is applied to the gate (6) is connected. The second address decode is performed on the gates of the P-channel and N-channel MOS transistors (T _P6 ) (T _N5 ) and the gates of the P-channel and N-channel MOS transistors (T _P7 ) (T _N6 ). 2-bit data line signal AD ₂ is given (7)
Are connected respectively to the inverter (4) from the source and drain of the N-channel MOS transistor (T _N7 ).
The selection signals RS ₁ and RS ₂ are output via (5). These three P-channel MOS transistors ( _TP5 ) ( _TP6 )
(T _P7 ) and three N-channel MOS transistors (T _P7 )
_N5 ) (T _N6 ) (T _N7 ) constitute one unit (10).

 Next, the operation will be described.

Address decode signal AD corresponding to each unit (10)
_{When one} bit of 1 becomes "L", the P-channel MOS transistor (T _P6 ) is turned on, and the power supply potential is applied to the P-channel MOS transistors (T _P6 ) and (T _P7 ). Therefore,
When any bit of the address decode signal AD ₂ becomes “L”, the P-channel MOS corresponding to this bit
Transistor (T _P6 ) (T _P7 ) turns on, N-channel type
Since the MOS transistors (T _N5 ) and (T _N6 ) are turned off, one of the outputs of the unit (10) becomes “H”. At this time, the N-channel MOS transistor (T _N7 ) is in the off state, and the two outputs are separated.

On the other hand, at the case where each unit (10) is not selected, the corresponding address decode signal AD ₁ is constantly "H", P-channel type MOS transistor (T _P5)
Turns off and N-channel MOS transistor (T _N7 )
Turns on. Therefore, regardless of the address decode signal AD _2, N-channel type MOS transistor (T _N5) (T _N6)
Is turned on, the two outputs of the unit (10) are fixed at "L".

According to the above configuration, since each unit (10) can be composed of six MOS transistors including P-channel type and N-channel type, the unit (1) as shown in FIG. ), The number of elements can be reduced by 25%.
A space saving of about 25% can be expected. In particular, when the present invention is applied to a row decoder provided for each memory cell row, the ratio of elements that can be reduced becomes large with respect to the entire circuit, which is extremely effective in reducing the circuit scale.

(G) Effects of the Invention According to the present invention, since the size of each unit of the decoding circuit is reduced to save space, a row decoder is formed for each memory cell column even when the row pitch of the memory cells is narrow. Becomes possible. Therefore, the size of the memory cell can be reduced, and the chip size can be reduced along with the high integration of the circuit.

[Brief description of the drawings]

1 is a circuit diagram of a decoding circuit of the present invention, FIG. 2 is a logic diagram of a conventional row decoder, and FIG. 3 is a circuit diagram of FIG. (1) (10) ... unit, (2) (3) ... NOR gate, (6) (7) ... data line, ( _TP1 ) to ( _TP7 ) ...
P-channel type MOS transistor, (T _N1 ) to (T _N7 ) ...
... N-channel MOS transistor.

Claims (1)

(57) [Claims] 1. One of a plurality of circuit units provided in parallel is designated according to a first decode signal, and one of two outputs of the designated circuit unit is designated according to a second decode signal. In the selected decoding circuit, first and second N-channel MOS transistors whose source sides are connected to ground, and first and second N-channel MOS transistors connected in series to the first and second N-channel MOS transistors, respectively. Second P-channel type MO
An S transistor; a third P-channel MOS transistor connected between a source of the first and second P-channel MOS transistors and a power supply; The connection point of the MOS transistor and the second N-channel type
A third N-channel MOS transistor connected between the connection point of the channel-type MOS transistor and the third decoding circuit. Receiving the second decode signal at the gates of the first N-channel and P-channel MOS transistors and the gates of the second N-channel and P-channel MOS transistors; 3. An output circuit according to claim 3, wherein outputs are obtained from both sides of said N-channel MOS transistor in accordance with said second decode signal.