JPH0278094A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the wiring area of a circuit around a memory cell array and to highly integrate a semiconductor memory by composing a decoder so that word lines can be selected in order when a reflected binary code is inputted as address data. CONSTITUTION:An input line to be connected with a decoder line B is made common to decoder lines A and B to be connected to the input line of an AND gate G1 and decoder lines the inverse of A and B to be connected to the input line of an AND date G2. Further, an input line to be connected to the decoder line, the inverse of A is made common to the AND gate G2 and an AND gate G3, and in the same manner, an input line to be connected to a decoder line, the inverse of B is made common to the AND gate G3 and an AND gate G4. Consequently, the number of through holes can be reduced, the number of the wirings of a decoder input line can be also decreased, the wiring area of the circuit around the memory cell array can be reduced, and the semiconductor memory can be highly integrated.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor memory, and in particular to a semiconductor memory in which a decoder is configured to reduce the wiring area of a circuit around a memory cell array and achieve high integration. Memory bank is concerned.

[Conventional technology]

FIG. 2 shows a conventional method of configuring a decoder in a semiconductor memory. Here, to simplify the explanation, a case is shown in which four word lines are decoded using 2-bit address data A and B. In the figure, l is an address buffer, 2 is a decoder, and 3 is a decoder line.

4 is a decoder input line, 5 is a through hole, A and B are address data, and G1, G2, G3, and G4 are AND gates.

As shown in this figure, generally, a decoder m3 indicated by a vertical line in the figure is arranged between address buffer 1 and decoder 2. Generally, this decoder line 3 is formed in a different wiring layer from the decoder input line 4 shown by the horizontal line in the figure, and is connected to the decoder input line 4 by providing through holes 5 at necessary locations. There is.

Conventionally, as shown in this figure, when a decoder is configured so that word lines are selected in order when a pure binary code is input as address data, consideration has not been given to the fact that the wiring area increases. It wasn't. (“Digital Inch-Grated Electronics (Di)
digitalIntegratedElectroni
cs) J 411 pages, Publisher: Matsufugrow Hill (Mc
GRAW-flILL), Author: Herbert Tau (H
erbert Taub), Donald Schilling (Do
[Problems to be Solved by the Invention] Hereinafter, it will be specifically shown that in the conventional decoder configuration method shown in FIG. 2, the wiring area of the circuit around the memory cell array increases. Note that, below, in order to quantify the wiring area, attention will be paid to the number of through holes 5 that connect the decoder line 3 and the decoder input line 4. n bits (n is
When decoding 2'' word lines with address data (an integer greater than or equal to 2), the conventional decoder configuration method is as follows:
Since each decoder input line is directly connected to a decoder line, n through holes are required for each AND gate forming the decoder.

Furthermore, since the decoder is composed of 2n AND gates, the total number of through holes is n×2n. (The case in Figure 2 corresponds to the case where n = 2, and the total number of through holes is 2 x 22 = 8.) Here, as an example, 256 bits (word line = 512 Book,
Considering a semiconductor memory with bit lines = 512, x 1 bit configuration), 2' = 51 with 9-bit address data.
Since two word lines are to be decoded, the number of through holes is extremely large, 9 x 2'=4608.

This has led to an increase in the wiring area of circuits around the memo cell array, and has hindered higher integration of semiconductor memories.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory in which a decoder is configured so as to reduce the wiring area of a circuit around a memory cell array and achieve high integration.

[Means to solve the problem]

In order to achieve the above object, the semiconductor memory of the present invention includes:
In a semiconductor memory that includes a decoder that decodes address data, when an alternating binary code is input as address data, the order in which word lines or bit lines in a memory cell array are selected is Starting with any word line or bit line in the memory cell array, the word lines or bit lines are selected in the order in which they are arranged in the memory cell array, and the end word line or bit line in the memory cell array is selected. The decoder is characterized in that the decoder is configured to select the word line or bit line at the other end of the memory cell array after the memory cell array is selected.

[Effect]

Address data of n bits (n is an integer of 2 or more),
When decoding 2n word lines, if the decoder is configured as described above, the AND gate located at the end of the decoder among the AND gates configuring the decoder is n.
Other AND gates require only one through hole each. Therefore, the number of through holes is
The total number is nX1+IX (2°-1) = n+2°-1 (conventionally, nX2"). Here, as an example, 2
56 bits (word line = 512 lines, bit line = 512 lines)
Considering a semiconductor memory with a 1-bit configuration, 2'=512 word lines are decoded with 9-bit address data, so the number of through holes is 9+2'-1=520. become individual.

That is, compared to the conventional 4608, the number is reduced to about 1/9, and the wiring area of the circuit around the memory cell array can be reduced by that much, making it possible to achieve high integration.

〔Example〕

Embodiment 1 FIG. 1 is a diagram showing a first embodiment of the present invention, and shows a method of configuring a decoder in a semiconductor memory. Here, to simplify the explanation, the differences between the six embodiments, which show the case of decoding four word lines with 2-bit address data, and the conventional example shown in FIG. When inputting pure binary code as address data,
Whereas the decoder was configured so that word lines were selected in order, in this embodiment, the decoder is configured so that word lines are selected in order when an alternating binary code is input as address data. This is what we are doing. By configuring the decoder in this way, adjacent ANDs in the decoder
All gate input lines except one can be made common.

That is, focusing on AND gate G1 and AND gate G2, the decoder lines that should be connected to the input line of AND gate G1 are A and B, and the decoder lines that should be connected to the input line of AND gate G2 are A and B. Therefore, AND gate G
1 and the AND gate G2, the input line to be connected to the decoder line B can be shared. Also, AND gate G2 and AN
Focusing on D gate G3, the decoder lines that should be connected to the input line of AND gate G2 are A and B, and the decoder lines that should be connected to the input line of AND gate G3 are A and B, so decoder line A and The input lines to be connected can be shared.

The same applies to the AND gate G3 and the ANDNO gate, and the input line to be connected to the decoder line B can be shared. Therefore, the number of through holes connecting the decoder line and the decoder input line is two for the AND gate G1 located at the end of the decoder, and only one through hole for each of the other AND gates. . Therefore, the number of through holes.

There are five in total, which is reduced to 5/8 compared to the conventional eight. Therefore, the number of decoder input lines is reduced accordingly, and the wiring area of the peripheral circuits of the memory cell array (not shown) can be reduced, and higher integration can be achieved.

Embodiment 2 FIG. 3 is a diagram showing a second embodiment of the present invention, in a semiconductor memory. A method of configuring a decoder using bipolar transistors is shown.

Here, to simplify the explanation, a case is shown in which four word lines are decoded using 2-bit address data. In this embodiment, unlike FIG. 1, the decoder 2
Bipolar transistors Q1, Q2, Q3 or Q4, Q5 . Q6 or Q7,
NO consisting of Q8, Q9 or QIO, Qll, Q12
Although the R gate is used, the above discussion regarding the effects of the present invention holds true in the same way. That is, all but one input line of adjacent NOR gates in the decoder can be made common. That is, transistors Q2 and Q5. Q4 and Q
7. The base wiring for Q8 and Qll can be shared. Therefore, the number of through holes connecting the decoder line and the decoder input line is the same as the NOR located at the end of the decoder.
Two gates are required, and each other NOR gate requires only one through hole. Therefore, the number of through holes is five in total, compared to the conventional eight.
Reduced to 5/8. Therefore, the number of decoder input lines is reduced accordingly, the wiring area of the circuit around the memory cell array can be reduced, and high integration can be achieved.

Embodiment 3 FIG. 4 is a diagram showing a third embodiment of the present invention.
An example layout of the decoder shown in the figure is shown. In addition,
Here, the decoder line (AL2: second layer aluminum)
, decoder input line (ALL: 1st layer aluminum), through hole (T
HI: through hole connecting first layer aluminum and second layer aluminum) and bipolar transistors (Q1 to Q12) forming the decoder. In this embodiment as well, according to the present invention, transistors Q2 and Q5. Q4
Since the base wiring of Q7, Q8 and Qll can be made common, the number of THLs is reduced. Therefore, the number of decoder input lines is reduced accordingly, the wiring area of the circuit around the memory cell array can be reduced, and high integration can be achieved.

Furthermore, the feature of this embodiment is that transistors Q2 and Q5,
The point is that the bases of Q4 and Q7, and Q8 and Qll are connected with polycrystalline silicon (poly-8i) for leading out the base electrode. In this way, the contact hole (CONT) connecting poly-8i for drawing out the base electrode and AL1 can also be shared, so that the wiring area of the circuit around the memory cell array can be further reduced. Furthermore, in this embodiment, the collectors of transistors Q1 and Q2, Q4 and Q5, Q7 and Q8, and QIO and Qll are commonly connected to resistors R1, R2, R3, and R4, so The containing layers are made common to each other, and C1, C2, C3, and C4 (collectors) are raised in common. Also, transistors Q3, Q6, Q9, and Q1
The base of 2 is made of polycrystalline silicon (
poly-3i) and commonly connected to the reference voltage VBB2,
In addition, the nf buried layer constituting the collectors of transistors Q3, Q6, Q9, and Q12 is made common, and the CO (collector)
This reduces the wiring area of circuits around the memory cell array.

Embodiment 4 FIG. 5 is a diagram showing a fourth embodiment of the present invention, and shows a method of configuring a decoder using MOS transistors in a semiconductor memory. Here, to simplify the explanation, a case is shown in which four word lines are decoded using 2-bit address data. In this embodiment, unlike in FIG. 1, MOS transistors T1, T2 . T3 or T4゜T5, T6 or T7, T8, T9 or Tl01Tl
I am using a NAND gate consisting of T12.
The above discussion regarding the effects of the present invention holds true as well. That is, all but one input line of adjacent NAND gates in the decoder can be made common. That is, transistors T3 and T5, T6 and T8. The gate wiring for T9 and Tll can be made common, and the wiring area of the circuit around the memory cell array can be reduced accordingly, allowing for higher integration.

Embodiment 5 FIG. 6 is a diagram showing a fifth embodiment of the present invention, and shows a method of configuring a decoder using IMOS transistors and bipolar transistors in a semiconductor memory. Here, to simplify the explanation, a case is shown in which four word lines are decoded using 2-bit address data.

In this embodiment, as in FIG. 5, a NAND gate is used as the logic gate constituting the decoder 2, and the above discussion regarding the effects of the present invention holds true in the same way. That is, the input lines of adjacent NAND gates in the decoder are
All except one can be made common, and accordingly, the wiring area of the circuit around the memory cell array can be reduced, and higher integration can be achieved.

Embodiment 6 FIG. 7 is a diagram showing a sixth embodiment of the present invention. The differences between this embodiment, which shows a method of configuring a decoder in a semiconductor memory, and the embodiment of FIG. 1 are as follows. In Figure 1, 2
With bit address data.

Whereas four word lines were decoded, in this embodiment, eight word lines are decoded using 3-bit address data.6Thus, the above discussion regarding the effects of the present invention holds true in the same way. In other words, all but one of the input lines of adjacent AND gates in the decoder can be made common, and accordingly, the wiring area of the circuit around the memory cell array can be reduced, and higher integration can be achieved.

〔Effect of the invention〕

As explained above, according to the present invention, when 2n word lines are decoded using n-bit address data (n is an integer of 2 or more), a through-hole connecting a decoder line and a decoder input line is provided. Focusing on the number of AND gates that make up the decoder, the number of AND gates located at the end of the decoder is n, and the other AND gates are:
Only one piece is required for each. Therefore, the total number of through holes is nX1+IX (2n-1)=n+2"
-1 (previously nx2''), for example, 25
Considering a semiconductor memory with 6 bits (word lines = 512, bit lines 2512, x 1 bit configuration), 2' = 512 word lines will be decoded with 9 bit address data, so The number of through holes above is
9+29-1=520 pieces. In other words, the conventional 46
The wiring area of the circuit around the memory cell array can be reduced by that much, and higher integration can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of logic gates showing a first embodiment of a semiconductor memory according to the present invention, FIG. 2 is a layout diagram of logic gates showing a conventional semiconductor memory, and FIG. FIG. 4 is a circuit layout diagram showing the second embodiment, FIG. 4 is a layout diagram showing the third embodiment of the present invention, and FIGS. 5 and 6 are respectively the fourth and fifth embodiments of the present invention. FIG. 7 is a logic gate layout diagram showing a sixth embodiment of the present invention. 1...Address buffer 2...Decoder 3...
Decoder line 4...Decoder input line 5...Through hole A, B...Address data G1-G
4...AND gate

Claims (1)

[Claims] 1. In a semiconductor memory including a decoder for decoding address data, the order in which word lines or bit lines in a memory cell array are selected when an alternating binary code is input as address data. starts from any word line or bit line in the memory cell array,
Word lines or bit lines are selected in the order in which they are arranged in the memory cell array, and after the end word line or bit line in the memory cell array is selected,
A semiconductor memory characterized in that the decoder is configured so that a word line or a bit line at the other end of the memory cell array is selected. 2. The semiconductor memory according to claim 1, wherein the Hamming distance of address data for selecting two adjacent word lines or bit lines is 1. 3. The decoder is composed of a plurality of logic gates having a plurality of input terminals into which address data is input, and at least one of the input terminals of adjacent logic gates is connected in common. A semiconductor memory according to claim 1. 4. The logic gate is composed of a circuit including at least one bipolar transistor, and the input terminals of adjacent logic gates are connected to each other by a polycrystalline silicon layer for leading out the base electrode of the bipolar transistor. 4. A semiconductor memory according to claim 3, characterized in that: 5. A semiconductor characterized in that the logic gate is constituted by a circuit including at least one MOS transistor, and input terminals of adjacent logic gates are connected to each other by gate electrodes of the MOS transistors. memory.