JPS6045842A - Multiplier circuit - Google Patents

Abstract

PURPOSE:To reduce the power consumption of a multiplier circuit without impairing the high-speed performance of the multiplier circuit, by providing plural input circuits, addition stages, etc. and increasing the circuit current for only the addition stages which are under operation with reduction of the circuit current given to other addition stages. CONSTITUTION:The input signals of a multiplicand (x) and a multiplier (y) are read into input latch circuits 20 and 21 respectively by controlling the phase relation between a read-in clock CPI for input latch circuit and signals A-G. As a result, the circuit current of a basic block for addition stages 45-49 of a multiplier circuit increases. In this case, basic blocks 1-19 and inverters 23-29 have the same delay time, and the signal sum S and a carry C0 of the multiplier circuit are transferred to the next lower addition stage. Thus the circuit current increased for this relevant stage with a high-speed operation. While the circuit current for other addition stages is reduced. As a result, the power consumption is reduced without deteriorating the high-speed performance of the multiplier circuit.

Description

[Detailed description of the invention] Industrial applications The present invention relates to reducing power consumption of a multiplication circuit.

Conventional configuration and problems When multiplying binary numbers, when the multiplicand X and the multiplier Y are expressed as positive integers as shown in equations (1) and (2), the product P
) is as follows.

Here, n and m are the bit word lengths of the multiplicand X and the multiplier Y, respectively, and represent the respective pinots of X□ and yl.

The multiplication process in equation (3) is as follows when the bit word length of multiplicand X2 multiplier Y is 4 bits, 4 3 2
1 ×)"4 'Y3 Y2 y4 x4°"1 x3°y1x2°y1x1°y1x4°y
2x3°y2x2°"2 xi°y2x4@y3 xdaiy3 x2°y3 xloyro+)!4°y4 昘°y
4 x2°”4 x1°y4P8P7P6P5P4P5
P2P1 The sum of the partial products x0·y of each bit becomes the product P.

A circuit configuration for performing such multiplication is shown in FIG. The multiplication method shown in FIG. 1 is called a carry-save method. In the figure, x1 to x4 are respective bit input terminals of the multiplicand X, 20 is an input latch circuit, and y1 to y4
are input terminals for each bit of the multiplier Y, 21 is an input latch circuit, and CPI is a read clock to the input latch circuits 20 and 21. 22 is an output launch circuit, P1 to P8
Each bit output terminal of the signal P, CPO, is a read clock to the output Lanochi circuit. 1 to 7 are AND gates, and have the input/output relationship shown in FIG.

In the figure, 201 is an AND gate. 8 to 10 are AND gates and half adders constructed as shown in FIG. In the figure, 30111S1 is an AND gate, 302 is a half adder, S is the sum output of the half adder, and CO is the carry output.

11 to 1d are AND gates and full adders constructed as shown in FIG. In the same figure, 401 is AN
The D gate 402 is a full adder, Ci is the carry output of the full adder, S is the sum output, and CO is the carry output. 17 is a half adder, K and Ci are input terminals, and S
is a sum output terminal, and Co is a carry output terminal. 18.1
Reference numeral 9 denotes a total adder, where a is an input terminal, Ci is a carry input terminal, S is a sum output, and Co is a carry output terminal.

With such a circuit configuration, by generating partial products using an AND gate and adding them using an adder, it is possible to perform the multiplication of the multiplicand and the multiplier shown in the multiplication X process described above.

As explained above, the parallel multiplier is configured by generating and adding partial products. Therefore, as shown in Figure 1,
The block consisting of AND gates 1 to 7 and full adders 18 and 19 is completely repeated. FIG. 5 shows a block circuit consisting of AND gates 1 to 7 and full adders 18 and 19. The transistors Q and Q form a negative logic AND gate to generate the product of X□・Y.

Transistors Q4 to Q23 and resistors R2 to R7 constitute a full adder 18.19. Ci, R and AND
The gate output x-y'7 is the input signal of the full adder, S is the sum output, and CO is the carry output.

■R is a constant voltage bias power supply, and transistors Q1.
Q4. Q13 and resistors R1, R2, and R5 form a constant current path. Q4゜Q
A constant current is flowing through 13.

VB1 to B3 are reference bias sources.

The operating speed of the circuit block shown in FIG. 5 depends on the characteristics of the devices that make up the circuit, but the transistor Q1
”41013, and the larger the current value, the faster the speed becomes. Therefore, in order to realize a high-speed multiplier, it is necessary to set a large value for this constant current, which reduces power consumption. In such a high-speed multiplier, if the bit word length of the multiplicand The size of the circuit becomes enormous, and when it is integrated into an integrated circuit, there are problems in terms of heat dissipation from the package, etc.

OBJECTS OF THE INVENTION In view of the above-mentioned drawbacks, the present invention provides a multiplier that consumes less power without sacrificing the high-speed performance of the circuit.

Structure of the Invention In order to achieve the above object, the multiplier of the present invention is comprised of a first input circuit 1" into which a multiplied signal is input, a second input circuit into which a multiplicable signal is input, and a logic circuit. , and a plurality of addition stages that process signals from the first and second input circuits, a current supply circuit that supplies current to the plurality of addition stages, and a current supply circuit that processes signals from the plurality of addition stages. and an output latch circuit, and the current supply circuit is configured to supply a higher current to the addition stage in which an operation is being performed among the plurality of addition stages than the other addition stages.

With the above configuration, the present invention provides a multiplier that can achieve low power consumption without sacrificing high performance.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below. Figure 6 shows
FIG. 3 is a block diagram of a multiplier in an embodiment of the present invention. Components that are the same as those in FIG. 1 are given the same numbers and their explanations will be omitted.

In the figure, 23 to 29 are inverters each having the same delay time as the basic blocks 1 to 19 constituting the multiplier.The inverters 23 to 29 are connected in a ring to form a ring oscillator. There is.

The waveforms of the outputs A to G of each inverter are out of phase by the delay time tpd of one stage of inverter, as shown in FIG. 7A to G. This A-G waveform is transferred to the inverter 30~
36 and AND gates 3A to 43, the outputs H to N of the AND gates are multiphase clocks that are "High" only during 1 tpd and have different phases, as shown in FIG. 7 H-H. is obtained. By controlling the value of vR shown in FIG. 5 for each addition stage 45 to 49 using this H-N signal, transistors Q1. Q4. The value of the constant current flowing through Q13 can be controlled.

Now, if the phase relationship between the input Lanochi circuit read clock CPI and the signals A to G is controlled as shown in FIG. 7, the input signals of the multiplicand
7, the circuit currents of the basic blocks of each addition stage 45 to 49 of the multiplication circuit increase sequentially in accordance with the waveforms shown in FIG. 7H-K.

Here, the sum S and carry IJ-Co- signals of the multiplication circuit are transferred to the addition stage one stage below, and are sent to the basic blocks 1 to 1.
19 and the inverters 23 to 29 of the ring oscillator have the same delay time, so Sam S and CA I)-
The circuit current increases only in the adding stage where the Co signal is transferred and the calculation is performed, and the calculation is performed at high speed. Note that the final addition stage 49 receives the outputs of AND gate 7) 4.2, 43, 37, M,
The sum of the H signals is calculated by the OR gate 44, and as shown by the output signal 0, the period during which the circuit current of the final addition stage 490 is increased is made longer in accordance with the time during which the carry Co is transferred.

As described in detail, according to the present invention, in a carry-save type multiplier, the circuit current is increased only in the adding stage where sum and carry signals are transferred and calculations are performed, thereby performing high-speed calculations. Since the circuit current of other addition stages is reduced, it is possible to create a high-speed multiplication circuit with low power consumption, and it is easy to integrate the multiplication circuit, especially in a multiplication circuit with a long input signal bit word length and a large circuit scale. It has the effect of becoming.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional multiplier; Figures 2, 3, and 4 are block diagrams of the main parts of Figure 1; Figure 5 is a circuit diagram of a conventional multiplier; Figure 6 d A block wiring diagram of a multiplier in an embodiment of the present invention, and FIG. 7 is an operating waveform diagram of the multiplier. 20.21 Input latch circuit, 22 Output lanotch circuit,
45.46.47,48.49・Addition stage. Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] Consisting of logic circuits, a first input circuit to which a multiplier signal is input, and a second input circuit to which a multiplicand signal is input,
And the above-mentioned No. 1. It has a plurality of addition stages that process signals from the second input circuit, a current supply circuit that supplies current to the plurality of addition stages, and an output Lanochi circuit that processes the signals from the plurality of addition stages. . A multiplication circuit, wherein the current supply circuit supplies a current equal to that of the other addition stages to the addition stage in which an operation is being performed among the plurality of addition stages.