JPH0475542B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multilevel logic circuits, and more particularly to multilevel logic circuits.
It concerns a multi-logic level circuit that operates on multiple clock pulses.

Dynamic multilevel logic circuits made by metal oxide silicon techniques require multiphase clocks to ensure correct execution of the desired logic functions. Execution of priority multilevel logic functions requires dividing the logic into time slots and specifying the required number of clock phases to cover the worst case or maximum number of logic levels to be executed. The clock phases are created by dividing the clock signal from the fundamental signal source. This results in a polyphase of the clock signal, with all phases typically being 1,
It is related to the frequency of the fundamental source divided by 2, 4, etc., which means that all phases of the clock are multiples of the frequency of the fundamental source. In this scheme, the frequency of operation is increased until one phase, only one at any time, becomes critical.

Although MOS circuits are expected to be manufactured economically,
The inherent slowness of these circuits compared to other forms of logic circuits makes these circuits unusable for many current dynamic logic applications, as they require separate clock phases and logic level evaluation for precharging. Not done.

The present invention also relates to digital multiplier circuits, and more particularly to digital multiplier circuits for use with microprocessors controlled by domino control circuits.

A major limitation in the use of field-effect transistor circuits, and especially large scale integrated circuits, is that dynamic logic circuits such as those found in multipliers are difficult to implement in high-speed applications due to the need for multiple clocks required in implementing logic circuits with field transistors. This is a restriction associated with the expansion of In the past, there were multiple clock phases required to implement field effect transistor logic circuits. The precharge phase is necessary to precharge all of the data lines interconnecting the transistors used to form the logic circuit;
The second clock phase is necessary to evaluate the results of the logic execution. When logic circuits are connected together and each stage depends on the result of the preceding logic stage,
Polyphase clock functionality is required. The first clock phase fully precharges all data lines of the logic circuit, the second clock phase evaluates the first logic level,
The result is then added to the second logic level evaluated by the third clock phase, and so on through the entire number of logic levels. Thus, the N logic level function that a field effect transistor is to perform requires N+1 clock phases, one to precharge all of the data lines and one for each logic level to be evaluated. . Thus, the time slot arrangement of logic levels causes many logic circuits to wait idly for their turn to be evaluated, and the overall result is that these circuits are significantly slower. Thus, field effect transistor logic circuits have hitherto been problem-free when used in handheld computers and similar applications. However, as the demands on circuits become more complex, the need for speed in performing complex logic functions becomes critical. The luxury of waiting for a suitable time slot for the circuit to evaluate is not acceptable in applications requiring high speeds in the nanosecond range.

Minimization of the time in a microprocessor device required to perform a multiplication function is achieved by implementing a hardware multiplier that performs a modified Booth algorithm for digital multiplication, reducing the number of processing cycles of a microprocessor to a relatively small number. microprocessor cycles. However, even this reduction in time is insufficient to provide field effect transistor type microprocessors with the speed necessary for modern technology applications.

The multi-level logic circuit includes a first plurality of logic circuits connected in a cascaded arrangement. Second
A plurality of pseudo logic circuits are also connected in a cascade arrangement and are used to generate logic pulses for evaluating the first plurality of logic circuits. The clock source provides a precharge signal to the first plurality of logic circuits and the second plurality of pseudo logic circuits, and the evaluation circuit provides a precharge signal to the first plurality of logic circuits and a second plurality of pseudo logic circuits, and the evaluation circuit precharges the pseudo logic circuits to obtain an evaluation signal for evaluating the logic state of the first plurality of logic circuits. It is used to combine the output signal from the logic signal and the clock signal.

A multi-level logic circuit is disclosed in which evaluation pulses are provided that match the utilization of data to be evaluated at each level.

The evaluation circuit is combined with multi-level logic circuits to obtain a high speed programmable logic array.

A digital multiplier circuit for a microprocessor utilizes a modified Booth algorithm to perform digital multiplication of two numbers and to perform a Booth multiplication of a selected number n, where n is a positive integer equal to half the number of bits in the multiplier. - Includes a booth recorder to record the multiplier in the operation set. Each operation set is applied by a multiplication set to a second plurality of n partial product selectors connected in a cascade arrangement, where each partial product selector multiplication set is applied to one of the recorded Booth operation sets. Execute one. The outputs of the partial product selectors are summed by a summing device and the domino circuit device provides an evaluation pulse to each element of the partial product selector upon completion of a booth operation set connected to the partial product selector.

In multi-level logic circuits, such as multipliers, performance is improved in terms of operating speed by detecting when each level of the multi-level logic circuit is ready for evaluation through the use of domino control circuits.

The domino control circuit implements a worst-case time delay for the propagation of one clock pulse and its complement to ensure exactly when the corresponding stage of the Booth multiplier is in the position to be evaluated.

The adder includes a plurality of adder circuits connected between selected elements of the plurality of partial product selectors. To guarantee the earliest possible evaluation of the data in the adder set, the domino control circuit considers the worst case as long as the time delay causes the adder to perform its logical operation and has the data ready to undergo evaluation. It also includes an adder circuit that represents the case where At the end of that time, the domino control circuit provides an evaluatable pulse to the next logic level in the multiplier.

These embodiments and the advantages and objects of the invention will become apparent from reading the specification in conjunction with the drawings.

In FIG. 1, a microprocessor is shown including a multiplier 161 according to the present invention. I/O
Commands from terminals (not shown) are sent to pad 1.
03 to the instruction data register 105, then the high speed decoder 107, the main decoder 10
9, and address arithmetic unit 111. Main decoder 109 decodes instructions into control signals used through the microprocessor. These control signals are transferred to a control pipeline register 1 which conveys the decoded signals via data bundle 117 to appropriate circuitry including multiplier 161.
15.

Microprocessor 100 basically has two parts: an instruction part represented by area 131 and a data part represented by area 133. Address arithmetic unit 111 supplies instructions from instruction data register 105 to displacement multiplexer 1.
35 and receives data from instruction link register 153 or general purpose register 119 via index multiplexer 137 based on the result of high speed decoder 107.

Appropriate arithmetic operations are carry break logic 15
5, the output 123 of address arithmetic unit 111 is latched in common address bus register 125. The output of this register is then applied to the integrated circuit's I/O via pad 139 to address either data memory or input/output address space, or to an internal bus for use as a constant. The output of the address arithmetic unit is also applied to instruction address multiplexer 145. The output of this multiplexer is latched in the instruction address register 147. Another input of the multiplexer, namely the instruction address
The incremental type of register is provided by 149.
The multiplexer 145 is controlled by the ordering circuit 14.
Provided by 3. Sequencing circuit 143 controls branches and interrupts received via pad 141. The output of instruction address register 147 is applied to I/O via pad 151 for addressing instructions in memory. The output of instruction address register 147 is also latched in instruction ring register 153 after a one cycle delay.

Arithmetic theory unit 127 has general purpose register 119
It receives data from the general register 119, machine control register 113, program status register, or interrupt status register through the C multiplexer or from the multiplier 161 through the B multiplexer. The carry to the arithmetic logic unit is mainly carried by the carry logic 1 under the control of the decoder.
It will be held from 21. The output of the arithmetic theory unit is regulated by saturation logic 129 in case of overflow. The output is then passed through X multiplexer 157 and Y multiplexer 159 to general purpose register 1.
He will be returned on the 19th.

When an instruction requiring multiplexing is decoded by the main decoder 107, general registers 5 and C
The multiplexer results are multiplied together by a multiplier, and the results are latched in registers internal to the block.

FIG. 2, to which reference is now made, provides the basic operating principle of multiplier 161 through the use of domino control logic contained therein. The inverted clock signal clock is a domino circuit multi-level logic system 10
A block diagram of the domino control multi-level logic is shown with an inverter 3 added to the domino control multi-level logic. Clock source 1 provides a clock signal via conductor 5 to the pseudo load control multilevel logic device. Data source 7 provides parallel data signals, DATA1-DATAN, to domino controlled multilevel logic 10 via data bus 9. Domino control multi-level logic device 10 includes M×N logic elements 13. The logic elements correspond to M levels of multilevel logic devices with a width of N bits.
The data words forming the ×M matrix are divided into words having a width of N logic elements connected together in a cascade arrangement. Furthermore, M domino circuits 1 are also connected in a cascade arrangement.
There are 5. Each logic element 13 and each domino circuit 1
5 is precharged by a clock signal which activates the gate of transistor 17, causing VCC, ie a voltage supplied from a voltage source not shown, to be applied to the corresponding logic element 13 and domino circuit 15. 1,1 logic element 19, 1,(N-1) logic element 21, and 1,N logic element 25 are connected to a clock signal that connects the corresponding logic element to a reference voltage, _Vdd, as indicated by arrow 31. It is evaluated by the activation transistor 27. The reason that the 1,1 domino circuit 29 is also evaluated by the clock signal is that the 1,1 domino circuit 29 is connected to represent the worst case condition, i.e. connected to the first row. This is because the evaluation pulses for any of the logic elements 13 are supplied by the inverting amplifier 33 to the logic elements 13 placed in the second row of the domino-controlled multilevel logic device one at a time to ensure a correct evaluation. Of course, the logic elements in the second row are connected in a cascade arrangement with the logic elements in the first row, and the transistors are connected to form an AND gate that AND-connects the clock signal supplied from inverter 3 and the output of inverter 33. The evaluation can be carried out at the same time that an evaluation pulse is applied to the gate of the transistor 37 connected together with 17. The data from the data source 9 is connected to the corresponding input terminal of the first row of logic elements present, and the Q terminal is connected at the input terminal to the corresponding logic element of the second row, thus creating a cascade connection. We must pay attention to this. This configuration is perfectly maintained throughout all M rows. The domino circuits 15 in each row are similarly connected in a cascade arrangement, each with a signal propagation delay to ensure that the corresponding logic completes all logic operations when the evaluation pulse is applied to the output of the inverter 33. Indicates the worst possible conditions. Evaluation of the domino control multilevel logic device 10 requires only (M-1) domino circuit devices, but if the data provided at the output of the logic element 13 is a member of M rows and is to be stored in a memory location, then M domino circuit 39
A memory pause may be supplied to the final output inverter 33 of. Thus, the occurrence of evaluation pulses for each row of logic elements is compared to the last domino of a row that falls as each domino that produces an evaluation pulse falls. This provides asynchronous operation for evaluating field effect transistor logic circuits.

FIG. 3, to which reference is now made, illustrates the multiplier 161 of FIG. 1 which includes the domino principle described with respect to FIG.
FIG. The multiplicand is passed from C multiplexer 167 in FIG. 1 via data bus 175 to six partial product selectors, rows 193, 195,
197, 201, 209 and 213. Multiplier is from general register 5,159 to conductor bundle 1
77 to booth recorder 217. In the embodiment of FIG. 3, the multiplier is 13 bits and the multiplicand is 16 bits. However, the examples provided here may apply to any size multiplier and any size multiplicand. All the circuits illustrated in FIG. 3 are precharged by the first stage clock QP as shown in FIG. 2 and during selected times by evaluation pulses as illustrated in FIG. I can continue. All of the partial product selectors are evaluated simultaneously by clock QE.
First partial product selector 193 is controlled by Booth recorder 219 using multiplier bits 10, 11 and 12. The second partial product selector 195 selects the Booth recorder 2 using multiplier bits 8, 9 and 10.
21. Third partial product selector 1
97 is controlled by Booth recorder 223 using multiplier bits 6, 7 and 8. The fourth partial product selector 201 selects multiplier bits 4, 5 and 6.
is controlled by a booth recorder 225 using a. The fifth partial product selector 209 is a Booth recorder 227 using multiplier bits 2, 3 and 4.
controlled by. The sixth partial product selector is controlled by Booth recorder 229 using multiplier bits 0, 1, and 2. The partial products from the first three selectors 193, 195, and 197 are added by a carry save adder (CSA) 199. CSA is evaluated by evaluation pulses provided by partial product selector delay circuit 179. The output of CSA 199 and the partial products from selector 201 are added by CSA 207. The evaluation pulse of CSA 207 is provided by CSA delay circuit 181. The output of CSA207 and the partial product from selector 209 are CSA2
11. The evaluation pulse of CSA 211 is provided by CSA delay circuit 183.
The output of CSA 211 and the partial products from selector 213 are added by CSA 215. CSA
215 evaluation pulses are provided by CSA delay circuit 185. The output of CSA 215 enters intermediate register 219. This completes one clock cycle of activity. On subsequent clock cycles,
The contents of intermediate register 119 are added by carry ripple adder (CRA) 227. This creates a product that is latched in product register 229.
The product register is then applied to arithmetic logic unit 127 via B multiplexer 165.

Referring now to FIG. 4, the timing diagram of FIG. 3 is shown for use in conjunction with FIG. In Figure 3, the data is displayed at the bottom of the page on conductor 1.
75, flows through a partial product selector and a carry save adder, and eventually emerges from product selector 229 at the top of FIG. Intermediate register 219 and carry ripple adder 227
The separation between indicates the completion of the first stage 365 and the beginning of the second stage 367. This separation is indicated by line and arrow combination 369. In Figure 4,
Vertical lines 321 and 326 represent the start of the multiplication cycle, in which case the precharge clock is indicated by arrow 33.
7, precharges the circuitry within multiplier 161 including the carry save adder and selector, provides an input to conductor bus 175 as shown by dimension line 339, and provides input to conductor bus 175 as indicated by dimension line 341. Precharge the carry ripple adder 227 as shown by . At vertical line 323, the precharge clock is removed as shown by waveform 329 and the evaluation clock is provided as shown by waveform 331. All partial product selectors are evaluated at times between vertical lines 323 and 338, as indicated by dimension line 351. The carry save adder (CSA) is vertical line 33
The first carry-save adder 199 is evaluated in time periods between 8 and 345. The evaluation pulse for carry save adder 199 is provided by PPS delay circuit 179. The first CSA delay circuit 181 has a vertical line 345
2nd CSA 207 during the time between and vertical line 347
A second evaluation pulse is supplied to. The CSA evaluation pulse is indicated by dimension line 355. 3rd CSA
The evaluation pulse is provided to the third CSA 211 during the time indicated by dimension line 357, which is the distance between vertical lines 347 and 349. The fourth CSA 215 is evaluated by the pulses provided by the third CSA delay circuit 185. This pulse occurs between vertical line 349 and vertical line 365 in FIG.
59. The evaluation result is vertical line 3
25 and vertical line 326, thereby completing the multiplication, and on the next cycle the data contained in intermediate register 219 is added by CRA 227 and the first It is added to product register 229 as is added to arithmetic logic unit 227 in the figure. Figure 4 is the first
The steps represent the operations that take place below line 369 in FIG.
Started by stages. Thus, the multipliers disclosed and discussed above are capable of performing complex multiplication functions and providing information to the arithmetic logic unit at a rate of one per clock cycle.

5A and 5B are simplified schematic diagrams of a 16 bit by 16 bit multiplier according to the present invention. The first partial product selector row 193 has 19 cells 1
91 and receives the most significant bit in registers 370 and 372, while the least significant bit is added to cell 374 of FIG. 5B. Multiple cells for the most significant bit are required because the most significant bit is a sign bit and is applied to three or more separate loads. Two special cells are required to perform booth operations.

The decoded Booth operand will cause the partial product selector to perform the function of the Booth operand. These features are listed in Table 1. In the present application of the preferred embodiment of FIG.
By moving each bit to the left, the number is doubled. Table 2 shows the number of cells in each row, and Table 1 shows the truth table for the decoding Booth algorithm.

Table 1 3 bit number 000 Add 0 to the value in the previous row of the register 001 Add the multiplicand to the value in the previous row of the register 010 Add the multiplicand to the value in the previous row of the register 011 Add the multiplicand to the value in the previous row Add twice the value 100 Subtract twice the multiplicand from the previous value 101 Subtract the multiplicand from the previous value 110 Subtract the multiplicand from the previous value 111 Subtract 0 from the previous value Table 2 Rows, cells and reference numbers Cells 1 Partial product selector 193, 19 2 Partial product selector 195, 19 3 Partial product selector 197, 19 4 Carry save adder 199, 18 5 Partial product selector 201, 19 6 Carry save adder 211, 18 7 Part Product selector 213, 19 8 Carry save adder 215, 18 9 Intermediate register 219, 54 10 Carry ripple adder 227, 26 11 Product register 229, 28 To minimize time delay, no more than two Design limitations on loads were made in the preferred embodiment, thus ensuring that the worst case condition is one load. This restriction is taken into account during the generation of the evaluation pulse. Extra cells 371 and 375 are provided and the first booth recorder 2
19 is used to implement the Booth algorithm. The output of the cell is shifted two bits to the right and applied to the second partial product selector 195. The result of the movement is transmitted through the conductor bundle 376.
Added to IR (intermediate) register 219 and accumulated there. The output of the second partial product selector is applied to a third partial product selector 197, row 199, whose output is applied to a carry save adder. Each carry-save adder used to create a row of carry-save adders is a full adder and therefore requires three inputs. The first reason is
This is because the outputs of each of the second and third partial product selectors are applied to row 199 of the first carry save adder to provide three inputs to be added. After that, the output of each full adder 310 is sent to the next full adder 31.
0, whose output is then combined with the output of the next partial product selector to make the summation result of the multiplication function performed by the Booth algorithm into the function described with respect to FIGS. 3 and 4. The previous carry-save adder 3 also contains the carry output until it is fed to the intermediate register 219.
summed by 10.

FIG. 6 is a schematic diagram of each booth recorder stage 380, which essentially consists of a programmable logic array 38.
1, where the Booth algorithm is decoded by programmable logic array 381 and applied to logic device 383, which includes NOR gates 385, 387 and inverter 389.
The output of the logic device 383 is indicated by dimension line 3 in FIG.
Evaluation pulse QE represented by 51 and provided by gated buffer amplifier 392
1 to the partial product selector via data bus 391.

FIG. 7 is a schematic diagram of each partial product selector whose input is provided via data bus 400 from a Booth recorder. The output from each partial product selector is provided via data bus 403. The input of each selector cell 189 is
Data bus 175 and inverted by 191. However, there is no input such as the least significant bit position, and then circuit 187 is biased by circuit 405. The bias is created by two depletion mode transistors connected to a voltage source, not shown, as shown in FIG. Partial volume movement is accomplished by passages 402 and 404.

A PRR delay circuit 179 is shown in FIG.
It is used to delay the evaluation pulse applied to the carry-save adder circuit 199 by a propagation delay that represents the worst case condition of the partial product selector. It consists of Noah gate 409 and amplifier 41
1, the result being a first CSA delay circuit 181 and a first CSA row 19
Added to 9. Throughout the illustrations, QE stands for evaluation pulse and QP stands for pre-charge pulse.

FIG. 9 is a schematic diagram of carry save adder circuit 205 and CSA delay circuit 183, which are identical. Transistor logic 425 with output supplied by data bus 427
Inverters 421, 422 and 4
Three inputs are supplied to 23. This is a full adder circuit and provides a sum output and a carry output via data bus 427.

FIG. 10, which is similar to the circuit of FIG. 9, is a carry ripple adder with an intermediate register 219.
represents each stage of device 223 whose outputs are summed by carry ripple adder 223. A carry circuit 431 separating each group of five carry ripple adders as shown in FIG. 5 is shown in FIG. 11 and includes a NOR gate 433 and two MOS transistors 435. . FIG. 10B is a circuit that provides a carry input for a carry ripple adder.

12A and 12B are intermediate registers located in the output buffer stage and also demonstrate the fact that the microprocessor controls the loading and storage of data in the transistors located at 471.

FIG. 13 shows the memory control circuit of FIG. 5, including NOR gates 455, 456 and transistor 4.
Contains 57.

FIG. 14 shows a schematic diagram of the circuit used to delay the output of the two least significant intermediate register bits (which do not need to be accumulated) into the product register.

FIG. 15 is a block diagram of product register 229. The storage control circuit is shown in FIG. 13, again it is used with the scan control and precharge pulses and evaluation pulses provided by the computer and the OR gates 444,4
45, 446, and a gated-OR function performed by transistor circuits generally designated 457.

FIG. 16, to which reference is now made, shows a programmable logic array 10 having an output connected to memory 2.
A schematic diagram of 0 is shown. Programmable logic array 100 includes two stages, in which the data appearing on data bus 9 in first decode stage 72 is divided into x-coordinates represented by data input lines and vertical lines 75,
The information is decoded by placing transistor 73 between the y coordinates represented by 76, 77 and 79. When the data is decoded,
It is added to a second stage 81, which is an output stage and is used to drive a load, which in the case of FIG. 16 is memory as well as other circuitry connected to data bus 93. . Programming of the output stage is represented by transistor 83, which provides connections for vertical lines 75, 76, 77 and horizontal lines 85, 87. Pseudo load circuit 15
is connected to the worst case condition by a single transistor 37 connected between the x and y axes of programmable logic array 100. Obviously, the more transistors conduct, the faster the line connected to transistor 27 will discharge. Therefore, the worst case arrangement is one transistor on and all but one data line transistors off. Thus the 16th
In the illustrated embodiment, transistor 8 is biased on and transistors 2, 4 and 6 are biased off. The available signal is pseudo logic 1
5 is AND-connected with the clock signal by the structure of gates 37 and 27 included in the clock signal. This causes a pulse to be applied to the output of inverter 33, thus enabling transistor 137 so that if the clock signal is removed from transistor 17, second stage 81 of the programmable logic array is evaluated. Output is data bus 83 and memory 2
If the second pseudo-circuit 101 is evaluated, the inverter 133 supplies a storage pulse to the memory 2 and the output of the programmable logic array is stored in the memory 2.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor including a multiplier according to the present invention, FIG. 2 is a block diagram of a domino control logic circuit, FIG. 3 is a block diagram of the multiplier of FIG. 1 according to the present invention, and FIG. is a timing diagram of the multiplier in FIG. 3, and FIGS. 5A and 5B are timing diagrams for the multiplier in FIG.
A simplified schematic diagram of the multiplier shown in FIG.
Schematic diagram of each Booth decoder stage in Figure B, Figure 7 is a partial product selector 191 in Figures 5A and 5B
8 is a schematic diagram of the PPR delay circuit shown in FIG. 5A, and FIG. 9 is a schematic diagram of the PPR delay circuit shown in FIG.
A schematic diagram of the save adder, FIG. 10 is a schematic diagram of the carry ripple adder used in FIG.
1 shows the carry circuit used in the embodiment shown in FIG. 5, FIGS. 12A and 12B show the intermediate register in the output stage of FIG. 5, FIG. 13 shows the storage control circuit shown in FIG. 5, and FIG. 15 is a schematic diagram of the intermediate register 21 of FIG. 5, and FIG. 16 is a schematic diagram of a programmable logic array embodying the present invention. Explanation of symbols, 10...Domino control circuit, 100
... Microprocessor, 161 ... Multiplier, 1
91, 193, 195, 197, 201, 20
9,213...Partial product selector, 199,20
7,211,215,227...CSA, 119,
219... Intermediate register, 229... Product register, 217, 219, 221, 223, 225,
227, 229...booth recorder, 381...
...Programmable logical array.

Claims (1)

[Scope of Claims] 1. A plurality of logic circuit means connected to perform a logical operation, a pseudo logic circuit means connected to supply a plurality of evaluation pulses, and a signal pulse to the plurality of logic circuits. and evaluation circuit means for evaluating each of the plurality of logic circuit means in response to the signal pulse and the evaluation pulse from the plurality of pseudo logic circuit means. In the circuit, the plurality of logic circuit means includes M×N logic circuit means corresponding to an M-level multi-level logic circuit with a width of N bits, where M and N are integers, and each of the logic circuit means has a It has a predetermined circuit configuration, the M×N logic circuit means are arranged in columns ranging from the first to the M-th column, and each of the N logic circuit means has a corresponding M-th column of N logic circuits. The N logic circuit means are connected to the corresponding logic circuit means of the next sequential column of N logic circuit means so as to define a cascade connection between each of the N logic circuit means of the first column having circuit means and similar connections are made. connected between each logic circuit means of each column of N logic circuit means to a corresponding logic circuit means of a next sequential column of N logic circuit means following said first column; The pseudo-logic circuit means have a predetermined similar circuit configuration and are connected to the first pseudo-logic circuit means in a cascade arrangement via the M-th pseudo-logic circuit, and the clock circuit means connects the M pseudo-logic circuits to the first pseudo-logic circuit means. A precharge clock signal pulse is connected to each of the circuit means and each of said M×N logic circuit means to supply a precharge clock signal pulse to the input of each pseudo logic circuit means and to each logic circuit means, and to supply an evaluation clock signal pulse to the input of each pseudo logic circuit means and to each of said logic circuit means. a signal pulse to each pseudo-logic circuit means and each logic circuit means; said pseudo-logic circuit means supplies a pseudo-logic circuit output signal in response to said precharge clock signal pulse; and said evaluation circuit means supplies said is connected to the output of the first pseudo-logic circuit means and the M×N logic circuit means, and supplies M evaluation signals in response to the evaluation clock signal pulse and the pseudo-logic circuit output signal; said first column of circuit means and N logic circuit means is energized by said evaluation clock signal as a first evaluation signal of said M evaluation signals to provide a respective output signal; The signal is provided by the evaluation clock pulse signal only, and the M-1 evaluation signal is provided by the evaluation clock pulse signal.
-1 pseudo-logic circuit means by the evaluation clock pulse signal combined with the evaluation pulse signal provided by the output signal of the first pseudo-logic circuit means. combined with said evaluation pulse signal by said output of said pseudo-logic circuit means corresponding to a column preceding N logic circuit means in a cascade arrangement for providing an output signal upon generation of an evaluation signal subsequent to said first logic circuit means; a multi-level logic circuit fed by said evaluation clock signal pulses.