JPS60105042A - Multilevel logic circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to multilevel logic circuits, and more particularly to multilevel logic circuits that operate with a single clock pulse.

Dynamic film made by metal oxide film silicon method
Multilevel logic circuits require multiphase clocks to ensure correct execution of the desired logic functions. Execution of priority multilevel logic functions requires specifying the required number of clock phases divided into logical time slots to cover the worst case or maximum number of logic levels to be executed. The clock phases are created by dividing the clock signal from the basic signal source. This results in a polyphase of the clock signal, where as a standard every phase is related to the frequency of the fundamental source divided by 1, 2°4, etc., which means that every phase of the clock is a multiple of the frequency of the fundamental source. It means something. In this scheme, the frequency of operation is increased until one phase, only one at any time, becomes critical.

Although MO8 circuits are likely to be economically manufactured, they require a separate lock phase for precharging and logic level evaluation, making these circuits circuit-specific when compared to other forms of logic circuits. Due to its slow speed, it is not routinely utilized in many current dynamic logic applications.

The present invention also relates to digital multiplier circuits, and more particularly to digital multiplier circuits for use with microprocessors where the digital multiplier circuits are controlled by domino control circuits.

A major limitation in the use of field effect transistor circuits, and especially in large scale integrated circuits, is the high speed required for implementing logic circuits with field transistors, such as dynamic logic circuits such as those found in multipliers, and the need for multiple clocks. This is a limitation associated with expanding to applications. In the past, there were multiple clock phases required to implement field effect transistor logic circuits. The precharge phase is necessary to precharge all of the data lines interconnecting the transistors used to form the logic circuit, and the second clock phase is necessary to evaluate the results of the logic execution. be. Polyphase tallock functionality is required when logic circuits are connected together so that each stage depends on the result of the preceding logic stage. The first clock phase precharges all data lines of the logic circuit, the second clock phase evaluates the first logic level, and then the result is evaluated by the sixth clock phase.
logic level, and so on across the entire number of logic levels. Thus, the N logic level function that a field effect transistor is to perform requires N+1 clock phases, one to precharge all of the data lines and one for each logic level to be evaluated. . The time slot arrangement of logic levels thus causes many logic circuits to wait idly for their turn to be evaluated, and the overall result is that these circuits are significantly slower. Thus, there have been no problems when field effect transistor logic circuits are used in handheld computers and similar applications. However, as the demands on circuits become more complex, the need for speed in performing complex logic functions becomes critical. The circuit cannot afford to wait for the appropriate time slot to evaluate in applications requiring high speeds in the nanosecond range.

The minimization of the time in microprocessor devices required to perform multiplication functions is reduced from a large number of microprocessor processing cycles to a relatively small number of microprocessor processing cycles by the implementation of Bardauev multipliers that perform a modified Booth algorithm for digital multiplication. -Reduced to cycle. However, even this reduction in time is insufficient to give field effect transistor type microprocessors the speed necessary for modern technology applications.

The multi-level logic circuit includes a first plurality of logic circuits connected in a cascaded arrangement. A second plurality of pseudo logic circuits is also connected in a cascade arrangement and is used to generate logic pulses for evaluating the first plurality of logic circuits. A clock source includes a first plurality of logic circuits and a second plurality of logic circuits.
providing a precharge signal to the plurality of pseudo-logic circuits, the evaluation circuit combining the output signal from the pseudo-logic signal and the clock signal to obtain an evaluation signal for evaluating the logic state of the first plurality of logic circuits; used for.

A multi-level logic circuit is disclosed in which evaluation pulses are provided that match the utilization of data to be evaluated at each level.

The evaluation circuit is designed to obtain a high-speed programmer sol logic array.
Combined with multi-level logic circuits.

A digital multiplication circuit for a microprocessor utilizes a modified Booth algorithm to perform digital multiplication of two numbers and the Booth algorithm of a selected number n, where n is a positive integer equal to half the number of bits in the multiplier. Operation set includes multiplier ta0: booth recorder to record. Each operation set is applied to a second plurality of n partial product selectors connected in a cascade arrangement by a multiplication set, where each partial performance selector multiplication set selects one of the recorded Booth operation sets. Execute. The outputs of the partial product selectors are summed by a summing device and the -mino circuit device provides an evaluation pulse to each element of the partial product selector upon completion of a Booth operation set connected to the partial product selector.

In multi-level logic circuits, such as multipliers, performance is improved in terms of operating speed by detecting when each level of the multi-level logic circuit is ready for evaluation through the use of domino control circuits.

- The mino control circuit implements a worst-case time delay for the propagation of one clock pulse and its complement to ensure exactly when the corresponding stage of the Booth multiplier is in the position to be evaluated.

The adder includes a plurality of adder circuits connected between selected elements of the plurality of partial product selectors.

To guarantee the earliest possible evaluation of the data in the adder set, the domino control circuit considers the worst case as long as the time delay causes the adder to perform its logical operation and has the data ready to undergo evaluation. It also refers to an adder circuit that is represented when At the end of that time, the P-mino control circuit provides an evaluatable pulse to the next logic level in the multiplier.

These embodiments and the advantages and objectives of the invention will become apparent from a reading of the specification in conjunction with the drawings.

In FIG. 1, a microprocessor is shown including a multiplier 161 according to the invention. Instructions from a decoder 10 terminal (not shown) are provided via pad 103 to an instruction data register 105 and then to a high speed decoder 10.
1, main decoder 109, and address arithmetic unit 1
Added to 11.

Main decoder 109 decodes instructions into control signals used through the microprocessor. These control signals are stored in a control pipeline register 115 which transmits the decoded signals to the appropriate circuitry that meets multiplier 161 via data bundle 117.

Microprocessor 100 basically has two parts: an instruction part, represented by the 1310 area, and a data part, represented by the 1330 area. Address arithmetic unit 111 receives data from instruction data register 105 via displacement multiplexer 135 and from instruction link register 153 or general purpose register 1.
19 through an index multiplexer 137 based on the result of the high speed decoder 107.

After the appropriate arithmetic operations have been performed as directed by carry-break logic 155, the output 123 of address arithmetic unit 111 is latched in common address bus register 125. The output of this register is then
It is applied to the integrated circuit circuit 10 via a parallel 139 for addressing either data memory or input/output address space, or to an internal bus for use as a constant. The output of the address arithmetic unit is also applied to an instruction address multiplexer 145. The output of this multiplexer is the instruction address register 147.
is latched. Another input of the multiplexer, the incremental version of the instruction address register, is provided by 149. Control of multiplexer 145 is provided by sequencing circuit 143. Sequencing circuit 143 controls branches and interrupts received via pad 141. The output of instruction address register 147 is applied to unit 10 via para V151 for addressing instructions in memory. Instruction address register 14
The output of 7 is also latched in instruction ring register 153 after a one cycle delay.

Arithmetic logic unit 127 receives data from general purpose register 119 via A multiplexer 163, and
Data is received from general register 119, machine control register 113, program status register, or interrupt status register via the C multiplexer or from multiplier 161 via the B multiplexer. The carry to the arithmetic logic unit is carried out by the carry logic 12 under the control of the main decoder.
It is performed from 1. The output of the arithmetic logic unit is regulated by saturation logic 129 in case of overflow. The output is then
X multiplexer 157 and Y multiplexer 159
is fed back to general-purpose register 119 via.

When an instruction requiring multiplexing is decoded by main decoder 101, the results of the 5 and O multiplexers in general purpose registers are multiplied together by a multiplier, and the results are latched in a register internal to that block.

FIG. 2, to which reference is now made, provides the basic operating principle of multiplier 1610 through the use of domino control logic contained therein. A block diagram of a domino controlled multi-level logic is shown with an inverter 3 where an inverted clock signal clock is applied to the circuit multi-level logic system 10. A clock source 1 provides a clock signal via conductor 5 to a pseudo load control multilevel logic device. Data source 7 provides parallel data signals, DAT
A 1 ~ DATA N t, (supplied. The domino-controlled multilevel logic device 10 includes MXN logic elements 13. The logic elements are NXM matrices corresponding to a multilevel logic device of M levels with a width of N bits. is divided into words having a width of N logic elements which are connected together in a cascade arrangement according to the data words that constitute it.Furthermore, 7
t-1 There are M domino circuits 15, also connected in a cascade arrangement. Each logic element 13 and each domino circuit 1
5 is precharged by a clock signal that activates transistor 170 gates, and is
A voltage supplied from an external voltage source is applied to the corresponding logic element 13 and domino circuit 15.

1.1 logic element 19.1j (N-1) logic element 21; The N logic elements 25 are evaluated by a clock signal activated transistor 27 which connects the corresponding logic element to a reference voltage, V(id, as indicated by arrow 31. The 1.1 tF mino circuit 29 is also evaluated by the clock signal. C. This is because the 1°1 domino circuit 29 is connected to represent the worst case state, that is, the evaluation pulse for any of the logic elements 13 connected to the first row is corrected by the inverting amplifier 33. Domino control multilevel logic device second at a time to ensure evaluation
This is because it is supplied to the theoretical elements 13 placed in the rows. Of course, the logic elements of the second row are connected in a cascade arrangement with the logic elements of the first row, thus ANDing the clock signal supplied from inverter 3 and the output of inverter 33.
The evaluation can be performed at the same time that an evaluation pulse is applied to the date of the transistor 37 which is connected together with the transistor 17 to form an AND date. The data from the data source 9 is connected to the corresponding input terminal of the first row of logic elements present, and the Q terminal is connected at the input terminal to the corresponding logic element of the second row, thus creating a cascade connection. Must pay attention. This configuration is perfectly maintained throughout all M rows. The domino circuits 15 in each row are similarly connected in a cascade arrangement, each with a signal propagation delay to ensure that the corresponding logic does not complete all logic operations when the evaluation pulse is applied to the output of the inverter 33. The conditions are considered to be the worst. Evaluation of Domino control multilevel logic device 10 is (
M-1) Only domino circuit device is required, but logic element 1
A storage pause may be provided to the final output inverter 33 of the Mr Domino path 39 if the data provided to the output of 3 is a member of M rows and is to be stored in a storage location. Thus, the occurrence of evaluation pulses for each row of logic elements is compared to the final NO minos of the row, which falls with each domino making the evaluation pulse. This provides asynchronous operation for evaluating field effect transistor logic circuits.

FIG. 6, to which reference is now made, is a block diagram of multiplier 161 of FIG. 1, which includes the domino principle described with respect to FIG. The multiplicand is transferred from the C multi-breather 16 in FIG. 1 via the data bus 115 to six partial product selectors,
Lines 193, 195° 197. 201, 209 and 213
added to.

The multiplier is applied from general register 5,159 to booth recorder 217 via wire bundle 177.

In the embodiment of FIG. 6, the multiplier is 173 bits and the multiplicand is 16 bits. However, the N provided here may apply to any size multiplier and any size multiplicand. All of the circuits described in FIG. 6 are precharged by the first stage clock QP, as shown in FIG. 2, and continued for a selected time period as described for FIG. 4 by an evaluation pulse. All of the partial product selectors are evaluated simultaneously by clock QE.

The first partial product selector 193 is controlled by a booth recorder 219 using multipliers 10, 11 and 12. The second partial product selector 195 has multiplier bits 8 and 9.
and 10. The third s type selector 197 is multiplier bit 6
．． Controlled by booth recorder 223 using 7 and 8. Fourth partial product selector 201ii is controlled by Booth recorder 225 using multiplier bits 4, 5 and 6. The fifth partial product selector 209 is controlled by the Booth recorder 22γ, which uses multiplier bits 2, 6 and 4. The sixth partial product selector is multiplier bits 0, 1
．． and a booth recorder 229 used. The first three selectors 193, 195 . and partial products from 197 are stored in the carry-save adder (C
8A) is added by 199. 0E34 is the evaluation provided by partial product selector delay circuit 179? Rated by Yarus. The output of C8A 199 and the partial products from selector 201 are summed by C8A 207.

0EIA 207 evaluation pulse is C8A delay circuit 181
Powered by. The output of C3A207 and the partial product from selector 209 are converted to Calo7 by C8A211.
5! fl le. (!SA:? 11 evaluation pulse is O8
Supplied by A delay circuit 183. C8A'l
11σ) The partial product from the output and selector 213 is C8
Added by A 215. C8A 215σ) evaluation norm is provided by the 0SA delay circuit 185. The output of 0EiA 215 enters intermediate register 219.

This completes one clock cycle of activity. On subsequent clock cycles, the contents of intermediate register 119σ are added by carry ripple adder (ORA) 227. This creates a product that is latched in product register 229. The product register is then applied to arithmetic logic unit 127 via B maltezolexer 165.

Referring now to FIG. 4, the timing diagram of FIG. 6 is shown for use in conjunction with FIG. In FIG. 3, data is entered via conductor 175 at the bottom of the page;
It flows through the partial product selector and carry-save adder and eventually emerges from the product selector 229 at the top of FIG. The separation between the intermediate register 219 and the carry ripple adder 227 is due to the completion of the first stage 365 and the second stage Fj! The beginning of 36γ is shown. This separation is indicated by line and arrow combination 369. In Figure 4, vertical line 3
21 and 326 represent the start of a multiplication cycle, where the precharge clock precharges the circuitry inside multiplier 1610, including the carry-save adder and selector, as shown by arrow 337, and the It provides an input to conductor bus 175 and also precharges the current carry ripple adder 227, indicated by dimension line 341. At vertical line 323, the precharge clock is removed as shown by waveform 329 and the evaluation clock is provided as shown by waveform 331. All partial product selectors are evaluated at times between vertical lines 323 and 338, as indicated by dimension line 351. The carry-save adder (C8A) is
The first carry-save adder 199 is evaluated sequentially in the time period between vertical lines 338 and 345. The evaluation pulse for carry-save adder 199 is provided by PP8 delay circuit 179. 10th
SA delay circuit 181 provides a second evaluation pulse to 208A 207 during the time between vertical line 345 and vertical line 347. The C8A evaluation pulse is indicated by dimension line 355. The 30th SA evaluation pulse is provided to the 3rd csA 211 during the time indicated by dimension line 357, which is the distance between vertical lines 347 and 349. 40th EI
A 215 is connected to the node supplied by the 30th SA delay circuit 185 with m+? 'f[+ is applied. This pulse occurs between vertical line 349 and vertical line 365 in FIG. 4 and is represented by dimension line 359. The result of the evaluation is stored in intermediate register 219 during the time between vertical line 325 and vertical line 326, thereby completing the multiplication, and in the next cycle the data contained in intermediate register 219 is are added to the product register 229 and added to the arithmetic logic unit 227 of FIG. 1. FIG. The multipliers disclosed and discussed above are therefore capable of performing complex multiplication functions. In addition, information can be provided to the arithmetic logic unit at a rate of one per clock cycle.

FIGS. 5A and 5B show a 16-bit
1 is a simplified schematic diagram of a 16-bit multiplier; FIG. The first partial product selector row 193 contains nineteen cells 191, which receive the most significant bits in registers 370 and 372, while the least significant bit is added to cell 314 of FIG. 5B. Multiple cells for the most significant bit are required because the most significant bit is a sign bit and is applied to three or more separate loads. Two special cells are required to perform booth operations.

The decoded Booth operan V will cause the partial product selector to perform the function of the Booth operand. These features are listed in Table 1. In the present application of the preferred embodiment of FIG. 5, at A, the number is doubled by moving each bit to the left. Table 2 shows the number of cells in each row, and Table 1 shows the truth table for the decoding Booth algorithm.

Table 1 6-bit number 000 Add O to the value in the previous row of the register 001 Add the multiplicand to the value in the previous row of the register 010 Add the multiplicand to the value in the previous row of the register 011 Add the multiplicand to the value in the previous row Add twice the value 100 Subtract twice the multiplicand from the previous value 101 Subtract the multiplicand from the previous value 110 Subtract the multiplicand from the previous value 111 Subtract 0 from the previous value Table 2 Rows, cells and reference numbers Cell Number 1 Partial product selector 193. 19 2 Partial product selector 195. 19 3 Partial product selector 197. 19 4 Carry-Save Adder 199. 185 Partial product selector 201. 19 6 Carry-save adder 211. 187 Partial product selector 213. 19 8 Carry-save adder 215. 189 Intermediate register 219. 54 10 Carey-Rizzol adder 227. 2611
Product register 229. 28 A design limit of no more than two loads per source tooth was used in the preferred embodiment to minimize time delays, but the worst-case condition is thus guaranteed to be one load. ing. This restriction is taken into account during the generation of the evaluation pulse.

Extra cells 371 and 375 are provided 1 and are used to execute the Booth algorithm provided by the first Booth recorder 219. The output of the cell is shifted two bits to the right and applied to the second partial product selector 195. The result of the movement is transferred to the wire R (intermediate) via the conductor bundle 376.
It is added to register 219 and accumulated there. The output of the second partial product selector is the third partial product selector 197, row 1
99 and its output is added to the carry-save adder. Each carry-save adder used to create a row of carry-save adders is a full adder;
Therefore, three inputs are required. The reason is that each output of the first, second and third partial product selectors is
The output of each full adder 310 is then added to the next full adder 310, where Its output is combined with the output of the next partial product selector σ] to provide the summation result of the multiplication function performed by the Booth algorithm to intermediate register 219 according to the function described with respect to FIGS. 6 and 4. are summed by the previous carry-save adder 310, which also includes the carry output, until

FIG. 6 is a schematic diagram of each booth recorder stage 380;
essentially includes a programmable logic array 381, where the Booth algorithm
Decorated by 1 and Noah Date 385, 38
7 and an inverter 389 are added to the rich logic device 383.

The output of logic device 383 is represented by dimension line 351 in FIG.
Under the control of the evaluation pulse QE1 supplied by
is applied to the partial product selector via data bus 391.

FIG. 7 is a schematic diagram of each partial product selector whose input is provided via data bus 400 from a Booth recorder. The output from each partial product selector is provided via data bus 403. The input of each selector cell 189 is provided via data bus 175 and inverted by 191. However, there is no input such as the least significant bit position, and then circuit 187 is biased by circuit 405. The bias is created by two depletion type transistors connected to a voltage source, not shown, as shown in FIG. Partial volume movement is accomplished by passages 402 and 404.

A PRR delay circuit 179 is shown in FIG. 8 and is used to delay the evaluation pulse applied to the carry-save adder circuit 199 by the propagation delay representing the worst case condition of the partial product selector. It includes a plurality of transistors 407 having outputs connected and combined by a Nor gate 409 and an amplifier 411, the result being a 10th SA delay circuit 181 and a 10th S
It is added to A row 199. Throughout the illustrations, QE represents the evaluation pulse and QP represents the precharge pulse.

FIG. 9 is a schematic diagram of carry save 7Ill K circuit 205 and O8A delay circuit 183, which circuits are identical. For addition of the circuit by means of a summation circuit obtained by implementing transistor logic 425 with an output supplied by data bus 427, inverter 4
Three inputs are provided at 21, 422 and 423.

This is a full adder circuit and provides a sum output and a carry output via data bus 421.

FIG. 10, which is similar to the circuit of FIG.
Each stage of 23 is represented. A carry circuit 431 separating each group of five carry ripple adders as shown in FIG. 5 is shown in FIG.
3 and 2 MOS) transistors 435. FIG. 10B is a circuit that provides carry power for a carry ripple adder.

FIGS. 12A and 12B are intermediate registers in the output buffer stage and also demonstrate that the Microprocessor controls the loading and storage of data in the transistors at 471.

FIG. 13 is the storage control circuit of FIG.

FIG. 14 shows a schematic diagram of the circuit used to delay the output of the two least significant intermediate register bits (which need not be accumulated) that go into the product register.

FIG. 15 is a block schematic diagram of product register 229.

The storage control circuit is shown in FIG. 13, again it is used with the scan control and precharge pulses and evaluation pulses provided by the computer, and the or date 444°445.446, and overall 4
It includes a gated-OR function performed by a transistor circuit represented at 57.

Referring now to FIG. 16, a schematic diagram of a programmer logic array 100 having an output connected to memory 2 is shown. Programmable logic array 100 includes two stages in which the data appearing on data bus 9 at first decode stage 72 is divided into X coordinates represented by data input lines and vertical lines 75 . The information is decoded by placing a transistor 73 between γ6 and the y coordinate represented by 77 and 79. When the data is decoded, it is applied to the second stage 81, which is the output stage;
In the case of FIG. 16, it is used to drive a load which is memory as well as other circuitry connected to data bus 93. Output stage programming is transistor 8
3, which is represented by vertical lines 75.76.77,
and horizontal line 85° 870 connection. The pseudo load circuit 15 is connected to the worst case condition by a single transistor 37 connected between the X and Y axes of the programmable logic array 100. Obviously, the more transistors that conduct, the faster the line connected to transistor 27 will discharge. Therefore, the worst case arrangement is one transistor on and all but one data line transistors off. Thus, in the embodiment of FIG. 16, transistor 8 is biased on and transistors 2, 4 and 6 remain biased on. The enable signal is uncoupled with the clock signal by a date 37 and 2T structure contained within pseudo-logic 15. This causes the output of the inverter 33 to be pulsed, thus enabling transistor 137 so that if the clock signal is removed from transistor 17, the second stage 81 of the programmable logic array is evaluated.

The output is applied to data bus 83 and memory 2, where if second pseudocircuit 101 is evaluated, inverter 133 provides a storage pulse to memory 2, and the output of the programmable logic array is applied to memory 2. be remembered.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a microprocessor including a multiplier according to the present invention, FIG. 2 is a block diagram of a domino control logic circuit, FIG. 3 is a block diagram of the multiplier of FIG. 1 according to the present invention, and FIG. a timing diagram of the multiplier of FIG. 6; FIGS. 5A and 5B are simplified schematic diagrams of the multiplier of FIG. 6;
6 is a schematic diagram of each Booth decoder stage in FIG. 5B, and FIG. 7 is a schematic diagram of the partial product selector 191 in FIGS. 5A and 5B.
FIG. 8 is a schematic diagram of the PPR delay circuit in FIG. 5A, FIG. 9 is a schematic diagram of the carry-save adder used in FIG. 5, and FIG. 11 is a schematic diagram of a carry-riggle adder according to the present invention, and FIG. 11 shows the carry circuit used in the embodiment of FIG. 5, and FIGS. 12A and 12B.
The diagram shows the intermediate register in the output stage of Figure 5, Figure 13 shows the storage control circuit of Figure 5, Figure 14 shows the buffer control circuit of Figure 5, and Figure 15 shows a schematic of the intermediate register 21 of Figure 5. figure,
FIG. 16 is a schematic diagram of a programmer sol logic arrangement embodying the invention. Description of symbols: 10-v mino control circuit; 100-microprocessor; 161-multiplier 191. 193.195,197,201,209.213 partial product selector il 99,207,211. 215.227-O8A; 119,219-intermediate register, 229-product register; 217.219°221.2
23,225,227.229-booth recorder;3
81-Programmable logic array drawing 1.) is;: (no change in content), U Ft'gJ FIG, 5^121#) 1[i, 5At31 p et al. 116 Ft'1.6 L---f Ft'g, 7 Ft'g, 8 Fit), 9 /'/evening, /24 h't1. /211 Ft'g, /J p Ft'y, /4 Procedural Amendment (Mutsu) September 180, 1980 Mr. Commissioner of the Japan Patent Office 1, Indication of the case 1982 Patent Application No. 164719 2, Title of invention Multi Level logic circuit 3, Relationship with the case of the person making the amendment 14th serial 1 Applicant address 4, Agent 5, Date of amendment order 1968 - Month I” 8. Contents of the amendment As shown in the attached sheet #! Engraving of Book Aa (no change in content) 3. Procedural amendment (formality) Showa O/2016/2016-Z Date Mr. Commissioner of the Patent Office 1. Indication of the case Showa (2nd year Patent Application No. 11-277 3) Person making the amendment (relationship with 1 +

Claims (1)

[Claims] [11Nfk as a positive integer, a first plurality of N logic circuit devices connected in a cascade V array and performing logical operations; MIf: as a positive integer, connected in a cascade P array; a second plurality N connected to provide a plurality M evaluation pulses;
a clock circuit device for supplying a precharge signal to the plurality of logic circuit devices and each element of the pseudo logic circuit device; and a plurality of evaluation pulses for each element of the plurality of logic circuit devices. A multilevel logic circuit comprising: a circuit device that evaluates by corresponding elements; and a multilevel logic circuit. (2) A multilevel logic circuit according to claim 1, characterized in that it includes a programmable logic arrangement. (3) In the multilevel logic circuit according to claim 2, the programmable logic array includes X and y
an xxy matrix logic device, each representing the number of data input lines and decoder V lines, each a positive integer, and one logic unit connected in the worst case to provide usable pulses to the xxy matrix logic device The multi-level logic circuit, characterized in that it includes: a pseudo-logic i-location including an array device; (4) In the multilevel logic circuit according to claim 6, the programmable logic array further comprises an output providing an output signal representing the program decoded by the signal on the data input line and the program stored in the XX7 matrix. The multilevel logic circuit characterized in that the multilevel logic circuit includes a stage device, the output stage device being enabled by an enable signal. (5) In the multilevel logic circuit according to claim 1, the circuit device includes: The multilevel logic circuit characterized in that it includes an and-date device for combining the precharge signal with the evaluation signal such that when the precharge signal is absent and the evaluation signal is present, the corresponding logic circuit device is evaluated. (6) When the plurality of logic circuit devices execute a logical operation, connecting the first plurality of logic circuit devices in a cascade arrangement; and the step of connecting the plurality of pseudo logic circuit devices from the second plurality of pseudo logic circuits connecting a second plurality of pseudo-logic circuit devices in a cascade arrangement when providing a plurality of evaluation pulses; and supplying a precharge signal to each element of the plurality of logic circuit devices and the pseudo-logic circuit device. and evaluating each element of a plurality of logic circuit devices by corresponding elements of a plurality of evaluation pulses. (7) an xxy matrix logic device, where x and y are both positive integers representing the number of data input lines and decode lines, respectively; and a worst-case arrangement for providing evaluation pulses to the xxy matrix logic device. a pseudo logic device including one connected logic array device. (8) A programmer-sol logic arrangement according to claim 7, which output stage device provides output signals representing the program decoded by the signals of the data input link and the program stored in the xxy matrix device. The programmable logic array further comprising: (9) A Booth recorder device for recording a multiplier N Booth operation set, where N is a positive integer equal to half the number of bits of the multiplier, and M is a positive integer;
a plurality of N partial product selector devices connected in a cascade arrangement of multiplicand sets of length M, each element of which is connected to an element of M operations to record a set of Booth operations; An addition device that adds the contents of the plurality of N partial product selector devices and the plurality of N partial product selector devices that are executed on a set of multiplicands,
The following evaluation evaluates the corresponding elements of a plurality of partial product selector devices having the adder placed between the elements of a plurality of N partial product selector devices and an input circuit connected to the output of the corresponding adder. A digital multiplier circuit comprising: a V mino device having an adder circuit device for generating pulses; In the digital multiplication circuit according to claim 9, the domino circuit device comprises: a clock device for supplying a precharge signal; a partial product stage device connected in a cascade arrangement for converting the precharge signal into an evaluation signal; , The digital multiplication circuit has the following characteristics. 0υ In the digital multiplication circuit according to claim 2, the Pmitsu circuit device further comprises a plurality of pseudo load devices and a booth connected to the corresponding partial product selector device.
a plurality of summing circuits connected to preselected pseudo load devices that provide evaluation pulses to each element of a plurality of N partial product selector devices upon completion of a set of operations; Multiplication circuit. (12+) In the digital multiplication circuit according to claim 9, the addition device includes a plurality of full addition circuit devices that combine the first human power, the second human power, and the sixth human power. Circuit. α3) In the digital multiplication circuit according to claim 11, each of the plurality of adder circuit devices includes a full adder circuit device having a first power, a second power, and a sixth power. The digital multiplication circuit. In the digital multiplier circuit according to claim 9, the addition device includes an output of the first multiplicand set from the preselected first partial product selector device and an output of the first multiplicand set from the preselected second partial product selector device. the output of the second set of multiplicands and the third
The digital multiplier circuit comprising a first plurality of full adder circuit devices for summing the outputs of a set of multiplicands. In the digital multiplier circuit according to claim 14, the adder further comprises an output of a fourth set of multiplicands of a fourth partial product selector device selected in advance, which is an output of the first set of full adder circuit devices. The digital multiplication circuit characterized in that it includes a second set of full adder circuit devices to be combined. tte In the digital multiplier circuit according to claim 10, the adder device is further connected to combine the output of the second set of full adder circuit devices with a fifth multiplicand set of a preselected fifth partial product selector device. The digital multiplication circuit, characterized in that it includes a sixth set of full adder circuit devices. α'7) In the digital multiplier circuit according to claim 16, the adder device further combines the outputs of the sixth set of full adder circuit devices with a sixth set of multiplicands of a preselected sixth partial product selector device. A fourth set of full adder circuit devices. QgIW A digital multiplication circuit according to claim 9, further comprising an intermediate set of registers for storing outputs of a plurality of partial product selector devices and an adder device. . (I9) A digital multiplication circuit according to claim 18, further comprising a second addition circuit device that selectively combines the outputs of the intermediate register device to obtain the product of the multiplicand and the multiplier. The digital multiplication circuit. (20) The digital multiplication circuit according to claim 19, further comprising: a plurality of storage register devices for storing the product of a multiplier and a multiplicand. (211) decoding the multiplier into a set of N Booth operations as a positive integer equal to half the number of bits of the Nk multiplier; Booth operation
executing a set on a multiplicand, wherein each element of a plurality of N partial product selector devices is connected to receive an element of a set of N operations; and a plurality of N partial product selectors. adding the contents of the device with the contents of a summing device placed between the elements of a plurality of N partial product registers; and a plurality of elements of a partial product selector device having an input circuit connected to the output of the corresponding summing device. A method for performing digital multiplication, comprising: generating a next evaluation pulse for evaluating. (2. In the method according to claim 21, the step of generating the next evaluation pulse includes the steps of supplying a precharge signal and converting the precharge signal into an evaluation signal. The said method.