JPS58155845U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS58155845U JPS58155845U JP5408382U JP5408382U JPS58155845U JP S58155845 U JPS58155845 U JP S58155845U JP 5408382 U JP5408382 U JP 5408382U JP 5408382 U JP5408382 U JP 5408382U JP S58155845 U JPS58155845 U JP S58155845U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- active element
- hermetically sealed
- coated
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例の気密封止形半導体パッケージを示す図
、第2図は半導体素子面に樹脂コーテングした従来例を
示す側面図、第3図は本考案の一実施例である気密封止
形半導体パッケージを示す断面図、第4図は本考案の一
実施例である半導体素子を示す要部側面図である。
図において、12はセラミック基板、13は半導体素子
、14はバット電極、15はワイヤ、16は外部リード
、17は不純物拡散層、18はポリイミド樹脂を示す。Figure 1 is a diagram showing a conventional hermetically sealed semiconductor package, Figure 2 is a side view of a conventional example in which the semiconductor element surface is coated with resin, and Figure 3 is a hermetically sealed semiconductor package that is an embodiment of the present invention. FIG. 4 is a cross-sectional view showing a shaped semiconductor package, and FIG. 4 is a side view of a main part showing a semiconductor element which is an embodiment of the present invention. In the figure, 12 is a ceramic substrate, 13 is a semiconductor element, 14 is a bat electrode, 15 is a wire, 16 is an external lead, 17 is an impurity diffusion layer, and 18 is a polyimide resin.
Claims (1)
素子を装着し、該基板と同−材又は金属材のキャップで
ハーメチックシールする気密封止形半導体装置であって
、該半導体素子の能動素子mlより低面に信号線接続用
バット面を設けて段差のある境界面となし、前記能動素
子面にはa線遮蔽用樹脂をコーテングし、前記バット面
の電極は不純物拡散層を介して該能動素子と接続されて
なることを特徴とする半導体装置。A hermetically sealed semiconductor device in which terminals are provided on the outside, a semiconductor element is mounted approximately in the middle of a heat-resistant insulating substrate, and hermetically sealed with a cap made of the same material as the substrate or a metal material, the semiconductor device A butt surface for signal line connection is provided on a lower surface than the active element ml of the device to form a stepped boundary surface, the active element surface is coated with a-ray shielding resin, and the electrode on the butt surface is coated with an impurity diffusion layer. A semiconductor device characterized in that the semiconductor device is connected to the active element via the active element.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5408382U JPS58155845U (en) | 1982-04-14 | 1982-04-14 | semiconductor equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5408382U JPS58155845U (en) | 1982-04-14 | 1982-04-14 | semiconductor equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58155845U true JPS58155845U (en) | 1983-10-18 |
Family
ID=30064715
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5408382U Pending JPS58155845U (en) | 1982-04-14 | 1982-04-14 | semiconductor equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58155845U (en) |
-
1982
- 1982-04-14 JP JP5408382U patent/JPS58155845U/en active Pending
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