JPS5846449U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPS5846449U JPS5846449U JP14149981U JP14149981U JPS5846449U JP S5846449 U JPS5846449 U JP S5846449U JP 14149981 U JP14149981 U JP 14149981U JP 14149981 U JP14149981 U JP 14149981U JP S5846449 U JPS5846449 U JP S5846449U
- Authority
- JP
- Japan
- Prior art keywords
- ceramic cap
- recess
- resin
- semiconductor equipment
- periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図はセラミックキャップを備えた従来の半導体装置
の正面図、第２図は第１図の半導体装置の□セラミック
±ヤツプ裏側の凹部底面に対するポリイミド樹脂層形成
要領を示す正面部、第３図は第２図の一部拡大図、第４
図は本考案に係る半導体装置の実施例を示す正面図、第
５図は同他の例を示す正面図で、図中、１はセラミック
ベース、２はチップ、３は外部リード、４はワイヤ、１
１゜１１′はセラミックキャップ、１２．１２’は凹部
、１３．１３’は底面、１４．１７はスリット、１ｓ、
ｔｉはポリイミド樹脂層、１６．１６’は低融点ガラス
である。Figure 1 is a front view of a conventional semiconductor device equipped with a ceramic cap, Figure 2 is a front view of the semiconductor device shown in Figure 1, showing a procedure for forming a polyimide resin layer on the bottom of the recess on the back side of the □ceramic cover, and Figure 3. Figure 4 is a partially enlarged view of Figure 2.
The figure is a front view showing an embodiment of the semiconductor device according to the present invention, and FIG. 5 is a front view showing another example. In the figure, 1 is a ceramic base, 2 is a chip, 3 is an external lead, and 4 is a wire. ,1
1゜11' is a ceramic cap, 12.12' is a recess, 13.13' is a bottom surface, 14.17 is a slit, 1s,
ti is a polyimide resin layer, and 16.16' is a low melting point glass.
Claims (1)
上に低融点ガラスを介しセラミックキャップを封着して
なり、前記セラミックキャップ裏側の前記チップに対向
する部分には凹部が設けられ、該凹部の底面に樹脂を滴
下することにより樹脂層が形成された半導体装置におい
て、前記セラミックキャップの凹部底面の周辺部に、前
記樹脂をせきとめるためのスリットを連続して設けたこ
とを特徴とする半導体装置。A ceramic cap is sealed on the periphery of a base on which a chip connected to an external lead is mounted, via a low-melting glass, and a recess is provided on the back side of the ceramic cap in a portion facing the chip. A semiconductor device in which a resin layer is formed by dropping resin on the bottom surface, characterized in that a slit for damming up the resin is continuously provided in the periphery of the bottom surface of the recess of the ceramic cap. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14149981U JPS5846449U (en) | 1981-09-24 | 1981-09-24 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14149981U JPS5846449U (en) | 1981-09-24 | 1981-09-24 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5846449U true JPS5846449U (en) | 1983-03-29 |
Family
ID=29934597
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14149981U Pending JPS5846449U (en) | 1981-09-24 | 1981-09-24 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5846449U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60110878U (en) * | 1983-12-28 | 1985-07-27 | カシオ計算機株式会社 | Fixed structure of display panel |
-
1981
- 1981-09-24 JP JP14149981U patent/JPS5846449U/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60110878U (en) * | 1983-12-28 | 1985-07-27 | カシオ計算機株式会社 | Fixed structure of display panel |
| JPH0219827Y2 (en) * | 1983-12-28 | 1990-05-31 |
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