JPS5869954U - semiconductor equipment - Google Patents

semiconductor equipment

Info

Publication number
JPS5869954U
JPS5869954U JP1981164625U JP16462581U JPS5869954U JP S5869954 U JPS5869954 U JP S5869954U JP 1981164625 U JP1981164625 U JP 1981164625U JP 16462581 U JP16462581 U JP 16462581U JP S5869954 U JPS5869954 U JP S5869954U
Authority
JP
Japan
Prior art keywords
semiconductor equipment
semiconductor device
container
abstract
lead wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1981164625U
Other languages
Japanese (ja)
Inventor
秀樹 山田
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP1981164625U priority Critical patent/JPS5869954U/en
Publication of JPS5869954U publication Critical patent/JPS5869954U/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案に係る従来の半導体装置用パッケージの
断面図を示す。第2図は本考案の一実施例を示す半導体
装置用パッケージの断面図、第3図は第2図の半導体装
置用パッケージの底面図を示す。 1・・・・・・ペレット、2・・・・・・アイランド、
3・・・・・・リード線、4・・・・・・パッケージ基
体。
FIG. 1 shows a sectional view of a conventional package for a semiconductor device according to the present invention. FIG. 2 is a sectional view of a semiconductor device package showing an embodiment of the present invention, and FIG. 3 is a bottom view of the semiconductor device package of FIG. 2. 1...Pellet, 2...Island,
3...Lead wire, 4...Package base.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 半導体装置を封止する容器の下面とほぼ同一面上にその
先端部分が位置するように該容器内で成形されたリード
線を有してなる半導体装置。゛
A semiconductor device having a lead wire formed within a container so that its tip portion is located on substantially the same plane as the bottom surface of the container for sealing the semiconductor device.゛
JP1981164625U 1981-11-04 1981-11-04 semiconductor equipment Pending JPS5869954U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1981164625U JPS5869954U (en) 1981-11-04 1981-11-04 semiconductor equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1981164625U JPS5869954U (en) 1981-11-04 1981-11-04 semiconductor equipment

Publications (1)

Publication Number Publication Date
JPS5869954U true JPS5869954U (en) 1983-05-12

Family

ID=29956856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1981164625U Pending JPS5869954U (en) 1981-11-04 1981-11-04 semiconductor equipment

Country Status (1)

Country Link
JP (1) JPS5869954U (en)

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