JPS5815268A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5815268A JPS5815268A JP56113891A JP11389181A JPS5815268A JP S5815268 A JPS5815268 A JP S5815268A JP 56113891 A JP56113891 A JP 56113891A JP 11389181 A JP11389181 A JP 11389181A JP S5815268 A JPS5815268 A JP S5815268A
- Authority
- JP
- Japan
- Prior art keywords
- emitter
- electrode
- base
- contact
- aluminum
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 3
- 239000007772 electrode material Substances 0.000 claims 4
- 238000000465 moulding Methods 0.000 claims 1
- 239000012811 non-conductive material Substances 0.000 claims 1
- 239000011347 resin Substances 0.000 claims 1
- 229920005989 resin Polymers 0.000 claims 1
- 239000000126 substance Substances 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract description 3
- 238000005275 alloying Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 6
- 238000000605 extraction Methods 0.000 description 6
- 229910000838 Al alloy Inorganic materials 0.000 description 5
- 239000000758 substrate Substances 0.000 description 5
- 125000004429 atom Chemical group 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- AZDRQVAHHNSJOQ-UHFFFAOYSA-N alumane Chemical group [AlH3] AZDRQVAHHNSJOQ-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- JXBAVRIYDKLCOE-UHFFFAOYSA-N [C].[P] Chemical compound [C].[P] JXBAVRIYDKLCOE-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000008094 contradictory effect Effects 0.000 description 1
- 239000013256 coordination polymer Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 230000003394 haemopoietic effect Effects 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- -1 hydrogen ions Chemical class 0.000 description 1
- 125000002887 hydroxy group Chemical group [H]O* 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 125000002346 iodo group Chemical group I* 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
- Bipolar Transistors (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、バイポーラトランジスタの電流増幅率ｈＦｌ
ｌ や１１ｆＭ音特性を改善する半導体装置に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION The present invention provides a current amplification factor hFl of a bipolar transistor.
The present invention relates to a semiconductor device that improves l and 11fM sound characteristics.
従来、バイポーラトランジスタやバイポーラＩＣの標準
的な電極形成工程は、次のように行なっていた。シリコ
ン基板もしくはエピタキシャル島領域の主表面の所定箇
所にポロン又Ｃ丁リンなどの不純物を熱拡散あるいはイ
オン注入によって導入しテ、エミッタ領域、ベース領域
およびコレクタ電極導出のための高濃度領域を形成し、
しかる後、これらの拡散領域の表面上の酸化被膜の一部
をエツチングで除去することによって、エミッタコンタ
クト用開孔、ベースコンタクト用開孔、およびコレクタ
コンタクト用開孔を形成する６次に、アルミニウム（以
下Ａ／と書く）などの金属を全面蒸着し、写真蝕刻工程
（以下ＰＲ，工程と称す）を行うことによって配線パタ
ーンを形成した後、４００〜５００℃の熱処理（以下ア
ルミアロイ工程と称す）を行うことにより、ＡＩとコン
タクト用開孔内のシリコンとのオーミ、り性接触を得る
ことができる。このアルミアロイ工程において、コンタ
クト用開孔内のシリコンは一部Ａ／電極に拡散し、逆に
／ｌ原子はコンタクト用開孔内のシＩＪ コン中へ拡散
していった後のシリコンの空孔へ拡散する。従って、コ
ンタクト用開孔内のＡ／電極の面積が大きい場合は、Ａ
Ｉ原子がコンタクト用開孔内のシリコンに大量に拡散し
、より深い部分にまで達する。この現象は拡散深さの浅
いエミ、り領域に於いて特に問題となり、エミ、り、ペ
ース接合が浅い場合に於いては、Ａ／原子がエミッタ・
ベース接合まで到達するため、この接合の結晶性を劣化
させ、エミッタ・ベース接合の逆方向リーク電流全増大
させ、ｈＰＨの低下や絶音の増大′ｌｔまねいていた。Conventionally, the standard electrode forming process for bipolar transistors and bipolar ICs has been carried out as follows. Impurities such as poron or carbon phosphorus are introduced into predetermined locations on the main surface of the silicon substrate or epitaxial island region by thermal diffusion or ion implantation to form high concentration regions for leading out the emitter region, base region, and collector electrode. ,
Thereafter, a portion of the oxide film on the surface of these diffusion regions is removed by etching to form an emitter contact hole, a base contact hole, and a collector contact hole. (hereinafter referred to as A/) is deposited on the entire surface, and a wiring pattern is formed by performing a photolithography process (hereinafter referred to as PR), followed by heat treatment at 400 to 500°C (hereinafter referred to as aluminum alloy process). ), it is possible to obtain ohmic contact between the AI and the silicon in the contact hole. In this aluminum alloy process, some of the silicon in the contact hole diffuses into the A/electrode, and conversely, the /l atoms diffuse into the silicon vacancies in the contact hole. Diffuses into the pores. Therefore, if the area of A/electrode in the contact hole is large,
A large amount of I atoms diffuse into the silicon within the contact opening, reaching deeper parts. This phenomenon is particularly problematic in the emitter region where the diffusion depth is shallow, and when the emitter, paste junction is shallow, the A/atom becomes the emitter.
Since it reaches the base junction, the crystallinity of this junction is degraded, and the reverse leakage current of the emitter-base junction is increased in total, leading to a decrease in hPH and an increase in the sound quality.
従ってエミ、り領域が深くかつ、コンタクト用開孔とエ
ミ、り領域表面周囲との距離が長い程、アルはニウムの
拡散による接合破壊はないことになるが、逆に高周波特
性を改善することはできない。Therefore, the deeper the emitter/reflection region is and the longer the distance between the contact hole and the surface of the emitter/reflection region, the longer the distance between the contact hole and the surface of the emitter/reflection region, the less the junction will be destroyed due to the diffusion of aluminum, but on the contrary, the high frequency characteristics will be improved. I can't.
一方、実験的にはエミッタコンタクト用開孔の周囲がエ
ミッタ領域の表面周囲の近くまで形成されている電極構
造ではｈｙｍの、絶対値並びに直線性が向上し、１／ｆ
雑音も改善されることが知られている。この現象はアル
ミアロイ工程に於いて、酸化膜中に含まれる水酸基（−
ＯＨ）がＡノと酸化反応を生じる際に、水素イオン（Ｈ
）が発生し、これが８ ｉ −８ｉＯｚ 界面付近の
電子を捕獲し、表面準位密度を減少させる結果である為
と解釈されている。On the other hand, in an electrode structure in which the periphery of the emitter contact hole is formed close to the surface of the emitter region, the absolute value and linearity of hym are improved, and 1/f
It is known that noise is also improved. This phenomenon occurs during the aluminum alloy process when hydroxyl groups (-
When OH) undergoes an oxidation reaction with A, hydrogen ions (H
) occurs, which is interpreted to be the result of capturing electrons near the 8 i -8iOz interface and reducing the surface state density.
近年、バイポーラＩＣに於いては、高周波化、省エネル
ギー化に対する特性改善と、ＬＳＩ化に伴う素子面積縮
少化への強い要求から、接合部の深さがしだいに浅くな
る傾向にあり、またコンタクト用開孔の大きさもｌＯμ
×１０μから４μ×４μへ縮少化が進行中である。この
為、上述したアルミ電極からのエミ、り・ペース接合附
近へアルミ原子が拡散して、接合を劣化させる危険性は
増大している。しかしながら、一方でｈＰＩｌの特性や
ｘ／ｆ雑音の改善もきびしい要求がかされてきている。In recent years, the depth of junctions in bipolar ICs has been gradually becoming shallower due to the strong demand for improved characteristics for higher frequencies and energy saving, and for smaller element areas due to the shift to LSI. The size of the opening is also lOμ
Reduction from ×10μ to 4μ×4μ is in progress. For this reason, there is an increased risk that aluminum atoms will diffuse from the aluminum electrode into the vicinity of the emitter/paste bond and deteriorate the bond. However, on the other hand, there are also strict demands for improvements in hPIl characteristics and x/f noise.
このため、従来のバイポーラトランジスタでは、上記の
相反する要求を同時に満たすことを断念シ、エミ、り・
コンタクト用開孔をエミ、り・ペース接合近傍まで広げ
て、ｈＦＩ改善を計る代りに、エミ、り・ベース接合を
深くして、アルミ原子がエミ、り・ベース接合まで溶融
拡散しないような方法を採用していた。この方法では、
上述した高周波特性の改善や素子サイズの縮少化、省エ
ネルギーに対する要求を満たすことは困難である。For this reason, conventional bipolar transistors have had to give up on satisfying the above contradictory requirements at the same time.
Instead of widening the contact hole to the vicinity of the emitter, rim, and paste junction to improve hFI, there is a method of deepening the emitter, rim, and base junction to prevent aluminum atoms from melting and diffusing to the emitter, rim, and base junction. was adopted. in this way,
It is difficult to satisfy the above-mentioned demands for improving high frequency characteristics, reducing element size, and saving energy.
本発明は、上記のような欠点を改善して、エミ、！・ベ
ース接合が浅く高周波特性の優れたトランジスタであっ
てもＡ／等アルンアロイ工程でＨ＋イオンを発生させる
材料でエミッタ・ペース接合部上の酸化Ｍｋネオ−−ラ
ツプすることにより、表面単位密度を減少させて％ ｈ
ＰＩや１／ｆ 雑音特性を改善した半導体装置を得る
ものである。The present invention improves the above-mentioned drawbacks and improves Emi!・Even if the base junction is shallow and the transistor has excellent high frequency characteristics, the surface unit density can be reduced by wrapping Mk neo-oxidation on the emitter paste junction with a material that generates H+ ions in the A/equal Aluminum alloy process. Let me%h
A semiconductor device with improved PI and 1/f noise characteristics is obtained.
本発明によれば、エミ、り領域と接触する電極面積が少
ない為、ＡＩ！がエミ、り・ペース接合近辺まで拡散し
て、接合の結晶性を劣化させることはなく、又エミ、り
・ベース接合を電極金属で酸化膜とともに被覆している
のでｓ ’ＩＰ］Ｉや１／ｆ雑音特性がすぐれたトラ
ンジスタ全実現することができる。又、エミッタ・ベー
ス接合の深さは十分浅くすることが可能なので周波数特
性もすぐれ、省エネルギー化に対応したトランジスタを
実現することが可能である。According to the present invention, since the electrode area in contact with the emitter region is small, AI! does not diffuse into the vicinity of the emitter, rim, and paste junctions and deteriorate the crystallinity of the junction, and since the emitter, rim, and base junctions are covered with the electrode metal along with the oxide film, s'IP]I and 1 /f All transistors with excellent noise characteristics can be realized. Further, since the depth of the emitter-base junction can be made sufficiently shallow, frequency characteristics are also excellent, and it is possible to realize a transistor that is compatible with energy saving.
以下、本発明を図面を参照してより詳細に説明する。Hereinafter, the present invention will be explained in more detail with reference to the drawings.
第１図、第２図は、ｈ■特性や１／ｆ雑音特性が改善さ
れた従来のバイポーラＩＣにかんばんに使用される縦型
ＰＮＰ）ランジスタ（以下Ｖ−ＰＮＰと書く）のエミッ
タ近辺の平面構造（第１図）及びＶ−ＰＮＰの構造断面
図（第２図）を示す。Figures 1 and 2 show the plane near the emitter of a vertical PNP transistor (hereinafter referred to as V-PNP), which is commonly used in conventional bipolar ICs with improved h characteristics and 1/f noise characteristics. The structure (FIG. 1) and the cross-sectional view of the V-PNP structure (FIG. 2) are shown.
このＶ−ＰＮＰは特にｖ、、のオフセットが少いことが
要求される差動形接続の場合に効果的に使われている。This V-PNP is particularly effectively used in the case of a differential connection where a small offset of v, , is required.
第１図、第２図で１・Ｅ、 ２・ＥＨエミ、り拡散領域
、ＩＥ−Ｃ，２Ｂ−Ｃ＃ｉエミッタ部コンタクト用開孔
で表面酸化膜に開けられたものである。１・Ｅ−Ｂ、２
・Ｅ−Ｂ ｔ′ｉエミ、り・ペース接合部を示す。又１
・ＡＬ、２・ＡＬはエミツタコンタクト用開孔全通して
エミ、り領域１・Ｅ、 ２・Ｅと接触するＡＪ引き出し
電極を示している。In FIGS. 1 and 2, 1.E, 2.EH emitter, ri diffusion region, IE-C, 2B-C#i emitter contact openings are made in the surface oxide film. 1・E-B, 2
・E-B t′i EMI, RI・Pace joint is shown. Again 1
・AL, 2・AL indicate AJ extraction electrodes that pass through the entire opening for emitter contact and contact the emitter regions 1・E, 2・E.
又、第２図に示すＶ−ＰＮＰ はＰ型基板２・１にＮ型
埋込層２・３とＰ型埋入層２・２″を形成し、表面にＮ
型エピタキシャル層２・４を形成し、このＮ型エピタキ
シャル層２・４にせり上ってきた各埋入領域２・２と接
触するようにＰ型領域２・５を拡散形成し、Ｐ型領域２
・５で囲まれたエピタキシャル層２・４にＰ型エミッタ
領域２・Ｅとベース電極取り出し用Ｎ＋領領域・６を形
成したものである。In addition, the V-PNP shown in Fig. 2 has N-type buried layers 2, 3 and P-type buried layers 2, 2'' formed on a P-type substrate 2, 1, and N-type buried layers 2, 2'' on the surface.
type epitaxial layers 2 and 4 are formed, and P type regions 2 and 5 are diffused and formed so as to be in contact with the buried regions 2 and 2 that have risen up on the N type epitaxial layers 2 and 4. 2
A P-type emitter region 2.E and an N+ region 6 for taking out the base electrode are formed in the epitaxial layers 2 and 4 surrounded by 5.
第１図、第２図かられかるように％ ｖＢＨオフセ、
トがきびしいＶ−ＰＮＰに於いては、エミ、り領域１・
Ｅ、２・ＥからのＡＩ！引き出し電極１・ＡＬ及び２・
ＡＬｔエミ、り部コンタクト用開孔１・Ｅ−Ｃ，２・Ｅ
−Ｃ全面でエミ、り領域１・Ｅ、２・Ｅに接触さすとと
もに、エミッタ・ベース接合部の外側までオーバーラツ
プして配置する方法が広く行なわれている。一方、Ｖ−
ＰＮＰのエミッタ領域１・Ｅ、２・ＥＦｉ素子面積縮少
化及び高周波化に対する要求から浅くなる傾向にある。As shown in Figures 1 and 2, % vBH offset,
In V-PNP with severe
AI from E, 2・E! Extracting electrodes 1・AL and 2・
ALt emitter, rim contact opening 1・E-C, 2・E
A widely used method is to contact the emitters 1, E, 2, and E over the entire surface of the emitter and overlap them to the outside of the emitter-base junction. On the other hand, V-
PNP emitter regions 1, E, 2, and EFi tend to become shallower due to demands for smaller area and higher frequency.
これは、次のような理由による。This is due to the following reasons.
バイポーラＩＣにおけるトランジスタの素子面積を解析
すると、ベース−絶縁層間、コレクター絶縁層間のしめ
る割合が大きく、これがＭＯ８ＩＣと比較してバイポー
ラＩＣのチップサイズが小さくできない大きな理由であ
る。従って、トランジスタを縮少化するにはエピタキシ
ャル厚さヲ薄くして、絶縁領域の横広がりを小さくする
ことが重要である。Analysis of the element area of a transistor in a bipolar IC reveals that the area between the base and the insulating layer and the area between the collector insulating layer is large, and this is a major reason why the chip size of the bipolar IC cannot be made smaller than that of the MO8 IC. Therefore, in order to downsize the transistor, it is important to reduce the epitaxial thickness and reduce the lateral extent of the insulating region.
この九め、Ｖ−ＰＮＰのエミ、りをＮＰＮトランジスタ
のベースと別に浅く拡散してエピタキシャル厚さを薄く
する方法が採用されている。このような浅いエミ、り、
ペース接合を有するＶ−ＰＮＰに第１図、第２図に示す
ようなＡ！電極を形成するとｌｌがエミ、り・ベース接
合まで拡散してエミッタ、ペース接合を劣化させたり、
さらに進行するとＡＪ原子が工′□ミ□、タ領域１・Ｅ
、２・Ｅを通りこして、ベース領域まで拡散する云わゆ
るアロイスパイクと呼ばれる事故がしげしげ発生する。Ninth, a method has been adopted in which the V-PNP emitter is shallowly diffused separately from the base of the NPN transistor to reduce the epitaxial thickness. Such shallow energy,
A! V-PNP with pace junction as shown in FIGS. 1 and 2! When electrodes are formed, ll diffuses to the emitter, ri and base junctions and deteriorates the emitter and paste junctions.
As it progresses further, the AJ atoms are
, 2.E and spreads to the base region, which frequently causes an accident called an alloy spike.
次に、本発明による第１の実施例を示すエミッタ近辺の
平面図を第３図に、Ｖ−ＰＮＰに適用した場合の構造断
面図を第４図に示す。Next, FIG. 3 is a plan view of the vicinity of an emitter showing a first embodiment of the present invention, and FIG. 4 is a structural cross-sectional view when applied to a V-PNP.
まず、第４図を参照すると、Ｖ−ＰＮＰはＰ型シリコン
基板４・１にＮ型埋入層４・３とＰ型埋込層４・２，４
・２′とを形成した後、Ｎ型エピタキシャル層４・４が
成長せしめられる。この気相成長時に各埋込層はエピタ
キシャル層４・４にせり上り、第４図図示のように々る
。次にＰ型不純物を高濃度に拡散して、Ｐ型絶縁分離領
域４・５をＰ型埋込層４・２に到達せしめエピタキシャ
ル＠４・４を複数の島領域に分離するとともに、Ｐ型壁
領域４・５”ｔＰ型埋入層４・２′に到達せしめてエピ
タキシャル層４・４の一部がＰ型壁領域４・５′とＰ型
埋込層４・２′とで囲むようにする。次に、このＰ型壁
領域４・５′とＰ型埋込層４・２′とで囲まれたエピタ
キシャル層４・４の部分にＰ型エミッタ領域４・ＥとＮ
型ベース、コンタクト領域４・６とを形成する。First, referring to FIG. 4, V-PNP is a P-type silicon substrate 4-1, an N-type buried layer 4-3 and a P-type buried layer 4-2, 4.
After forming 2', an N-type epitaxial layer 4 is grown. During this vapor phase growth, each buried layer rises up onto the epitaxial layers 4, 4, as shown in FIG. Next, P-type impurities are diffused at a high concentration to make the P-type insulating isolation regions 4 and 5 reach the P-type buried layers 4 and 2, separating the epitaxial layers 4 and 4 into a plurality of island regions. The wall regions 4 and 5"t reach the P-type buried layers 4 and 2' so that a part of the epitaxial layers 4 and 4 are surrounded by the P-type wall regions 4 and 5' and the P-type buried layers 4 and 2'. Next, P-type emitter regions 4.E and N
A mold base and contact regions 4 and 6 are formed.
次いで、表面酸化膜にそれぞれベース、エミ。Next, base and emitter are applied to the surface oxide film, respectively.
り、エレクタ電極導出のためのコンタクト用開孔を設け
、全面ＡＡ！、 ％着後、ホトエツチングによる選択エ
ツチングで電極配線が形成されるが、特にエミ、り部分
のこの電極構造が第３図に示されている。 ・
これら、第３図、第４図で、３Ｅ、４ＥＶｉＶ−ＰＮＰ
のエミ、り領域であり、その深さは約Ｉ島である。３・
Ｅ−Ｃ及び４・Ｅ−Ｃは、エミッタコンタクト用開孔を
示し、開孔面積は４μ×４Ａの大きさである。エミッタ
コンタクト用開孔３・Ｅ−Ｃ，４・Ｅ、Ｃ内からその２
５μ外側の酸化膜上にまで第１０＆ｊ電極３ Ａ Ｌ（
ａ）、 ４ Ａ Ｌ（ａｌが配置されており、又エミッ
タ・ベース接合部上を含みその近辺にもＡｊ電極３ＡＬ
伽１．４ Ａ Ｌ（ｂ）＠化膜上に形成されており、こ
れらは５〜′１．５μの巾をもつｆｉｔ配線Ａで互いに
接続されている。A contact hole is provided for leading out the erector electrode, and the entire surface is AA! After deposition, electrode wiring is formed by selective etching using photoetching, and this electrode structure, especially at the emitter and ridge portions, is shown in FIG.・ In these figures 3 and 4, 3E, 4EViV-PNP
It is a region with a depth of approximately I island. 3.
E-C and 4·E-C indicate openings for emitter contacts, and the opening area is 4μ×4A. Emitter contact opening 3・E-C, 4・E, Part 2 from inside C
The 10th &j electrode 3 A L (
a), 4 A L (Al is arranged, and Aj electrode 3 AL is also arranged in the vicinity including above the emitter-base junction.
1.4 A L(b)@ is formed on the oxide film, and these are connected to each other by a fit wiring A having a width of 5 to 1.5 μm.
このように、工２．タ領域３・Ｅ、４・Ｅと接触する４
ｊ電極３ Ａ Ｌ（ａ）、 ４ Ａ Ｌ（ａ）の面積は
少くとも、Ａｊ電極３ Ａ Ｌ（ｂｌ、 ４ Ａ Ｌ（
ｂ）のため１／ｆ維音は少く、シかもコンタクト用開孔
３・Ｅ、Ｃ。In this way, work 2. 4 in contact with data area 3・E, 4・E
The areas of the Aj electrodes 3 A L(a) and 4 A L(a) are at least as large as the Aj electrodes 3 A L(bl, 4 A L(
Because of b), the 1/f fiber sound is small and contact openings 3, E and C may be used.
全通してＡｊ電極３ Ａ Ｌ（ａ）、 ４ Ａ Ｌ（ａ
ｌ中に拡散していくシリコンの量はＡ！電極３ ｋ Ｔ
、（ａｔ、 Ｊ Ａ Ｌ（ａ）が小さいので、従来の
ＡＪ電極の配置法に比較すると大巾に少ない、又、Ａｌ
配線Ａの巾も狭すのでＡｊ電極３ Ａ Ｌｆａｌ、 ４
Ａ Ｌ（ａｌ中に拡散しに、シリコンがエミ、り・ベ
ース接合上を含む近辺に配置された大量のＡ／電極３
ＡＬ（ｂｌ、 Ｊ ＡＬ中）へは殆んど拡散していかな
い。このため、エミ、り・領域３・Ｅ、４・Ｅ中のシリ
コン結晶へ拡散して行＜ｈｐＯ量も少ないので、エミッ
タ・ベース接合までＡｊが拡散して接合の結晶性を劣化
させることもない。従って高周波特性が優れ％ ｈＦ
Ｆｉが大きく雑音も少いトランジスタを得ることができ
る。Aj electrode 3 A L (a), 4 A L (a
The amount of silicon that diffuses into l is A! Electrode 3kT
, (at, J A L(a) is small, so compared to the conventional AJ electrode arrangement method, the amount of Al
Since the width of wiring A is also narrowed, Aj electrode 3 A Lfal, 4
A L (a large amount of A/electrode 3 placed near the emitter, including on the base junction) where silicon diffuses into the Al.
It hardly diffuses into the AL (bl, J AL). Therefore, since the amount of Aj is small, Aj diffuses into the silicon crystal in the emitter-base junction and deteriorates the crystallinity of the junction. do not have. Therefore, the high frequency characteristics are excellent%hF
A transistor with high Fi and low noise can be obtained.
第５図は本発明の他の実施例としての電極部分を示した
もので、Ａ部分、即ちエミッタ領域５・Ｅと接触するＡ
ｌ引き出し電極５ＡＬ（ａｔと、エミッタ・ベース接合
上の酸化膜の上に配置されているＡＩＭ極５ＡＬ（ｂｌ
とを配線するＡＪ配線は、第３図、第４図の実施例の場
合よりも長（へので、ＡＪ電極５ＡＬ（ａｌに拡散した
シリコンは、外側のＡｌ中へ拡散してｂくの全防止する
効果に一層著しい。FIG. 5 shows an electrode part as another embodiment of the present invention.
l extraction electrode 5AL (at) and AIM electrode 5AL (bl) placed on the oxide film on the emitter-base junction.
Since the AJ wiring that connects the AJ electrodes 5AL and 5AL is longer than that in the embodiments shown in FIGS. The prevention effect is even more remarkable.
Ｊメ上、述べた実施例では従来のプロセス全変更するこ
となしに、マスクバタ・・ン上容易に実現することが可
能である。即ち、従来は工２．タコンタクト用開孔のＡ
、 ｌ引き出し電極は、ボンタクト用開孔部からＡＪ配
線取り出しと、アルミアロイ工程で酸化膜との酸化反応
に、Ｖって、表面準位を減少する役割を両方兼用してい
念が、本発明にこ７′１７ら透分離した為に素子面積を
減少することが出来、１／ｆ雑音特性や”Ｆｌｉ特性高
周波特性を改善することができる。The above-described embodiment can be easily implemented on the mask pattern without completely changing the conventional process. In other words, in the past, work 2. A of the hole for contact
, l The extraction electrode has the dual role of taking out the AJ wiring from the bond opening and reducing the surface level of V in the oxidation reaction with the oxide film in the aluminum alloy process. Since the elements 7' and 17 are transparently separated, the element area can be reduced, and the 1/f noise characteristics and "Fli characteristics" high frequency characteristics can be improved.
第６図は、本発明の更に他の実施例を示す平面図であり
、エミ、り領域６Ｅ、！：接触するＡｊ電極６Ａ、Ｔ′
、（ａ）とエミ、り・ベース接合上を含むその近辺の液
化膜上に形成したＡＩ電極６ＡＬ（ｂｌと全接続する配
線６・ｐｏｌｙはポリシリコンにリン又はボロン、Ａｊ
ｆＬど全拡散して形成した低抵抗半導体材料であり、Ａ
７［極６ＡＴ、（ａｌと配線６−ｐｏｌｙの境界ではシ
リコシの濃度は配＠６・ｐｏｌｙ 部分の方が高いの
でコンタクト用開孔６・Ｅ、Ｃ中からｋｌ電極６・ＡＬ
（ａｌへ拡散したシリコンが外側に配置されているＩｔ
電極６・ＡＬ（ｂ）へ広がって行くことはない、従って
、上記の効果は一層顕微である。このとき配線６・ｐｏ
ｌｙの長さは短くとも何ら差しつかえない。FIG. 6 is a plan view showing still another embodiment of the present invention, in which the emitter areas 6E, ! : Contacting Aj electrode 6A, T'
, (a) and the AI electrode 6AL formed on the liquefied film in the vicinity including the top of the emitter/base junction (the wiring 6/poly, which is fully connected to bl, is made of polysilicon with phosphorus or boron, Aj
It is a low-resistance semiconductor material formed by fully diffusing fL, and A
7 [Pole 6AT, (At the boundary between Al and wiring 6-poly, the concentration of silicon is higher in the wiring @6-poly part, so kl electrode 6-AL is removed from contact openings 6-E and C.
(It where silicon diffused into al is placed on the outside)
It does not spread to the electrode 6・AL(b), so the above effect is even more microscopic. At this time, wiring 6・po
There is no problem even if the length of ly is short.
以上、述べたように、本発明によるバイポーラトランジ
スタはエミ、り・ペース接合が浅い場合にきわめて有効
であり、この為高周波特性がすぐれ、又素子サイズの低
域にも効果が大きい。父、エミッタ・ベース接合近辺の
酸化膜上をＡｊなど熱処理工程で（ｌ イオンを発生す
る材料で被覆することにより、表面単位密度を減少させ
、ｈア。As described above, the bipolar transistor according to the present invention is extremely effective in cases where the emitter, paste, and paste junctions are shallow, and therefore has excellent high frequency characteristics and is also highly effective in the low range of the device size. The surface unit density is reduced by coating the oxide film near the emitter-base junction with a material that generates ions in a heat treatment process such as Aj.
特性や１／ｆ雑音特性がすぐれ、差動形接続のトランジ
スタに用いると■□オフセ、トが十分率さいすぐれ几半
導体装置を実現できる。It has excellent characteristics and 1/f noise characteristics, and when used in differentially connected transistors, it is possible to realize an excellent semiconductor device with sufficient offset and f.
本発明は主としてバイポーラＩＣのＶ−ＰＮＰのエミッ
タ、コンタクトのＡｌ引き出しについてのみ述べたが、
浅い接合を有し、かつ表面単位密度を下げる必要のある
デバイスには、等しく応用できることは言うまでも々い
。Although the present invention has mainly been described only regarding the Al extraction of the V-PNP emitter and contact of a bipolar IC,
Needless to say, the present invention is equally applicable to devices that have shallow junctions and require a reduction in surface unit density.
第１図は従来のバイポーラＩＣのＶ−ＰＮＰエミッタ電
極部を示す平面図である。
ＩＥ・・・・・・エミ、り（Ｐ 層）
Ｉ Ｅ・Ｃ・・・・・・エミ、り、コンタクト１ Ｅ
−Ｂ・・・・・エミ、タ、ペース接合ＩＡ−Ｌ・・・・
エミッタコンタクトのｈｔ引き出し電極
第２図は従来のＶ−ＰＮＰ’に示す構造断面図である。
２・１・・・・・・Ｐ型基板
２・２・・・・・・埋込みＰ 層
２・３・・・・・・埋込みＮ 層
２・４・・・・・・Ｎ型エピタキシャル領埴２・５・・
・・・・（縁Ｐ＋領域
２・６・・・・・・ベースＮ 層
２・Ｅ・・・・・・エミ、り（Ｐ 層）２・Ｅ−Ｃ・・
・・・エミ、り・コンタクト２・Ｅ、Ｂ・・・・・エミ
ッタ・ペース接合２・Ａ−Ｌ・・・・・・エミッタ、コ
ンタクトのＡｊ引き出し電極
第３図は本発明のｑ）＋−の実施例によるＶ、ＰＮＰの
エミ、り′「ｕ極部五：′斤す平■ｉ図である。
３・Ｅ ・・・・・・・・・エミッタＣＰ 悄）３・
Ｅ−Ｃ・・・・工ｉ、夕、コンタクト３・Ｅ、Ｂ・・・
・・・エミッタ、ベース接合３・Ａ Ｌ （ａｌ・・・
・・・エミ、り、コンタクト近辺のＡ７？電極
３・ＡＬ（ｂ）・・・・・工き、タウベ接合後合上の酸
化膜上に配置されているＡ７電極
Ａ・・・・・・・・・・・ ・・・３ＡＬ（ａｌと３Ａ
Ｌ（ｔｅ＋とを配線している巾の狭いｌ’ｌ電極
第４図は本発明の第一の実施例によるＶ −ＰＮＰを示
すＨｆ造造血面図ある。
４・１−° ・・・・・・Ｐ型基板
４・２・ ・・・・・埋込みＰ 層
４・３・・ ・・・・・埋込みＮ 層
４・４・・・・・・・・・・・Ｎ型エピタキシャル領域
４・５・・・・・・・・・・絶縁Ｐ 領域４・６・・・
・・・・・・・・・ベースＮ 層４・Ｅ・・・・・・・
・・・・・エミッタ（Ｐ”１ｉ）１・Ｅ−Ｃ・・・・・
・・・・ニオツタ、コンタクト４・Ｅ−Ｂ・・・・・・
・・エミッタ、ベース接合１・ＡＬ（ａ）・・・・・エ
ミッタ、コンタクト近辺のＡｃｔ極
４・Ａ Ｉ、 （ｂｌ・・・・・・・・・エミッタ・ベ
ース接合上の酸化膜に配置されているＡ／電
極
第５図は本発明の他の実施例によるＶ−ＰＮＰエミッタ
電極部♀示す平面図である。
５・Ｅ・・・・・・・・・・・・・・エミッタＣＰ
層）５・Ｅ、Ｃ・・・・・・・エミ、り、コンタクト５
・Ｅ、Ｉ３・・・・・・・エミ、タ、ベース接合５・Ａ
Ｌ（ａｌｌ、−・１．・エミ、り・コンタクト近辺の
ＡＪ電極５・ＡＬ（ｂｌ・・・・・エミ、り、ベース接
合上の酸化膜上に配置されているｋｌ
ｔ極
Ａ・・・・・・・・・−・・・・・・・・・・３ＡＬ（
ａ）と３ＡＬ（ｂ）とを配線している巾の狭いｈｔ電極
第６図は本発明の更に他の実施例によるＶ−ＰＮＰの電
量部を示す千面融である。
６・Ｅ・・・・・・・・・・・・エミッタ（Ｐ ７１
）６・Ｅ−Ｃ・・・・・・エミフタ、コンタクト６・Ｆ
−Ｂ・・・・・エミッタ、ベース接合６・ ＡＬ（ａｔ
・・・・・エミ、り、コンタクト近辺のＡ Ｉ ’！、
極６・ＡＬ（ｂト・・・・・エミッタ、ベース接合上の
酸化膜上に配置されているＡｊ電極
６・ｐｏｌｙ・・・・・・ポリシリコンにボロン、リン
。
Ｎ〕などを拡散して形成し念低
抵抗領域
代理人 弁理士 内 原 音
１、Ｅ
２、Ｅ、８ ２．Ｅ、Ｃ２，６
第２図
拾３図
第４図
５ＡＬ（ａ−）
ど・、Ｅ 乙ＡＬ（必）
どＡＬ（ｂ’）
第６図
２９２−FIG. 1 is a plan view showing a V-PNP emitter electrode portion of a conventional bipolar IC. IE・・・Emi, Ri (P layer) I E・C・・・Emi, Ri, Contact 1 E
-B...Emi, Ta, pace joint IA-L...
ht extraction electrode of the emitter contact FIG. 2 is a structural sectional view of a conventional V-PNP'. 2.1...P-type substrate 2.2...Buried P layer 2.3...Buried N layer 2.4...N-type epitaxial layer 2.5...
...(Edge P+ area 2, 6...Base N layer 2, E...Emi, Ri (P layer) 2, E-C...
...Emitter, contact 2, E, B... emitter, paste junction 2, A-L... emitter, contact Aj extraction electrode in Figure 3 is q)+ of the present invention. This is a diagram of the emitter of V and PNP according to the embodiment of 3.
E-C...Eng, evening, contact 3, E, B...
...Emitter, base junction 3・A L (al...
...Emi, Ri, A7 near Contact? Electrode 3・AL(b)...A7 electrode A......3AL (al and 3A
Figure 4 is a view of the Hf hematopoietic surface showing the V-PNP according to the first embodiment of the present invention. ...P-type substrate 4.2...Buried P layer 4.3...Buried N layer 4.4...N-type epitaxial region 4. 5... Insulation P area 4, 6...
・・・・・・・・・Base N Layer 4・E・・・・・・・
...Emitter (P"1i) 1・E-C...
...Niotsuta, Contact 4 E-B...
・・Emitter, base junction 1・AL(a)・・・Act pole 4・A I, (bl・・・・・・・・・Place on the oxide film on the emitter/base junction) near the emitter and contact FIG. 5 is a plan view showing the V-PNP emitter electrode part ♀ according to another embodiment of the present invention. 5.E Emitter CP
layer) 5・E, C...Emi, Ri, contact 5
・E, I3...Emi, T, base connection 5・A
AJ electrode 5 near the L(all, -1., emitter, ri, contact), AL(bl...Emi, ri, klt electrode placed on the oxide film on the base junction) A...・・・・・・・・・−・・・・・・・・・・・・3AL(
The narrow ht electrode wiring a) and 3AL(b) in FIG. 6 is a multifaceted fusion diagram showing the capacitance portion of a V-PNP according to still another embodiment of the present invention. 6.E・・・・・・・・・Emitter (P 71
)6・E-C・・・Emi-lid, contact 6・F
-B... Emitter, base junction 6 AL (at
...Emi, Ri, AI' near the contact! ,
Diffusion of boron, phosphorus, N, etc. into the electrode 6, AL (b... placed on the oxide film on the emitter and base junction) electrode 6, poly...... polysilicon. 1, E 2, E, 8 2. E, C2, 6 Figure 2, 13, Figure 4, 5 AL (a-) Do, E Otsu AL ( Must) Do AL (b') Figure 6 292-
Claims (2)
面上の絶縁膜上の少なくともエミ、り・ペース接合上を
おおう第一の電極物質と、エミッタ直接接触する第二の
電極物質とを有し、前記第一の電極物質と前記第２のＷ
接物質とけ、電気的に相互に配線により接続されており
、かつ絶縁膜上の前記第一および第二の電極物質は少な
くとも一部で酸化膜、チ、化膜、モールド樹脂など非伝
導物質により互いに分離されていることを特徴とする半
導体装置。(1) A first electrode material covering at least the emitter, paste and paste junction on the insulating film on the main surface of the semiconductor chip forming the emitter-base junction tube, and a second electrode material in direct contact with the emitter. , the first electrode material and the second W
The first and second electrode materials on the insulating film are at least partially formed of a non-conductive material such as an oxide film, a chemical film, a molding resin, etc. A semiconductor device characterized by being separated from each other.
する配線は、不純物を含有する半導体材料で形成されて
いることを特徴とする特許請求の範囲第１項記載の半導
体装置。(2) The semiconductor device according to claim 1, wherein the wiring interconnecting the first and second @contact materials is formed of a semiconductor material containing impurities.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113891A JPS5815268A (en) | 1981-07-21 | 1981-07-21 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP56113891A JPS5815268A (en) | 1981-07-21 | 1981-07-21 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5815268A true JPS5815268A (en) | 1983-01-28 |
| JPH0120550B2 JPH0120550B2 (en) | 1989-04-17 |
Family
ID=14623721
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP56113891A Granted JPS5815268A (en) | 1981-07-21 | 1981-07-21 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5815268A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5974672A (en) * | 1982-10-20 | 1984-04-27 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS606366A (en) * | 1983-06-20 | 1985-01-14 | トキコ株式会社 | Method of controlling screw clamping machine |
| JPH0570221U (en) * | 1991-02-16 | 1993-09-24 | 高北農機株式会社 | Manure spreader |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5146880A (en) * | 1974-10-18 | 1976-04-21 | Matsushita Electronics Corp | TORANJISUTA |
-
1981
- 1981-07-21 JP JP56113891A patent/JPS5815268A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5146880A (en) * | 1974-10-18 | 1976-04-21 | Matsushita Electronics Corp | TORANJISUTA |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5974672A (en) * | 1982-10-20 | 1984-04-27 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
| JPS606366A (en) * | 1983-06-20 | 1985-01-14 | トキコ株式会社 | Method of controlling screw clamping machine |
| JPH0570221U (en) * | 1991-02-16 | 1993-09-24 | 高北農機株式会社 | Manure spreader |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0120550B2 (en) | 1989-04-17 |
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