JPS5974672A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS5974672A
JPS5974672A JP18580682A JP18580682A JPS5974672A JP S5974672 A JPS5974672 A JP S5974672A JP 18580682 A JP18580682 A JP 18580682A JP 18580682 A JP18580682 A JP 18580682A JP S5974672 A JPS5974672 A JP S5974672A
Authority
JP
Japan
Prior art keywords
layer
base
integrated circuit
semiconductor integrated
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18580682A
Other languages
Japanese (ja)
Inventor
Yusuke Yamada
山田　友右
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP18580682A priority Critical patent/JPS5974672A/en
Publication of JPS5974672A publication Critical patent/JPS5974672A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Bipolar Transistors (AREA)

Abstract

PURPOSE:To improve the noise characteristic by forming an n<+> diffused layer of a high concentration in a base layer and then connecting it to a base contact, in a vertical type p-n-p transistor. CONSTITUTION:In the base layer 3 of the vertical type p-n-p transistor, the n<+> diffused layer 12 of a high concentration is formed with the same polarity as the layer 3 and more deeply than an emitter layer 4, and the layer 12 is connected to the base contact 15. Thereby the resistance value of a resistor 8 in the layer 3 immediately under the contact 5 can be reduced. Thus, base expansion resistance becomes small, and then the noise characteristic can be improved. Besides in this case, a base width and the concentration and the thickness of the base layer 3 are sufficient as left conventional.

Description

【発明の詳細な説明】 この発明は半導体集積回路に使用される縦形ＰＮＰ）ラ
ンリスタのベース拡がシ抵抗を下げ、雑音特性を向上す
ることができる半導体集積回路装置に関するものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device in which the base expansion of a vertical PNP run lister used in a semiconductor integrated circuit can lower resistance and improve noise characteristics.

第１図は従来の半導体集積回路装置を示す概略断面斜視
図である。同図において、（１）はコレクタ領域として
動作するＰ　基板、（２）はＰ分離層、（３）ハｎ−エ
ピタキシャル層からなる縦形ＰＮＰ）ランリスタのベー
ス層、（４）は通常のベース拡散で形成されるＰ層から
なるエミツタ層、（５）は通常のエミッタ拡散で形成さ
れるｎ　層からなるベースコレクタ、（６）　、　ｆｆ
）および（８）は抵抗値がそれぞれｒ　！　、　ｒ　２
およびｒ３　　の抵抗、（９）はコレクタ電極、（１０
）はエミッタ電極’１　　（１１）はベース電極である
。FIG. 1 is a schematic cross-sectional perspective view showing a conventional semiconductor integrated circuit device. In the figure, (1) is a P substrate that acts as a collector region, (2) is a P isolation layer, (3) is a base layer of a vertical PNP (run lister) consisting of a Han-epitaxial layer, and (4) is a normal base diffusion. (5) is an emitter layer made of a P layer formed by normal emitter diffusion, (6) is a base collector made of an n layer formed by normal emitter diffusion, and ff
) and (8) each have a resistance value r! , r2
and the resistance of r3, (9) is the collector electrode, (10
) is the emitter electrode '1 (11) is the base electrode.

なお、縦形ＰＮＰ　）ランリスタのペース拡がシ抵抗ｒ
　５６／は抵抗（６）　、　（７）および（８）の和、
すなわちｒｂｂ’＝（’　１　＋ｒ　２　＋ｒ　３　）
である。また、抵抗（６）はエミッタ直下のｎ一層の抵
抗であシ、　抵抗（１）はエミッタ領域からベース領域
までの横方向の抵抗であり、抵抗（８）はベースコンタ
クト真下の１層の抵抗である。In addition, for vertical PNP) the pace expansion of the run lister is difficult.
56/ is the sum of resistances (6), (7) and (8),
That is, rbb' = (' 1 + r 2 + r 3 )
It is. In addition, the resistor (6) is a single-layer resistor directly under the emitter, the resistor (1) is a lateral resistance from the emitter region to the base region, and the resistor (8) is a single-layer resistor directly under the base contact. It is.

次に、上記構成による縦形ＰＮＰ　）ランリスタの雑音
特性について説明する。まず、トランジスタに外付けさ
れる信号源抵抗を０とすると、トランジスタから発生す
る雑音電圧ｅｎは一般に次の式で近似される。Next, the noise characteristics of the vertical PNP run lister having the above configuration will be explained. First, assuming that the signal source resistance externally connected to the transistor is 0, the noise voltage en generated from the transistor is generally approximated by the following equation.

ここで、′ｒｂｂｌはベース拡がシ抵抗、ｒｅは工ツタ
接合抵抗、Δｆは周波数帯域、Ｋはボルツマン定数、Ｔ
は絶対温度である。Here, 'rbbl is the base expansion resistance, re is the engineering junction resistance, Δf is the frequency band, K is Boltzmann's constant, and T
is the absolute temperature.

このように、トランジスタの雑音電圧はベース拡がシ抵
抗ｒｂｂ’とエミッタ接合抵抗ｒｅとの抵抗成分で支配
されておｐ１小さい方が雑音特性が良いことがわかる。In this way, it can be seen that the noise voltage of the transistor is dominated by the resistance components of the base expansion resistance rbb' and the emitter junction resistance re, and the smaller p1 is, the better the noise characteristics are.

しかしながら、従来の半導体集積回路装置ではそのエミ
ッタ接合抵抗ｒ。がエミッタ電流で決定６ （ｒ、ζ−ｍＱ）されるため、すべてのトランジスＥ りにおいて同じ条件になシ、雑音特性の差はベース拡が
り抵抗ｒｂｂ’で支配される。このベース拡がシ抵抗ｒ
ｂｂ’は前記したように１抵抗（６）　、　（７）およ
び（８）の抵抗値の和（ｒｂｂ’　＝ｒ１　＋　ｒ　２
　＋　ｒ　３　）で示されるため、（５）抵抗（６）の
抵抗値ｒ、を小さくするためにはベース（３）の濃度を
高くするか、あるいはベース（３）の厚みを薄くする方
法があるが、耐圧が低くなるため、制限される。また、
（Ｂ）抵抗（７）の抵抗値ｒ２を小さくするためには同
様にベース（３）の濃度を高くするか、あるいはエミツ
タ層（４）、！：ベースコンタクト（５）の距離を短か
くする方法があるが、同様に耐圧で制限されるなどの欠
点があった。However, in the conventional semiconductor integrated circuit device, its emitter junction resistance r. Since E is determined by the emitter current 6 (r, ζ - mQ), all transistors E must be under the same conditions, and the difference in noise characteristics is dominated by the base spread resistance rbb'. This base expansion resistance r
As mentioned above, bb' is the sum of the resistance values of one resistor (6), (7), and (8) (rbb' = r1 + r2
+ r 3 ). Therefore, in order to reduce the resistance value r of (5) and resistor (6), there is a method of increasing the concentration of the base (3) or decreasing the thickness of the base (3). However, it is limited due to the low withstand voltage. Also,
(B) In order to reduce the resistance value r2 of the resistor (7), the concentration of the base (3) must be similarly increased, or the emitter layer (4),! : There is a method of shortening the distance of the base contact (5), but it also has drawbacks such as being limited by the withstand voltage.

したがって、この発明の目的は縦形ＰＮＰトランジスタ
のベース拡がシ抵抗ｒｂｂ’を小さくして、雑音特性を
向上することができる半導体集積回路装置を提供するも
のである。Therefore, an object of the present invention is to provide a semiconductor integrated circuit device in which the base expansion resistance rbb' of a vertical PNP transistor can be reduced to improve noise characteristics.

このような目的を達成するため、この発明は縦形ＰＮＰ
）ランリスタのベース層に、エミツタ層よシ深い、前記
ベース層と同極性の高濃度拡散層を形成し、この高濃度
拡散層をベースコンタクトに接続するものであシ、以下
実施例を用いて詳細に説明する。In order to achieve such an object, the present invention utilizes a vertical PNP.
) A highly doped diffusion layer of the same polarity as the base layer, which is deeper than the emitter layer, is formed in the base layer of the run lister, and this highly doped diffusion layer is connected to the base contact. Explain in detail.

第２図はこの発明に係る半導体集積回路装置の一実施例
を示す概略断面斜視図である。同図において、（１２）
はベース層（３）と同一極性で、かつエミツタ層（４）
より深く前記ベース層（３）に形成すると共に前記ベー
スコンタクト（５）に接続する高濃度ｎ＋拡散層である
。FIG. 2 is a schematic cross-sectional perspective view showing an embodiment of the semiconductor integrated circuit device according to the present invention. In the same figure, (12)
has the same polarity as the base layer (3), and the emitter layer (4)
This is a high concentration n+ diffusion layer formed deeper in the base layer (3) and connected to the base contact (5).

次に、上記構成による縦形ＰＮＰ　）ランリスタの雑音
特性について説明すると、高濃度ｎ＋拡散層（１２）を
ベース層（３）内に形成すると共にベースコンタクト（
５）に接続することにより、抵抗（８）の抵抗値ｒ３を
小さくすることができる。このため、ベース拡が９抵抗
ｒｂｂ’が小さくなり、雑音特性を向上することができ
る。なお、この場合、ベース幅やベース層の濃度および
厚さは従来のままでよい。Next, to explain the noise characteristics of the vertical PNP () run lister with the above configuration, a high concentration n+ diffusion layer (12) is formed in the base layer (3) and the base contact (
5), the resistance value r3 of the resistor (8) can be reduced. Therefore, the base expansion resistance rbb' becomes smaller, and the noise characteristics can be improved. Note that in this case, the base width and the concentration and thickness of the base layer may remain the same as before.

以上詳細に説明したように、この発明に係る半導体集積
回路装置によれば縦形ＰＮＰ　トランジスタにおけるベ
ース層のベース幅やベース層の濃度および厚さを変える
ことなしに、ベース拡がり抵抗を小さくすることができ
るため、雑音特性を向上させることができる効果がある
。As explained in detail above, according to the semiconductor integrated circuit device of the present invention, it is possible to reduce the base spreading resistance without changing the base width of the base layer or the concentration and thickness of the base layer in a vertical PNP transistor. This has the effect of improving noise characteristics.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来の半導体集積回路装置を示す概略断面斜視
図、第２図はこの発明に係る半導体集積回路装置の一実
施例を示す概略断面斜視図である。 （１）・・・・Ｐ　基板、（２）・・・・Ｐ　分離層、
（３）・・・、ベース層、（４）−−−−エミツタ層、
（５）。 ・・・ベースコンタクト、（６）　、　（７）および（
８）・・・・抵抗、（９）・・・・コレクタ電極、（１
０）・・・・エミッタ電極、（１１）・・・・ベース電
極、（１２）・・・・高濃度ｎ＋拡散層。 なお、図中、同一符号は同一または相当部分を示す。 代理人　　葛　野　信　− 手　続補　正　書、（自発）５゜ 昭和　　年　　月　　口 ６゜ ’ｌ’−１１°許庁長宮殿 １、”１を件の表示　　　　１．１・願昭　５７−１８
５８０６号２、発明の名称 半導体県債回路装置 ３　補正をする者 事件との関係　　　特許出願人 住　所　　　　　東３ｊＣ都千代田区丸の内二丁目２番
３号名　称（６０１）　　　三菱電機株式会社代表者片
山仁八部 ４、代理人 住　所　　　　　東京都工代田区丸の内二丁ロ２番３汀
補正の対象 明細書の発明の詳細な説明の欄 以　　上FIG. 1 is a schematic cross-sectional perspective view showing a conventional semiconductor integrated circuit device, and FIG. 2 is a schematic cross-sectional perspective view showing an embodiment of the semiconductor integrated circuit device according to the present invention. (1)...P substrate, (2)...P separation layer,
(3)..., base layer, (4)---emitter layer,
(5). ...Base contact, (6), (7) and (
8)...Resistance, (9)...Collector electrode, (1
0)...emitter electrode, (11)...base electrode, (12)...high concentration n+ diffusion layer. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Agent Makoto Kuzuno - Procedural amendment (self-motivated) 5゜Showa year month mouth 6゜'l'-11°Kochocho Palace 1, ``1'' 1.1・Gan Showa 57-18
5806 No. 2, Name of the invention Semiconductor prefectural bond circuit device 3 Relationship with the case of the person making the amendment Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Higashi 3JC Name (601) Mitsubishi Electric Corporation Representative Katayama Ninhachibe 4, Agent Address: 2-3 Marunouchi 2-chome, Kodaita-ku, Tokyo, Japan Detailed description of the invention in the specification subject to amendment

Claims (1)

【特許請求の範囲】[Claims] 縦形ＰＮＰ　）ランリスタを用いた半導体集積回路装置
において、前記縦形ＰＮＰ　）ランリスタのベース層に
、エミツタ層よシ深い前記ベース層と同極性の高濃度拡
散層を形成し、この高濃度拡散層をベースコンタクトに
接続したことを特徴とする半導体集積回路装置。In a semiconductor integrated circuit device using a vertical PNP) run lister, a high concentration diffusion layer having the same polarity as the base layer and deeper than the emitter layer is formed in the base layer of the vertical PNP run lister, and this high concentration diffusion layer is used as the base layer. A semiconductor integrated circuit device characterized by being connected to a contact.
JP18580682A 1982-10-20 1982-10-20 Semiconductor integrated circuit device Pending JPS5974672A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18580682A JPS5974672A (en) 1982-10-20 1982-10-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18580682A JPS5974672A (en) 1982-10-20 1982-10-20 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS5974672A true JPS5974672A (en) 1984-04-27

Family

ID=16177212

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18580682A Pending JPS5974672A (en) 1982-10-20 1982-10-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5974672A (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326580A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Semiconductor unit
JPS5456777A (en) * 1977-10-14 1979-05-08 Nec Corp Semiconductor device
JPS54101289A (en) * 1978-01-27 1979-08-09 Hitachi Ltd Semiconductor device
JPS5550656A (en) * 1978-10-09 1980-04-12 Toshiba Corp Semiconductor device
JPS55134963A (en) * 1979-04-09 1980-10-21 Nippon Telegr & Teleph Corp <Ntt> Composite semiconductor device and manufacture thereof
JPS5815268A (en) * 1981-07-21 1983-01-28 Nec Corp Semiconductor device
JPS58210672A (en) * 1982-06-01 1983-12-07 Nec Corp Semiconductor device
JPS58212171A (en) * 1982-06-02 1983-12-09 Hitachi Ltd Semiconductor device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326580A (en) * 1976-08-25 1978-03-11 Hitachi Ltd Semiconductor unit
JPS5456777A (en) * 1977-10-14 1979-05-08 Nec Corp Semiconductor device
JPS54101289A (en) * 1978-01-27 1979-08-09 Hitachi Ltd Semiconductor device
JPS5550656A (en) * 1978-10-09 1980-04-12 Toshiba Corp Semiconductor device
JPS55134963A (en) * 1979-04-09 1980-10-21 Nippon Telegr & Teleph Corp <Ntt> Composite semiconductor device and manufacture thereof
JPS5815268A (en) * 1981-07-21 1983-01-28 Nec Corp Semiconductor device
JPS58210672A (en) * 1982-06-01 1983-12-07 Nec Corp Semiconductor device
JPS58212171A (en) * 1982-06-02 1983-12-09 Hitachi Ltd Semiconductor device

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