JPS5815263A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5815263A
JPS5815263A JP11396181A JP11396181A JPS5815263A JP S5815263 A JPS5815263 A JP S5815263A JP 11396181 A JP11396181 A JP 11396181A JP 11396181 A JP11396181 A JP 11396181A JP S5815263 A JPS5815263 A JP S5815263A
Authority
JP
Japan
Prior art keywords
lead
plate
terminal
static electricity
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11396181A
Other languages
Japanese (ja)
Inventor
Shuji Kondo
修司 近藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11396181A priority Critical patent/JPS5815263A/en
Publication of JPS5815263A publication Critical patent/JPS5815263A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/60Protection against electrostatic charges or discharges, e.g. Faraday shields
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PURPOSE:To prevent the damage of a circuit element chip associated in a package by the influence of static electricity when the static electricity is applied to the lead terminal of the package. CONSTITUTION:The end of a lead terminal 4 is formed in a structure having a shortcircuit lead 8 at one end of a shortcircuit plate 7. The coupler 9 of the terminal 4 to the plate 7 is formed in a shape such as wedge or conical shape at the end of the terminal 4, and is constructed locally in an ultrafine coupling structure with the plate 7. Accordingly, when several bending forces are applied to the plate 7, the coupler 9 can be simply and readily broken, and the plate 7 and the terminal 8 can be separated. In this manner, since all the lead terminals are connected immediately before use, even if static electricity is applied to the lead terminal during the stock or transportation, all the leads becomes the same voltage. Thus, an accident of damaging the circuit element chip due to the production of potential difference at the chip can be prevented.

Description

【発明の詳細な説明】 本発明は、半導体装置に関するものであり、特にパッケ
ージのリード端子に、静電気が印加された時に、パッケ
ージ内部に組込れた回路素子チップが該静電気の影響で
破損することを防いだ、リード端子の構造に関するもの
である。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and in particular, when static electricity is applied to the lead terminals of a package, a circuit element chip incorporated inside the package is damaged due to the influence of the static electricity. This relates to the structure of the lead terminal that prevents this from occurring.

IC、LS Iなどの回路素子チップ(以下単にチップ
と略称する)、特にMOS型チップなとは、チップ内に
電位差が生じた場合、その電位差によりチップの機能が
損傷破壊されることがある。
When a potential difference occurs within a circuit element chip (hereinafter simply referred to as a chip) such as an IC or LSI, especially a MOS type chip, the function of the chip may be damaged or destroyed by the potential difference.

チップを損傷破壊に至らしめる電位差の多くは、保管、
運搬、或は取扱時に生じる静電気によるものであシ、そ
の静電気がリード端子を通じてチップ内に電位差を生じ
せしめることに起因するチップの機能の破壊が多い0 静電気からチップを保護する対策として、従来韮り種々
の方策が講じられており、例えば、導電性スポンジにリ
ード端子を差し込んで保管運搬する方法、導電材料(金
属など)で構成された専用運搬具、或はリード端子ガー
ドルを用いるなど、特別に工夫された治具、装置により
、チツフ一端F−間即ちチップ内に電位差の発生を防ぐ
方法が採用されている。
Many of the potential differences that damage and destroy chips occur during storage,
This is due to static electricity generated during transportation or handling, and the functionality of the chip is often destroyed due to the static electricity creating a potential difference within the chip through the lead terminals. Various measures have been taken to prevent this, such as storing and transporting lead terminals by inserting them into conductive sponges, using special carriers made of conductive material (metal, etc.), or using special lead terminal girdles. A method has been adopted to prevent the generation of a potential difference between one end of the chip and the other end of the chip, that is, within the chip, using specially designed jigs and devices.

本発明は上記の従来例と同様に、静電気の影響で、チッ
プ内に電位差を生じることによる破損を防ぐ目的である
が、上記従来例と異なり、特別の治具、装置を必要とし
ないリード端子構造をイiする半導体装置を提供するも
のである。
Similar to the above conventional example, the purpose of the present invention is to prevent damage caused by potential differences within the chip due to the influence of static electricity, but unlike the above conventional example, lead terminals do not require special jigs or equipment. The present invention provides a semiconductor device having a good structure.

以下、まず、従来の半導体装置のパッケージの構成につ
いて説明する。
First, the configuration of a conventional semiconductor device package will be described below.

なお以丁の説明は、樹脂封止型パッケージを例にあげて
行なう。、第1図は、従来の憤j脂封正型パッケージ用
リードフレームの一般的な形状を示したものである。ダ
ブ1に半導体チップを接着し、リード2にリードワイヤ
で所定の配線を行なった後、樹脂封止3を施こす0樹脂
封止後、第2図に示す如く、斜線部で示すリード端子4
のみを残してリードフレーム外枠ら、保持板6を切除し
た後、リード端子4を折曲げて第3図の如き完成品とす
る。
The following explanation will be given using a resin-sealed package as an example. FIG. 1 shows the general shape of a conventional lead frame for a sealed package. After adhering the semiconductor chip to the dub 1 and performing predetermined wiring with lead wires to the leads 2, resin sealing 3 is applied.After resin sealing, as shown in FIG.
After removing the outer frame of the lead frame and the retaining plate 6, leaving only the lead terminals 4, the lead terminals 4 are bent to form a finished product as shown in FIG.

以上が従来の一般的な半導体装置のパッケージの製法及
び構造である。
The above is the manufacturing method and structure of a conventional general semiconductor device package.

しかし、このような従来の半導体装置は、先に述べたよ
うに静電気によって破壊されるのを防止するために特別
に工夫された冶具、装置を必要とした。
However, such conventional semiconductor devices require specially devised jigs and devices to prevent them from being destroyed by static electricity, as described above.

本発明は、特別の治具、装置を必要とせず静電気による
破壊を防止できる半導体装置を提供するものであり、以
下本発明の詳細な説明する。
The present invention provides a semiconductor device that can prevent damage caused by static electricity without requiring special jigs or equipment, and the present invention will be described in detail below.

(実施例1) 本実施例の半導体装置におけるリードフレームの構造は
第4図に示す如く、リード端子4の先端部には、短絡板
7f:有し短絡板7の一端に4士短絡リード8を有した
構造である。リード端子4と短絡板7の結合部9は、第
4図、第6図に示す如く(第6図は第4図の破線内部A
の拡大図)、IJ−ド端子4の先端は楔状或は錐先状な
どの形状で、短絡板7とは局部的な微細結合構造となっ
ている5、したがって、短絡板7に数回の曲折力を加え
7Iは簡便容易に結合部9が折損し、短絡板7とリード
端子8が分離出来る構造となっている。
(Example 1) As shown in FIG. 4, the structure of the lead frame in the semiconductor device of this example is as shown in FIG. It has a structure with The connecting portion 9 between the lead terminal 4 and the shorting plate 7 is as shown in FIGS.
(enlarged view), the tip of the IJ-domain terminal 4 has a wedge-like or cone-like shape, and has a locally fine bonding structure with the shorting plate 7. 7I has a structure in which the connecting portion 9 can be simply and easily broken by applying a bending force, and the shorting plate 7 and the lead terminal 8 can be separated.

−J二記構造を有t〜だリードフレームに、通常のJj
法で回路素子チップを組立て、樹脂封止3を施こした後
、第4図に示す斜線部、即ちリードフレームの外枠6及
び保持板6部を切断除去すると、樹脂封止3部11+t
1面のリード端子4,4′は、隣接するリード端子間か
、短絡板7で相互に接続さノ1だ形状のリード端子とな
る。
- A lead frame with a J2 structure, a normal JJ
After assembling the circuit element chip by the method and applying resin sealing 3, cutting and removing the shaded portion shown in FIG.
The lead terminals 4 and 4' on one side are connected between adjacent lead terminals or connected to each other by a shorting plate 7, forming an oval-shaped lead terminal.

しかる後、リード端子4,4′を第6図の如く、所定の
角度(はぼ90度)に折り曲げ、さらに短絡リード8,
8′を、短絡板7に対し該略泊角に折り曲げれば、短絡
リード8,8′自体の弾性により、短絡リード8,8′
の先端部9は堡に接触状態を保持することになり、すべ
てのリード端子が、電気的に等電位となり、いずれかの
リード端子に静電気が印加されてもリード端子間に大き
な電位差が生じることを防ぐことが出来る。
After that, the lead terminals 4, 4' are bent at a predetermined angle (approximately 90 degrees) as shown in FIG.
If the short-circuiting leads 8, 8' are bent to the approximately angle with respect to the short-circuiting plate 7, the short-circuiting leads 8, 8' will be bent due to the elasticity of the shorting leads 8, 8' themselves.
The tip 9 of the lead terminal remains in contact with the redoubt, and all the lead terminals have an electrically equal potential, and even if static electricity is applied to any lead terminal, a large potential difference will occur between the lead terminals. can be prevented.

上記の実施例では、パッケージの左右のリード端子間の
接続は、短絡リードの弾性を利用して接続する方式で説
明したが、さらに強固な接続状態を保持させる必要があ
る場合には、短絡リード8゜8′の先端部9の接触点を
、溶接、半田付け1等の六法で固着させればよい。
In the above example, the connection between the left and right lead terminals of the package was explained using the elasticity of the short-circuited leads. However, if it is necessary to maintain an even stronger connection, the short-circuited leads The contact point of the 8° 8' tip 9 may be fixed by any of the six methods such as welding, soldering, etc.

以上の如くのリード端子構造を有する半導体装置を用い
れば、使用直前までリード端子間がすべて接続されてい
るため、保管運搬中に、リード端子に静電気が印加され
ても、全リード端子が同電位となるため、回路素子チッ
プに電位差が生じて破損する事故が防止される。
If a semiconductor device having the lead terminal structure as described above is used, all the lead terminals are connected until just before use, so even if static electricity is applied to the lead terminals during storage and transportation, all the lead terminals will have the same potential. Therefore, an accident in which a potential difference occurs in the circuit element chip and causes damage to the circuit element chip is prevented.

同半導体装置の使用法は、使用直前に、リード端子の先
端に設けた短絡板7,7′に、数回の曲折力を加えれば
、前述の如く、楔状或は錐先状の結合部9が容易に折断
し、リード端子は夫々独立したリード端子となるため、
使用時の取扱上の1月題はほとんどないと言える。
The semiconductor device is used by applying bending force several times to the shorting plates 7 and 7' provided at the tips of the lead terminals immediately before use, and as described above, the wedge-shaped or cone-shaped coupling portion 9 is formed. easily breaks, and each lead terminal becomes an independent lead terminal.
It can be said that there are almost no January problems when using it.

(実施例2) 実施例1では、樹脂封止型ノ(ツケージのリードフレー
ムの形状で説明したが、セラミツクツ(ツケージでも、
基本的には同一構造で、同様の効果力;得られる。
(Example 2) In Example 1, the shape of the lead frame was explained using a resin-sealed type (cage).
Basically, they have the same structure and the same effects can be obtained.

第7図は、半導体ペレット組立直後のセラミンクパッケ
ージの平面図であり、リード端子41゜41物先端は、
実施例1と同様に第6図の如く、楔状、或は錐先状を有
して局部的に短絡板71゜71′と接がって居り、短絡
板に数回の折り曲げ操作を加えると容易に短絡板71.
71’がIJ −)” m子41.41’から折断分離
構造としである。
FIG. 7 is a plan view of the ceramic package immediately after the semiconductor pellet is assembled, and the tip of the lead terminal 41° is
As in Embodiment 1, as shown in FIG. 6, it has a wedge-like or cone-like shape and is locally connected to the shorting plates 71° and 71', and when the shorting plate is bent several times, Easily short circuit plate 71.
71' is the IJ-)" m-shaped member 41. The structure is broken and separated from 41'.

第8図は第7図のリード端子41.41’を所定角度折
り曲げた後のノζツケージの正面図である。
FIG. 8 is a front view of the cage after the lead terminals 41 and 41' of FIG. 7 are bent at a predetermined angle.

リード端子41.41’に接かった短絡板71.71’
に附属する短絡リード81.81’は、図の如く、リー
ド端子に対し概略直角に曲折すると、短絡リード81.
81’はパッケージの下部で、短絡リード自体が有して
いる弾性により、短絡リード81゜81′相互間が圧接
され、パッケージのリード端子はすべてが電気的に結合
されたことに在る。
Shorting plate 71.71' connected to lead terminal 41.41'
When the short-circuit leads 81.81' attached to the short-circuit leads 81.81' are bent approximately at right angles to the lead terminals as shown in the figure, the short-circuit leads 81.81' become short-circuit leads 81.
81' is the lower part of the package, and due to the elasticity of the shorting leads themselves, the shorting leads 81 and 81' are brought into pressure contact with each other, and all the lead terminals of the package are electrically connected.

なお短絡リード81.81’を実施例1と同様に溶接等
の方法で固着すれば、固着部が強固になる。
Note that if the short-circuiting leads 81, 81' are fixed by a method such as welding as in the first embodiment, the fixed portion becomes strong.

また半導体装置の使用法は実施例1と同様である。Further, the method of using the semiconductor device is the same as in the first embodiment.

以トの如く本発明の半導体装置を用いれば、リード端子
がすべて良電導体で接続されて居り、リード端子に静電
気が印加された場合にも、パッケージ内の半導体ペレッ
トに電位差が生じることを効果的に明止し、静電破壊か
ら半導体ペレットを保護することが容易に可能になる。
As described above, if the semiconductor device of the present invention is used, all the lead terminals are connected with good conductors, and even if static electricity is applied to the lead terminals, it is possible to prevent the potential difference from occurring in the semiconductor pellet inside the package. This makes it easy to protect semiconductor pellets from electrostatic damage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図と第2図は従来の半導体装置のリードフレームの
平面図、第3図は従来の樹脂封止型の半導体装置のパッ
ケージの斜視図、第4図は本発明の一実施例における半
導体装置のリードフレームの平面図、第5図は同リード
フレームの要部拡大斜視図、第6図は同リードフレーム
を用いた本発明の一実施例における半導体装置の正面図
、第7図は本発明の他の実施例における半導体装置の3
V−面図、第8図は同、半導体装置の正面図である。、
3.31 ・・・・・・ノくツケージ本体、4.4’、
41゜41/・・・・・・リード端子、6・・・・・・
リードフレーム外枠、7 、7’、 71 、71’・
・・・・・短絡板、8.8’。 81.81’・・・・・・短絡リード。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名第1
図 $211 113図 114図 115図 卒6図 第7図 第8図
1 and 2 are plan views of a lead frame of a conventional semiconductor device, FIG. 3 is a perspective view of a conventional resin-sealed semiconductor device package, and FIG. 4 is a semiconductor device according to an embodiment of the present invention. 5 is an enlarged perspective view of the main parts of the lead frame, FIG. 6 is a front view of a semiconductor device according to an embodiment of the present invention using the same lead frame, and FIG. 7 is a diagram of the present invention. 3 of the semiconductor device in other embodiments of the invention
The V-plane view and FIG. 8 are front views of the semiconductor device. ,
3.31 ・・・・・・Cage body, 4.4',
41゜41/...Lead terminal, 6...
Lead frame outer frame, 7, 7', 71, 71'・
...Short circuit plate, 8.8'. 81.81'...Short lead. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 1
Figure $211 113 Figure 114 Figure 115 Figure 6 Figure 7 Figure 8

Claims (1)

【特許請求の範囲】[Claims] 先端部が細くなった電極リード端子と、前記電極リード
端子の先端部に局部結合し、前記電極リード端子を互い
に電気的に接続する短絡板とを備え、前記短絡板が前記
電極リード端子より切断除去できるようにしたリードフ
レームを有することを特徴とする半導体装置。
An electrode lead terminal having a tapered tip, and a shorting plate locally coupled to the tip of the electrode lead terminal to electrically connect the electrode lead terminals to each other, the shorting plate being cut from the electrode lead terminal. A semiconductor device characterized by having a removable lead frame.
JP11396181A 1981-07-20 1981-07-20 Semiconductor device Pending JPS5815263A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11396181A JPS5815263A (en) 1981-07-20 1981-07-20 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11396181A JPS5815263A (en) 1981-07-20 1981-07-20 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5815263A true JPS5815263A (en) 1983-01-28

Family

ID=14625535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11396181A Pending JPS5815263A (en) 1981-07-20 1981-07-20 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5815263A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547795A (en) * 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
JPS6418750U (en) * 1987-07-22 1989-01-30

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4547795A (en) * 1983-03-24 1985-10-15 Bourns, Inc. Leadless chip carrier with frangible shorting bars
JPS6418750U (en) * 1987-07-22 1989-01-30

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