JPS58151670A - Picture data processing device - Google Patents

Abstract

PURPOSE:To process a large quantity of picture data at a high speed, by editing the picture data in real time by an editing circuit, and also constituting so as to use a frame memory of only 1 face. CONSTITUTION:Each byte to be inputted is inputted in order to a data register of a frame memory, and is stored in an address disignated by address information of a memory address register 52. Subsequently, whenever 1 byte of a picture data is stored, a store address is updated by +1, and a horizontal counter 55 is also counted up. In such the way, when the last byte of the head line is stored in the frame memory, the counter 55 is counted up to a value (w), and a detecting signal 60 is outputted from a comparator 57. Subsequently, when the last byte of the line of the field is stored in the frame memory, the coincidence is made by a comparator 58, a signal 62 is outputted, and the editing end of the head field is detected.

Description

[Detailed Description of the Invention] The subject of the invention is an output format of an output device lid on a frame memory, which is based on the image data that is divided into fields and inputted, and the editing information that is manually input for each field. (Edit the two together, output sub-side 1 for 1 and 1 elephant theta)
The present invention relates to an image take processing device that performs.

BACKGROUND ART In the conventional 1liIi image data processing apparatus, editing of the data for one song is executed by program processing using two frame memories. That is, as shown in FIG. 1, the host computer 1 divides the image take (fields A to 1) from the dependent medium into fields by field and inputs the image data (fields A to 1). At number 1, add 41' to the first frame memo IJ 1.1 i. Then,
@Feather - The program changes each field on the frame memo 1 to its ossuary collection 1 information (2, therefore, to the second frame memory 12 in accordance with the output format of the output device of the horizontal scanning type output device. 1 gathering.

Because of this configuration, conventional double-image take processing devices require a relatively long processing time when processing a large amount of image data, and require 21 I] of frame memory, which makes the device There was a problem with increasing costs.

OBJECTS OF THE INVENTION It is an object of the present invention to improve the problems of the prior art and to provide a single image data processing device that uses a frame memory to perform high-speed editing of image takes in real time.

Thus, the image take processing device according to the present invention includes an editing circuit for editing image data in real time. This editing circuit includes a first circuit means for setting and holding editing information of a field to be edited (field of interest) of image data, and a first circuit means for setting and holding the editing information for a field to be edited (field of interest) of the image data, and holding address information for storing the image data in the frame memory. , and the storage start address information of the field of interest determined based on the editing information before the start of editing of the field of interest is set.
(3) circuit means, a third circuit means whose held value increases each time a predetermined number (one byte or several bytes) of the field of interest is stored in the frame memory, and a held value of the eighth circuit means; and a fourth circuit that detects that the last byte of the line currently being edited in the field of interest is stored in the frame memory based on the editing information held by the first circuit means and outputs a detection signal. means, a fifth circuit means whose held value increases each time a detection signal is output from the fourth circuit means, a held value of the fifth circuit and editing information held by the first circuit means. a sixth circuit means for detecting that the last byte of the field of interest has been stored in the frame memory and outputting a detection signal based on the detection signal from the fourth circuit means and the first circuit means; a seventh 1U path and ten stages for controlling update of the address information held by the second circuit means based on the editing information held by the fourth circuit means; When the held value of the eighth circuit means is reset and a detection signal is output from the sixth circuit means, the fifth
When the held value of the circuit means is reset, (4) the editing information and storage start address information of the field next to the field of interest are respectively set in the first and second circuit means (2).

Embodiments of the Invention The input format of image data is generally defined as the format shown in FIG. 2 or FIG. 8, whether it is input manually from a host computer or input manually from a replacement storage medium.

In the data format shown in FIG. 8, each field (A-D) 202, 212, 222, 28 of the image take
21d.

Edit information (referred to as rectangle take) 201 immediately before that.

211, 221, and 231 are added and manually added.

In the data input format of FIG. 8, the image take valley fields (A, D) 802, 812.822, 882
Rectangular data 301 , all , 321 , 88
1 will be sent to the front man all at once.

In either of these data formats, the contents of the rectangular data and image data are generally as shown in FIG.

The rectangular data for one field is shown in Figure 4 (a).
As shown in the figure, after the first key code KEY, the four positions a and b of the corresponding field and the size of the corresponding field w,
This is a configuration in which the information in h is continued. The image data is shown in Figure 4 (
As shown in b), the image information of each line (W bytes/line) is arranged from the first line to the last line of the corresponding field with the key code KI at the beginning. Figure 4 (c) shows the address space of the frame memory (corresponding to the output format), with X bytes (horizontal direction)
This is the size of the xy line (vertical 1α direction). a above,
b, w, and h are information having meanings as shown in FIG. 4 (c).

Next, one embodiment of the present invention will be described. Note that the data may be in either the format shown in Figure 2 1 or Figure 8, but for convenience, the format shown in Figure 2 is used, and the contents of the rounded rectangle data and image data are as shown in Figure 4. It will be explained as follows.

FIG. 5 is a block diagram illustrating one embodiment of the present invention. However, FIG. 5 only shows the editing circuit, which is the main part of the image data processing apparatus according to the present invention, and includes the frame memory, its read/write control circuit, and the interface control unit with the host computer switching storage medium. ,
The interface control unit with the output device, the central processing that controls the entire device and the performance center, etc. are omitted for the sake of brevity.

In FIG. 5, 51 is a field address register that holds rectangular data, and 52 is a memory address register that holds address information that specifies the address of a frame memory (not shown) where image data is to be stored. Reference numeral 53 is a line address register that holds band information indicating the frame memory address at which the first byte of the currently processed line of the field being edited has been stored, and 54 is an adder for address calculation.

55il''j: horizontal counter; 56 is a vertical page counter; horizontal counter) 5 is a counter for detecting whether the first byte of the currently processed line in the field being edited has been stored in the frame memory. It is.

The vertical counter 56 is a counter for detecting whether up to the first line of the field being edited has been stored in the frame memory (I). 57 and 58 are comparators, respectively. When the ratio f9 unit 57c detects a match between the information W in the field address register 51 (horizontal length of the field, number of bytes) and the value held in the horizontal counter 5 (count 11a), the detection number 6o is detected. Output. This comparator 571ITt, logical negation signal 61 of the detection signal 6o
is also output. When the comparator 58 detects a match between the information h (vertical length (number of lines) of the field) in the field address register 51 and the value (count value) held in the vertical counter 56, it outputs a detection signal o2. 68-71
It's Nigate. The gates 63 to 66 are opened when the detection signal 62 from the comparator 58 is output (logic "1"). Gates 67 and 69 are open when the signal 61 from the comparator 57 is output (when processing is "1"), and gates +) 8.
10. 71 is when the detection signal 6o is output (logic "i"
(when l+) opens.

Note that the horizontal counter 55 counts up by 1 in response to the signal 61, and is reset in response to the detection signal 6o. The comparator 57 is
Each time one byte of image data is stored in the frame memory, the signal 60 and 61 are output, so the horizontal counter (8
) The value of 35 matches the number of stored bytes of the line being processed. The vertical counter 56 counts up by 1 with a signal 150 and is reset with a signal 62. Therefore, the first column of the vertical counter 56 is set to the number of lines stored in the field currently being processed. The adder 54 adds 1 to the input 11N each time the signal N 61 is output and outputs the result, but when the signal 60 is output and the value X is given through the gate 71, it adds X to the input value. and output it.

First, the composition of edited song j in this real 7AI example will be explained.

When rectangular data of the first field is input from the host computer according to the data input format shown in Figure 2 from the medium, the central processing unit of the image data processing device inputs the rectangular data. 1f in the rectangular data at the same time.
"Use information a and b to store the start address of the field (a
10b-y) is set in the 9-output memory address register 52 and the line address register, )3. In addition,
At this point, the horizontal and vertical 1 and 56 counters are set. As in the past, the fact that the human-powered data is rectangular data is identified by the key code at the beginning (FIG. 4).

Next, the image data of the first field of J& is manually entered sequentially from the first line following the key code (FIG. 4).

Each manually inputted byte is inputted once to a data register of a frame memory (not shown), and stored in the band specified by the address information of the memory address register 52. At this time, each time a byte is stored, a comparison is performed. The address information in the memory address register 52 is input to the adder 54 via the gate 67 in response to a signal 61 output from the device 57, and after being added by +1, it is reset to the memory address register 52 via the 5 gate 60. That is, each time one byte of image data is stored, the storage address is updated by +1.At the same time, the horizontal counter 05 also counts up.

In this way, the last byte (W byte) of the first line
is stored in the frame memory, the horizontal counter 5 counts up to 1 increments, and the comparator 57 outputs a detection signal 60. As a result, the horizontal counter 55 is reset and the vertical counter 56 is incremented by one. Also, the line address register D is connected via the gate.
The contents of 3 are manually input to the adder M, and the 1st value added by 10X is reset to the memory address register 52 and the line address register 63 via the gate 70. Therefore, the address of the frame memory where the first byte of the second line is to be stored is set in both address registers 52 and 53i. Thereafter, each byte of the second line is sequentially stored in the frame memory while incrementing the address by 1 as described above.

As described above, when the last byte of the last line (h main line) of the field is stored in the frame memory, a match is found in the comparator 58 and a signal 62 is output. That is, the end of editing of the first field is detected, the rectangular data of the next field is set in the field address register 51 through gates 63 to 66tn, and the storage start address information of that field is still stored in the memory address register 52.
and line address register 53 (reset. The horizontal, 0υ and vertical counters, i5.56, are reset by signals 60 and 62i, respectively.Then, the image data of the corresponding field is edited in the same way as described above. Ru.

In this embodiment, the image data is stored in the frame memory in units of one byte, but it may be stored in units of multiple bytes. However, if data is to be stored in units of 2 bytes, for example, it is necessary to increase the address information of the memory address register 52 and the value of the horizontal counter 55 by 2. Furthermore, after performing the boundary correction, the comparator 5
It becomes necessary to operate 7. Also, comparator 57. '
A single comparator may also be used for S. Furthermore, instead of calculating the storage start address of each field in the central processing section, a circuit for calculating the storage start address of each field may be provided in the editing circuit.

It should be noted that although the explanation has been made assuming the case of the data manual format shown in FIG. 2, it is obvious that the above embodiment can be applied as is to the case of the data manual format shown in FIG. However, a means for storing rectangular data of all fields is required.

Effects of the Invention α As detailed above, the present invention has a configuration in which image data is edited in real time by an editing circuit rather than by program processing, and only one frame memory is used. Therefore, an image data processing device capable of processing large amounts of image data at a higher speed than before can be produced at a lower cost than before.

[Brief explanation of drawings]

Figure 1 is a diagram for explaining the image data editing method in a conventional image data processing device, Figures 2 and 8 are diagrams showing the general input format of image data, and Figure 4 is a diagram showing the image data editing method. FIG. 5, which is an explanatory diagram of the rectangular data, is a block diagram showing the main structure of an embodiment of the present invention. 51...Field address register, 52...Memory address register, 53...Line address register, 54...Adder 1.55...Horizontal counter,
Part...Vertical counter, 57.58...Comparator, 68
~71...Gate.

Claims (1)

[Claims] ＋]) Image data processing that is equipped with an editing circuit that edits image data that is divided into fields and manually inputted sequentially into editing information that is manually edited for each field in real time according to the output format on the frame memory. In the apparatus, the editing circuit includes first circuit means for setting and holding editing information of fields to be concentrated (fields of interest), and address information for storing image data in the frame memory. a second circuit means for storing storage start address information of the field of interest which is determined based on the editing information at the start m of editing of the field of interest; A third circuit means whose held value increases each time it is stored, and a held value of the third circuit means and the first
and a fourth circuit means that detects that the last byte of the line currently being edited in the tenth field is stored in the frame memory based on the editing information held by the circuit means, and outputs the entire detection signal. , a fifth circuit means whose held value increases each time a detection signal is output from the fourth circuit means; a held value of the fifth circuit means and editing information held by the first circuit means; a detection signal from the fourth circuit means and a detection signal from the first circuit means; and a seventh circuit means for controlling updating of the address information held by the second circuit means based on the editing information held by the third circuit means, and when a detection signal is output from the fourth circuit means, the third circuit means When a detection signal is output from the sixth circuit means, the value held in the fifth circuit means is reset, and the editing information and storage amount of the field next to the field of interest are reset. An image data processing device characterized in that address information is set in each of the first and second circuit means.