JPS58151658A - Reading-out circuit of board information - Google Patents

Abstract

PURPOSE:To obtain effective board information within a minimum time, by adding the information for discriminating a board into board error information, to recognize a board in which an error is generated, and inhibiting an output of a memory board having a low priority degree by this signal. CONSTITUTION:To memory boards 10, 20 and 30, priority is given in said order, and from these boards, a common error generating signal 50 is outputted. Subsequently, a board error information reading-out circuit in each memory board outputs the signal 50, simultaneously to generates inhibit signals 12, 22, and 32 to the memory board having a low priority by this error generating signal. Also, each memory board transfers the inhibit signal in order to the subordinate memory board, when the inhibit signal is applied from the host memory board. In this way, among the memory boards in which an error is generated, a board error in the most significant memory board is read out by a CPU40.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a board information reading circuit.

[Technical background of the invention and its problems]

In order to improve its reliability, the main memory device is equipped with FCC (error correction) ffl function, and when an error occurs, board error information (information indicating which memory bit caused the error) is transmitted. The information is forwarded to CPIJ and repaired during maintenance and inspection based on this information. Conventionally, when an error occurs in a memory board constituting the main memory, the CPU issues a board error (lit@i) from the valley memory board at the time of occurrence.

Reading of this board error information has conventionally been executed by the following system.

FIGS. 1 and 2 are block diagrams showing examples of the configuration of the conventional biasing system. First, in the example shown in FIG.
Signal indicating that an error has occurred) 11, 21.3
1, and cpu4o (d) This error 9 generated signal I
The board in which the error occurred is identified by I, 21.31, and the board error information is read from the memory board 1 where the -1 error occurred. However, in the case of this first design with 7 stems, there are as many errors as there are memory boards! 9 generation signals must be prepared, and this method is becoming difficult to adopt, especially in these days when the degree of nap integration of C1-'U has increased and efficient use of input/output bins has become an important issue. .

Next, in the example of FIG. 2, each memory board 10, 20.

I has a common error occurrence signal, and as shown in Figure 3, the first bit of the board error information, :) ) (other bits may also be used), sets a flag bit indicating the occurrence of an error. elJlo sequentially reads each memory board. However, according to the example in Fig. 2, CP
The average time for U to read the board error information becomes longer; for example, if the main memory is made up of N memory boards, the CPU 4 (J) will have to perform up to N read cycles.

[Purpose of the invention]

The present invention was made in order to solve the above problems, and its purpose is to provide a board information readout circuit that can read out board information with a minimum amount of hardware and a minimum of processing time. There is.

[Summary of the invention]

That is, in the present invention, information for board identification is added to the board error information, and the CPU recognizes the board in which the error has occurred based on this 'liV information, and also uses the error occurrence signal to identify the memory with lower priority. By inhibiting the output gate of the board, multiple pieces of board error information are prevented from coexisting on the data bus.

[Embodiments of the invention]

FIG. 4 is a block diagram showing one embodiment of the present invention, and in this embodiment, each memory board 10.

In addition, 30 is given priority to this number 11. Each of the memory boards 10, 20, and 3o outputs a common error occurrence signal 50, and the board error information reading circuit in the valley memory board outputs an error occurrence signal ``nu'' at the same time. Inhibit signals 12 and 22 for memory boards with low priority depending on the generated signal.
, 32 have been created. Furthermore, when each memory board receives the above-mentioned inhibit signal from the upper memory board 7j-1, it sends an inhibit signal to the lower memory board.
Therefore, among the memory boards where the error occurred, the board error in the highest memory board is C.
)' U 4 (indulged by l.

Figure 5 shows an example of a circuit for reading out board error information in the valley memory board. 63, 64, an AND gate 65, a Nante gate 66, an output register 67, and an output gate 68. An error occurrence signal is applied to the input terminal 69, a read strobe signal from the 02 port 40 is applied to the input terminal 70, an inhibit signal from the upper memory board is applied to the input terminal 71, and the output terminal 7
2 outputs an inhibit signal to the lower memory board, and output terminal 73 outputs an error occurrence signal to the CPU 40.

Next, FIG. 6 is an operation timing diagram of this embodiment when an error occurs on the upper memory board and the lower memory board at the same time. In FIG. The area below the broken line represents the operation of the lower memory board.

When a board error occurs in a memory board, regardless of whether it is an upper or lower memory board, board error information (this information includes information for identifying the memory board) is written to the output register 67, and the input terminal The negative logic error occurrence signal applied to 69 becomes low level. At the falling edge of the error generation signal applied to the input terminal 69, the flip-flop 61 is set and its Q output becomes low level. The Q output of this flip-flop 61 is passed through inverters 62 and 64 and an output terminal 73 to
)' The occurrence of a negative logic error in tJ40 is transmitted to No. 11 in color, and the output of ANDKATE 65 is lowered to low level, and the negative logic is inhibited from the output terminal 72)
<I is transmitted to the lower memory board as number i. Therefore, at the same time that the flip-flop 61 in the upper memory board is set, the output gate 68 in the lower VC memory board is inhibited.

On the other hand, when the negative logic error occurrence signal 50 applied from the output terminal 73 becomes low level, the CPU 4 (1) knows that a board error has occurred in one of the memory boards, and outputs the input terminal 70 of all memory boards. The negative logic read strobe signal applied to the output signal is set to low level for one period of time.

A negative logic read strobe (i) applied from the CPU 4 (+) is inverted by an inverter 63 and applied to one input of a Nant gate 66.

At this time, the Nant gate 66 in the upper memory board
Since the input is at high level, the output of the NAND gate 66 becomes low level for the same time as the read strobe signal 9, and the board error information of the upper memory board is output from the output gate 68 to the data bus of the CPU 40. , the CPU 40 uses this board error information to know in which storage bit of which memory board an error has occurred.

- One of the inputs of the Nant gate 66 in the lower memory board is brought to a low level by the low level inhibit signal applied to the input terminal 71 of that memory board from the output terminal 72 of the upper memory board. Therefore, the output of the lower memory board's NAND gate remains at high level. Therefore, the output gate 68 of the lower memory board remains closed, and the board error information omitted in the output register 67 is retained as is.

When the read strobe signal applied from the CPU 40 to the input terminals 70 of all memory boards becomes high level after a period of time has passed, the rising edge of the read strobe signal causes the Noritsu flop 6 in the memory board to be activated regardless of whether it is upper or lower.
LUtt-, reset p-At this time, both the J input and the input of the 7-lip flop 61 in the upper memory board are at high level, so the Q output and the Q output are inverted, and the output terminal 72
A negative logic inhibitor 2= is applied to the input terminal 71 of the lower memory board from
The negative logic error occurrence signal applied to U4-0 also goes high.

On the other hand, flip-flop 6]1 in the lower memory board
Since the dJ input is high level and the input is low level, Q
The output enable output is not inverted, and the negative logic inhibit HM signal applied from the output terminal 72 to the input terminal 71 of the lower memory board and the negative logic error 1 signal applied from the output terminal 73 to the CPU 40 are low. There are up to level 1.

Therefore, the CPIJ 40 sets the negative logic input signals applied to the input terminals of all memory boards to a low level for one moment.

The negative logic read strobe signal applied from the CPU 40 is inverted by the inverter 63 and
6 is added to one input.

At this time, the flip-flop in the upper memory board is inverted by the inverter 62 and applied to the Nant gate 66, so the output of the Nant gate 66 in this upper memory board remains at high level, and therefore the upper memory The board's output gate remains closed.

On the other hand, since the other two Nant gates 66 in the lower memory board are both at high level, the output of the Nant gate 66 in the lower memory board becomes low level for the same time as the indulgence strobe signal, and the lower Board error information is output from the output gate □□□ of the memory board to the data bus of C)'[J4(], and the CPU 40 uses this board error information to determine which memory port ℃ an error has occurred in which memory bit. Know.

When the read strobe signal applied from the CPU 40 to the input terminals 70 of all memory boards becomes high level after a certain period of time has elapsed, the rising edge of the read strobe signal triggers the 7 lip-flops in all memory boards, regardless of whether they are upper or lower. .

At this time, the 7 lip-flop 61 in the upper memory board
Since the J input is at a low level and the K input is at a high level, its Q output is not inverted.

On the other hand, since the J and K inputs of the 7-lip flop 61 in the lower memory board are both at high level, its Q output is inverted, and therefore the output from the output terminal 72 is input to the input terminal 71 of the lower memory board. The negative logic inhibit signal applied to the output terminal 73 and the negative logic error generation signal applied from the output terminal 73 to the CPU 40 become high level and return to the initial state.

Although the above description has been made using an example where board error information is extracted from a memory board, the present invention is more broadly applicable to a case in which board error information generated in a plurality of input boards is transmitted to a CPU.
It can be applied when the problem starts to emerge.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, U P
(Since J has only one information generation signal (corresponding to the error generation signal in the above embodiment), the CPU
The amount of hardware can be minimized, and the board information (corresponding to the board error information in the above embodiment) includes information for identifying the board. The CPU can learn the necessary board information just by executing one read cycle. That is,
According to the present invention, effective board information can be provided to the CPU with a minimum amount of hardware and a minimum processing time.

[Brief explanation of drawings]

1 and 2 are block diagrams of the conventional rod/stem, FIG. 3 is a diagram showing an example of board information according to the conventional method, and FIG.
The figure is a block diagram showing an embodiment of the present invention, FIG. 5 is a 1U circuit diagram showing an example of the circuit of the present invention, and FIG. 6 is a timing diagram of the present invention. 10.20.30...Memory hoard 40...C
PU12, 22, 32...inhibit signal related
...Error occurrence signal 61...Flip-flop 6
7... Output register 68... Output gate agent Patent attorney Noriyuki Chika (1 other person) 1st prisoner Figure 2 0 Figure 3 [■ Figure 4 Figure 5

Claims (1)

[Claims] When board information is generated, the board information is written to the output register and an information generation signal is output to the CPU, and the output gate is opened in the time width of the read strobe signal applied from the CPU and the output register is sent to the output register. In the board information reading circuit that sends the loaded board information to the data bus of the CPU, information for identifying the board is included in the board information, and the information generation signal or the board with the higher priority is means for generating an inhibit signal for inhibiting the output gate of a board with a lower priority in response to an applied inhibit signal; and means for generating an output of the information generation signal and the inhibit signal when the board information is read by the CPLI. and means for stopping the board information.