JPS58150128U - bus line circuit - Google Patents
bus line circuitInfo
- Publication number
- JPS58150128U JPS58150128U JP4471282U JP4471282U JPS58150128U JP S58150128 U JPS58150128 U JP S58150128U JP 4471282 U JP4471282 U JP 4471282U JP 4471282 U JP4471282 U JP 4471282U JP S58150128 U JPS58150128 U JP S58150128U
- Authority
- JP
- Japan
- Prior art keywords
- pass line
- state
- level clamp
- bus line
- line circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来例を示す図、第２図は本考案の一実施例を
示す図、第３図、第４図はバスの通常動作を説明する図
、第５図、第６図は本考案の他の実施例を示す図である
。
符号の説明、１・・・・・・パスライン、２・・・双方
向性バスドライバー、３・・・出力コントロール端子、
４・・・トライステートドライバー、５・・・レシーバ
−１６・・・電圧源、７・・・プルアップ抵抗、１７・
・・プルダウン抵抗、１８・・・レベルクランプ集積回
路。Figure 1 is a diagram showing a conventional example, Figure 2 is a diagram showing an embodiment of the present invention, Figures 3 and 4 are diagrams explaining the normal operation of the bus, and Figures 5 and 6 are diagrams of the present invention. It is a figure which shows the other Example of an invention. Explanation of symbols: 1...pass line, 2...bidirectional bus driver, 3...output control terminal,
4... Tri-state driver, 5... Receiver-16... Voltage source, 7... Pull-up resistor, 17...
...Pull-down resistor, 18...Level clamp integrated circuit.
Claims (1)
ラインにおいて、前記パスラインに接続されたバスドラ
イバーと、一端を定量圧源にもう一端を前記パスライン
に接続された抵抗もしくはレベルクランプを目的とし前
記パスラインに接続されたレベルクランプ回路より成り
、前記パスラインに接続されたトライステート出力がす
べてディスエーブル状態（高インピーダンス状態）にな
ったときに、前記一端を定電圧源にもう一端を前記パス
ラインに接続された抵抗もしくはレベルクランプ回路に
より、前記パスラインを論理的にハイもしくはローに固
定することを特徴とするパスライン回路。゛In a pass line composed of an integrated circuit with a tri-state output, there is a bus driver connected to the pass line, and a resistor or level clamp with one end connected to the fixed pressure source and the other end connected to the pass line. It consists of a level clamp circuit connected to the pass line, and when all tri-state outputs connected to the pass line are in a disabled state (high impedance state), one end is connected to the constant voltage source and the other end is connected to the pass line. A pass line circuit characterized in that the pass line is logically fixed to high or low by a resistor or a level clamp circuit connected to the line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4471282U JPS58150128U (en) | 1982-03-31 | 1982-03-31 | bus line circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4471282U JPS58150128U (en) | 1982-03-31 | 1982-03-31 | bus line circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58150128U true JPS58150128U (en) | 1983-10-07 |
Family
ID=30055760
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4471282U Pending JPS58150128U (en) | 1982-03-31 | 1982-03-31 | bus line circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58150128U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02311919A (en) * | 1989-05-26 | 1990-12-27 | Nec Corp | Bus line system |
-
1982
- 1982-03-31 JP JP4471282U patent/JPS58150128U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02311919A (en) * | 1989-05-26 | 1990-12-27 | Nec Corp | Bus line system |
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