JPS58148478A - Manufacture of josephson integrated circuit - Google Patents

Abstract

PURPOSE:To prevent separation and flaws of photoresist attendant with the contact exposure of the photoresist and to improve the yield rate, by forming a highly protruded convex part in the region of a substrate other than the region required for forming the Josephson integrated circuit in advance. CONSTITUTION:The positive type photoresist is applied on the silicon substrate 1. The substrate is exposed by using a convex part forming mask pattern and developed. Then an SiO2 evaporation film (thickness is 1-3mum) is formed on the entire surface. The photoresist and the SiO2 film are removed and the convex part 31 is formed at the outside of the Josephson integrated circuit region. When the photoresist 41 is applied, the part of the photoresist at the convex part 31 is highest. Therefore, when a photomask 42 is contacted with the photoresist 41 for contact exposure, a photoresist part 43 is intensely adhered to the photomask. However, the photoresist part on the constitutional part of the Josephson integrated circuit is not contacted with the photomask, and the separation and flaws do not occur.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to an integrated circuit element, and more specifically, to an integrated circuit element:
This is similar to the rJ method.

(2) Prior art and problems The development and application of integrated circuits including di-electronic junctions (i.e., di-electronic integrated circuits) is progressing (for example, art materials [i.e., The beginning of mourning 7
"Son Logic Device", Nikkei Elect 12ris, 1979
(Reference: July 9, issue 216, pp. 56-72)
It is important in manufacturing to form a fine metal layer in order to increase the degree of integration, shorten the processing time, and reduce power consumption. Additionally, it is also important to dramatically improve the yield rate of 9 in manufacturing doffing.

One of the reasons for the decline in the yield of integrated circuits is the occurrence of photoresist peeling and damage in microfabrication technology.

At IIc during exposure of photoresist coated in %,
Part of the 1st photoresist was peeled off in order to attach the photomask to the 7th photoresist KIF (for contact exposure).
(i.e., adhesion of the resist to the 7-axis mask)
The Luzost surface may be scratched, and this may become a scratch on the ridge, resulting in defective side crystals, resulting in a decrease in yield.

An example of the cross-sectional structure of a diagonal integrated circuit is shown in FIG. 1, and as shown below, the dielectric Cefnon integrated circuit has a multilayer structure. On a silicon substrate 1, a ground plane layer 2 of a superconducting thin film, an insulating layer 3, a lower electrode 4 and an upper electrode 5 of the superconducting thin film, Cefnon junctions 6 and 7 of an oxide film barrier, an insulating layer 8, a resistor layer 9, Superconducting thin film Guérande grain contact) A 10° termination electrode 11, a control line insulating layer 12, and a control edge 13 of the superconductor 4# are formed.

In such a multilayer structure of an integrated circuit, the surface is extremely uneven. For this reason, even if 7 layers of Otoresist are applied for buttering a predetermined layer,
As expected, unevenness will occur on the resist surface. Then, when you bring the photomask into contact with the photoresist at your knees, the convex part of the resist will come into close contact with the photomask.When you take the photomask off, the convex part
Otrenost adheres to the 7 otmask and forms part of the 7 otrenost layer, which peels off, and even if it does not peel off, the photorenost surface is scratched.Furthermore, if an I-ji dust resist is used as a photoresist, the resolution Although excellent, their brittleness makes the peeling and scratching described above even more of a problem. Such peeling results in the formation of a conductor layer or insulating layer with a pattern different from the predetermined pattern, resulting in a defective product because the circuit wiring differs from the predetermined one. The gap is shown in Figure 1 and the insulating layer 8 in the following structure is 8.
In the case where the lift-off method is used to form a evaporated film of 10%, to explain it more specifically, first, as shown in FIG.
A layer of photoresist 21 is applied over the formation of the lower electrode 4 and the ground contact IO. Small irregularities occur on the surface of the photoresist layer 21, and the photomask 22 is placed in contact with the renost layer 21 in the round shape for contact exposure.
As a result, the photoresist (21) of the convex portion is tightly adhered as shown in FIG. And 7 oto! 1 after clearing the screen 22
When leaving eLn, -923 of the 7th photoresist layer 21 may be peeled off. When the photorenost layer 21 is developed, the #separated portion 23 also becomes a removed portion of the resist. Next, when 810Jl is formed on the entire surface by vapor deposition, 810Jl is also formed on the exposed portion of the peeled portion 23. . Then, at the same time as removing the photoresist layer 21, the StO vapor deposited layer on it is removed (lifted off) to obtain a SlO insulating layer with a predetermined number of turns, which corresponds to 23 ms of stripping. Unnecessary 810 j[
In this case, the setting area of the Cefnon junction 6 (for one reason) becomes smaller. Therefore, it is no longer possible to obtain a Cefnon junction with predetermined characteristics, and the product is determined to be defective. Therefore, gloximity exposure may be considered as a substitute for contact exposure, but in this case, since there is a distance of several lθ μm between the photomask and the photoresist, the resolution is lower than that of contact exposure, and the precision of microfabrication is also lower.

(3) Purpose of the Invention The purpose of the present invention is to prevent peeling and scratches of photoresist caused by contact exposure of 700% in a process for manufacturing integrated circuits.

Another object of the present invention is to propose a method of manufacturing a non-contact integrated circuit that improves the manufacturing process while performing contact exposure of the photoresist.

(4) Structure of the Invention The purpose of the present invention is to prevent the photorenost coated on the constituent parts of the integrated circuit from coming into contact with the 7-otomask, so that the formation of the integrated circuit on other substrates excluding the area of This is achieved by a method of manufacturing an integrated circuit, which involves forming in advance a convex portion that protrudes higher than the multilayer structure constituting the integrated circuit in the region.

The thickness of the convex portion formed on a substrate such as silicon is 1 to 3 mm.
The area to form p1 in μm should preferably be a scribe area that divides the substrate into two sections of the integrated circuit.In addition, if the chip is large, an island-like area should be formed in a place that does not affect the circuitry within the sections. A convex portion may be formed. The width of the convex part is number 1
It can be appropriately selected in the range of 0 to several 100 μm.

It is preferable that the convex portion is formed on the substrate 4 ahead of the non-integrated circuit structure layer.
N4. Aj20. Alternatively, the metal film may be formed using a lift-off method.Furthermore, the substrate may be selectively etched to leave a portion of the substrate unetched to form a convex portion.

(5) Embodiments of the Invention The present invention will be explained below using preferred embodiments n*iq.

Implementation m * Example 1 Bogi 7 Otrenost was applied on a silicon substrate, which is the substrate of the Noshiryu Funon integrated circuit, exposed with a mask for forming convex portions and a master turn, developed, and then a SlO island coating ( Thickness 1
~3 μm) is formed on the entire surface. At the same time as the photoresist is removed, the SiO film on it is also removed to form a convex area outside the area where the diagonal integrated circuit is to be formed [31 (Fig. 114)].
form. This convex portion 31 is located on the substrate 1 when viewed from a plan view.
The first integrated circuit to be formed is the second one to divide 32! This means that it is formed in the area (Figure 5 of the irises).

The width of the convex portion 310 is several 10 to several 100-.

The function of this convex portion is explained by the insulating layer 8 as shown in FIGS. 2 and 3.
To explain the case of contact exposure of 7-resist to form a photoresist, when the photoresist 41 is applied as shown in Figure #I6, the photoresist portion at the convex portion 31 becomes the highest. For this reason, when the photomask 42 is brought into contact with the photoresist layer 41 for contact exposure, the photoresist portion 43 on the convex portion 31 comes into strong contact with the photomask, but this does not affect the structure of the non-integrated circuit. The photoresist portion 42 does not come into contact with the photomask. Therefore, if the photoresist scratches or scratches occur, the scratches will occur in the photoresist portion 42 on the convex portion 31, and the structure of the dicarbonate integrated circuit. No peeling or scratches will occur in the 7th photoresist on the part up to that point. As a result, the pattern defects caused by conventional photoresist + MdJlIK are eliminated, and 7 photoresist layers with a predetermined pattern can be obtained by development after exposure, and a predetermined insulating layer 8 can be obtained.
t-can be formed. As in the case described above, this convex portion 31 prevents the photoresist from being peeled off or damaged when forming patterns for the lower electrode 4, upper electrode 5, control line 13, etc. and when contact exposing the photoresist. , product yield can be improved.

Ikkan Todoroki 111j Although the convex portion 31 in FIG. 6 is a single unit, the convex portion 551 (FIG. 7) can be formed in the following multilayer structure. First, thick JiHOJ in the formation of a convex part with an embodiment force of 1
Convex base layer 52 with a thickness of about 0.5 JIm, not an i-deposited film
1. Next, when forming the ground plane layer 2t, the first stacked layer 2 is also formed on the convex base layer 52 at the same time.
′ is formed. This can be easily accomplished by modifying the photomask pattern. Similarly, when 4 is formed on the insulating layer 3, the bonding capacitor &11, the resistor layer 9, and the lower noble capacitor 4, the stacked layers 3', 11', 9 are stacked on the right side.
' and 4' are sequentially formed on one stacked layer 2' to constitute the convex portion 51. This convex portion 51 (FIG. 7) is shown in FIG.
This becomes a convex portion when patterning the insulating layer 8 in FIG. 3 and #I6, and the same effect as the first embodiment can be obtained. When the insulating layer 8, the upper electrode 5, and the control line insulating layer 12 are further formed on this convex portion, stacked layers that will constitute the convex portion are similarly formed.

*m a The convex portion can also be formed by selectively etching the silicon substrate of the non-integrated circuit. That is, as shown in FIG. 8, seven photoresist layers 61 having a predetermined pattern are formed on the silicon substrate 1. Then, as shown in FIG.

Next, when the silicon substrate l is etched with an etching solution such as hydrofluoric acid, the photoresist layer 61 acts as a mask and the portion 62 below it remains unetched (FIG. 9).
, this portion 62 is a convex portion when viewed from the whole, and is obtained in a shape pattern similar to the convex portion shown in @4 and fss diagrams. The height of the etching solution (that is, the height of the convex part) is 1~
Taking into account the size of the 7-inch integrated circuit to be formed, the price may be higher than that. After removing the photoresist layer 61, a multilayer structure of a di-1 Cefnon integrated circuit is formed in the recessed portion of the silicon I-board. When forming the multilayer structure, since there is a convex portion 62, the photoresist portion on the convex portion comes into contact with the photomask, and the 7 photoresist groups on the dicarbonate cefnon accumulation (b) path structure contact with the 7 photomask. This prevents any disadvantageous peeling or scratches from occurring on the resist.

The convex portion can be formed by stacking layers in the same manner as in Embodiment 2 by setting the machining depth to about 0.5 μm.

(6) Effects of the Invention As mentioned above, by forming the convex portions in advance outside the area of the integrated circuit, the photorenost layer applied on the integrated circuit component can be easily exposed during contact exposure. Since there is no contact with the photomask, the photoresist can be peeled off and scratches can occur.
Product yield is improved.

Furthermore, the present invention may be applied not only to the manufacture of integrated circuits, but also to the manufacture of integrated circuits containing bipolar transistors or MOB transistors.

[Brief explanation of drawings]

Figure 1 is a schematic cross-sectional view of an integrated circuit, and Figure 2 is a schematic cross-sectional view of the integrated circuit after a photoresist layer is applied during the formation of the integrated circuit. Figure 3 is a schematic cross-sectional view of a non-7 integrated circuit when the photoresist layer shown in Figure 2 is brought into contact with the photoresist layer. FIG. 5 is a cross-sectional view illustrating a state in which a convex portion is formed on a silicon substrate; FIG. 5 is a plan view illustrating a state in which a convex portion is formed on a silicon substrate; FIG. 7 is a schematic cross-sectional view of an integrated enclosure similar to that shown in FIG. 3, which explains the function of the convex portions formed on the substrate. 6 is a partial sectional view of FIG. 6, FIG. 8 is a sectional view illustrating the next state after forming a seven-hole resist pattern on a silicon substrate, and FIG. FIG. 1... Silicon substrate, 2... Ground plane layer,
4... Lower electrode, 5... Upper electrode, 6, 7... Di-Cefnon junction, 8... Insulating layer, 9... Resistor layer,
12... Control line insulating layer, 13... Control line, 21...
・Photoresist layer, 22... Photomask, 23.
... Peeling portion, 31... Convex portion, 41... Photoresist layer, 42... 7 otomask, 43... Photoresist portion in contact with photomask, 51... Convex portion,
62...Protrusion.

Claims (1)

[Claims] 1. In the production of a digital Cefnon integrated circuit, a photoresist is used to form a metal layer or an insulating layer of a predetermined thickness. Pre-form a protruding convex portion on the multilayer structure constituting the non-contact integrated circuit in other areas of the substrate other than the non-integrated circuit formation area to avoid contact. 7 Non-integrated circuit manufacturing method that uses 4I mold.