JPS5814551A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To lessen the interval of wiring and thus make a device highly integrated, by opening a window in an insulation film on a semiconductor substrate, superimposing a conductor and the second insulation film, and removing the conductor by etching by using the third insulation film as a mask. CONSTITUTION:PSG4 having a window 5 is connected to a substrate 2 having a diffusion layer 3, Al 10 is laid thereon, and an insulation film 11 is applied thereon by rotation. Then, the laminate thus prepared is incinerated by plasma, thereby the insulation film 11 is left very thinly in a part other than a concave part, and, with a positive resist mask 12 given, Al 10 is paterned by sputter etching. When the resist 12 and the insulation film 11 are removed. The Al wiring 10 with the window 4 buried entirely is completed. According to this constitution, the increase in the width of wiring in a connection window part is avoided, the window can be buried completely by the wiring even when there exists some slippage in positions of the wiring and connection, and the interval of the wiring can be lessened. Thus, the device can be made highly integrated.

Description

[Detailed description of the invention] A method for manufacturing the 91Ia semiconductor device of the present invention, especially the wiring pattern method Regarding Ichino's formation IP Shibu.

Conventionally, in integrated circuits, when contact is made between a dielectric layer and a diffusion region formed in a base layer, the fk method has been used as in Kugata.

That is, as shown in FIG.
In the area where contact is made with +, increase the width and D
, ``'The alignment margin with the tact window was increased. Figure 1 6) is a cross-sectional view along h-A of the layout @ 1, 2 is the semiconductor substrate, 3 is the diffusion region, 4 is a phosphosilicate glass film.

However, in the conventional hollow wiring, the width is large at the commuting contact part, so the wiring interval with the adjacent wiring @1' occupies a considerable proportion of the wide area). The line width had to be larger than the minimum wiring spacing. This was one of the reasons for the delay in increasing the degree of integration in integrated circuits.

The present invention solves these conventional drawbacks and provides a method for manufacturing wiring that can reliably make contact with the substrate at the wiring contact portion without increasing the width of the wiring.

The features of the present invention include a step of forming a window in a first insulating film deposited on a semiconductor substrate, a step of forming a conductor layer on the window, and a step of forming a conductor layer on the conductor layer. 2, a step of forming a third insulating film on the second insulating film, and a step of removing the dielectric layer by etching using the third insulating film as a mask. There is a particular thing.

Hereinafter, one embodiment of the present invention will be described using the drawings. Second
Figures (a) to (f) are process-order sectional views for explaining an embodiment of the present invention.

As shown in FIG. 2(1k), a diffusion region 3 is formed on the substrate 2, and a phosphosilicate glass film 4 having a contact window 5 is deposited thereon. As shown in FIG. 2(b), a conductive layer 10 made of aluminum or the like is formed thereon, and then methoxy 7 81 (OCHs) a and a 0.5-hydrochloric acid aqueous solution are added on it in a ratio of 1=1. Mix at a ratio of 9 to 10 with methylalpour
500 Or
, p, m rotation speed=-toshi and the insulating film 11 is 50
Forms about 0A. Then, as shown in Figure 2 (6), 0
．． 4 Torr O, Prada! The insulating film 11 is ashed, leaving an extremely thin insulating film 11 in the remaining parts except for the recessed parts. Next, Posilex) 12 (0FPR77-...
(manufactured by Tokyo Ohka Co., Ltd.) is formed thereon and patterned as shown in FIG. 2(d). Next, positive resist 1 with
When sputter etching is performed using a gas diluted with argon (Ar) using PC4 and BO2 using the insulating film 11 as a mask, the conductor 10 is patterned as shown in FIG. Resist 12 and insulating film 1
By removing 1, a conductive layer 10 (wiring) completely filling the contact window 5 is formed as shown in FIG. 2(f). As a result, even if the wiring and contact positions are slightly misaligned, the contact window can be completely tightened without increasing the wiring width at the contact window, making it possible to reduce the wiring spacing. High integration is achieved.

As explained above, according to the present invention, the wiring spacing can be reduced and high integration can be achieved.

[Brief explanation of drawings]

Figure 1 shows conventional wiring, Figure 2 (&) to (f)
1A and 1B are process-order sectional views showing an embodiment of the present invention. 2; semiconductor base edge, 3 phosphosilicate glass film (first insulating film), 5; contact window (window portion), lO; conductor layer, 11
; Insulating film (third insulating film), 12: Positive resist (third
insulation film). i$1 yam 1 mouth

Claims (1)

[Claims] a step of patterning a J13C1 insulating film on the second insulating film; and a step of etching away the conductive layer using a third insulating film as a mask. manufacturing method.