JP2926790B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a wiring structure that is electrically connected to a semiconductor device via a through hole opened in an interlayer insulating layer.

[Conventional technology]

Conventionally, the wiring configuration of this type of semiconductor device has a lower wiring and an upper wiring with an interlayer insulating film interposed therebetween, and has been electrically connected by a through hole opened in the interlayer insulating film. The through hole is opened on the upper surface of the lower wiring, and the exposed upper surface portion is brought into contact with the lower wiring to electrically connect the lower wiring (see FIGS. 7A and 7B).

[Problems to be solved by the invention]

In the above-described conventional semiconductor device, as the degree of integration increases and as miniaturization progresses, the wiring interval and the wiring width also become narrower. Therefore, the opening area of the through hole is gradually reduced, and at the same time, the connection area between the lower wiring and the upper wiring is also reduced. Therefore, the electric resistance of the through-hole was increased. FIG. 4 is a graph showing the relationship between the opening area of the through hole and the electric resistance. This bluff is
The electric resistance measured by connecting 1000 through holes in series is shown. The solid line in this graph is a conventional example, and it can be seen that the electric resistance sharply increases as the opening area of the through hole decreases. The reason is considered to be a natural oxide film formed on the lower wiring surface. This oxide film has a thickness of several tens to several tens of millimeters, and can be easily broken by heat treatment (about 400 ° C.) after connecting the lower layer wiring and the upper layer wiring or a pretreatment for forming the upper layer wiring by a through hole. it can. Therefore, the contact area between the lower wiring and the upper wiring is always smaller than the opening area of the through hole. If the size that can break the oxide film is uniform and the density is constant, as the opening area of the through hole is reduced, the contact area is sharply reduced, and the electric resistance of the through hole is greatly increased. .

When the electric resistance of the through hole increases, the characteristics of the semiconductor device are deteriorated, and the yield is lowered due to the deviation from the standard. For example, the low level of the output of one circuit rises due to the increase in resistance, and the high level
It may cause a malfunction due to the sense of the level, or may slow down the switching speed because the time constant, which is the product of the wiring capacitance and the electric resistance, increases. As described above, as the miniaturization progresses and the through-hole opening area decreases, there is a disadvantage that the electric resistance increases and the characteristics and the yield of the semiconductor device decrease.

[Means for solving the problem]

A semiconductor device according to the present invention includes a lower wiring provided on a semiconductor substrate, a lower interlayer insulating film provided on the semiconductor substrate and partially covering a side surface of the lower wiring, and an upper interlayer covering the lower interlayer insulating film. An insulating film, a through hole provided in the upper interlayer insulating film to expose the upper surface of the lower wiring and the remaining part of the side surface, and the upper surface of the lower wiring via the through hole covering the upper interlayer insulating film. And an upper layer wiring in contact with the remaining portion of the side surface.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1A is a plan view of a first embodiment of the present invention, and FIG.
FIG. 1B is a sectional view taken along line XX ′ of FIG. 1A.

In the figure, 1 is a lower interlayer insulating film, 2 is a lower wiring, 3 is a stopper insulating film, 4 is an upper interlayer insulating film, 5 is a through hole, and 6 is an upper wiring.

In this embodiment, the through hole is made larger than the width of the lower wiring, and the side surface of the lower wiring is used as a connection surface in the same manner as the surface. This way,
If the contact area with the upper layer wiring increases, the natural oxide film formed on the lower layer wiring surface is broken by heat treatment etc., and if the density and size of contact with the upper layer wiring are fixed, the opening area is reduced. Also, the contact area is not so small due to the side contact surface, and therefore, the electric resistance is hardly increased. FIG. 4 shows the relationship between the opening area of the through hole and the electric resistance. In this figure, the through-hole opening area of the present invention represents the surface area of the lower wiring. As can be seen from this figure, in the conventional example, the through-hole resistance sharply increases at the same time as the through-hole opening area is reduced, whereas in the present invention it does not increase so much.

Next, an example of the present invention is shown in FIGS. 2 (a) to (k). FIG. 2 (a) shows that after forming a desired diffusion layer in a semiconductor substrate, a lower interlayer insulating film 1 is formed, and a material (for example, photoresist) which can be easily peeled off is formed in a portion to be a lower layer wiring.
Is deposited and then patterned. 2 (b), the lower interlayer insulating film 1 is etched using the release material as a mask. In this case, a film such as a nitride film, an oxide film, or polyimide TEOS is used for the lower interlayer insulating film, and a reactive ion etch or the like is used for etching. FIG. 2 (c) deposits a wiring material using a sputtering method. As the wiring material, copper, aluminum containing copper, aluminum containing Si, aluminum, or the like is used. FIG. 2 (d) shows the removal of the release material and the wiring material deposited on the release material by a lift-off method to form the lower wiring 2. FIG. 2E deposits a stopper insulating film 3. If a polyimide resin is used for the lower interlayer insulating film 1, this material uses CVD or a plasma oxide film or a nitride film.
FIG. 2F deposits an upper interlayer insulating film 4. This material uses, for example, a nitride film, an oxide film, polyimide, TEOS, or the like. FIG. 2 (g) is a diagram in which a photoresist 12 is applied to form an opening, and FIG. 2 (h) is used as a mask to form an opening window of a through hole in the upper interlayer insulating film 4.
For example, a polyimide resin is used for the upper interlayer insulating film 4 and the lower interlayer insulating film 1, and a plasma nitride film is used for the stopper insulating film. Although the upper interlayer insulating film 4 is dry-etched, a portion having no lower-layer wiring is formed of a plasma nitride film as a stopper insulating film, so that a deep groove is not formed due to excessive etching. FIG. 2 (i) is a diagram in which the stopper insulating film is removed using the upper interlayer insulating film as a mask, the natural oxide film on the lower wiring is removed with a thin HF-based solution, and at the same time the corners are rounded. In FIG. 2 (j), after an upper wiring layer is deposited thereon, it is patterned to form an upper wiring 6. Here, the reason for using the stopper insulating film is that the lower and upper insulating films are made of a polyimide resin having a low relative dielectric constant in order to improve the switching speed (for example, the relative dielectric constant is polyimide 3.5, SiO ₂ 3.8, Si ₃ N ₄ 7 ). For example, as shown in FIG. 2 (k), a lower insulating film can be used also as a stopper insulating film by using a plasma nitride film as a lower insulating film and a plasma oxide film as an upper insulating film. By doing so, the contact area with the upper layer wiring increases by the side surface of the lower layer wiring, and the through-hole resistance does not increase so much. For example, comparing the contact areas of the through holes in FIGS. 1 and 6, in the conventional FIG. 6, the width of the through hole must be smaller than the width of the lower wiring. When the lower layer wiring width is 3 μm, the width of the through hole is 1.5 μm. If the length in the length direction of the lower wiring is 2 μm, the contact area with the upper wiring is 1.5 μm × 2 μm = 3 μm ² .
On the other hand, in the example of the present invention, when the depth at which the side surface of the lower wiring is exposed is 0.5 μm, the contact area with the upper wiring is {3 μm (upper surface) +0.5 μm × 2 (side surface)} × 2 μm.
m = 8 μm ² , which greatly increases.

3 (a) to 3 (i) are process sectional views showing another example of the manufacturing method of the present invention. In this example, the case where the width of the lower layer wiring is further reduced and a through hole cannot be opened on the lower layer wiring is shown. 3 (a) to 3 (d) are the same as those in FIGS. 2 (a) to 2 (d). FIG. 3 (e)
Then, the upper insulating film 4 is deposited. This material is the same as in FIG. FIG. 3 (f) is a view in which a photoresist is applied and opened, and a part of the through hole is outside the upper surface of the lower wiring. FIG. 3 (g) shows the photoresist 12
Using the mask as a mask, the upper insulating film and the lower insulating film are removed by etching to expose the upper surface and side surfaces of the lower wiring. Next, as shown in FIG. 3 (h), an upper wiring material is deposited. In this case, for example, when aluminum is deposited by a sputtering method, an opening of a through hole is formed as shown in FIG.
A shape with poor step coverage like FIG. 3 (i) irradiates this with an excimer laser beam to temporarily melt and flatten the aluminum film. Aluminum exhibits a high absorption coefficient (〜1.3 × 10 ⁶ cm ⁻¹ ) with respect to ArF excimer laser light (193 nm). For this reason, about 70% of the light incident on the aluminum is absorbed in a layer as shallow as 10 nm below the surface, melts and is flattened by viscous flow (Semiconductor World 1988 November 83 p. 83). Thereafter, this film is patterned to form the upper wiring 6.
By doing so, even if the side surface area increases by the thickness of the lower wiring and the width of the lower wiring further narrows, the area in contact with the upper wiring increases and the resistance of the through hole does not increase so much. For example, the width of the lower wiring is 1.5 μm and the film thickness is 2 μm, and the length of the through hole in the wiring direction is 1.5 μm.
Then, the contact area with the upper wiring is 1.0 × 1.5 in the conventional structure in which a through hole is formed on the surface of the lower wiring when the length of the through hole in the width direction of the lower wiring is 1.0 μm.
μm ² = 1.5 μm ² . On the other hand, in the example of the present invention, {1.0 (upper surface) +1.5 (side surface)} × 1.5 μm ² = 3.75 μm ² , which is a large increase. FIGS. 5A to 5E are plan views of the second, third, fourth, and fifth embodiments of the present invention, respectively. FIG. 5 (a) shows a case where the present invention is applied to a terminal of a lower layer wiring. FIG. 5 (b) shows a case where the invention is applied to a corner where the lower wiring is broken. FIG. 5C shows the case where the upper layer wiring is parallel to the lower layer wiring. FIG. 5D shows a case where the lower layer wiring is dented in a concave shape to increase the side wall area of the lower layer wiring. FIGS. 6 (a) and 6 (b) show the second embodiment of the present invention.
6 is a plan view of a seventh actual finger example. This is a case where the step 8 is provided and the side wall area is increased by lowering the lower wiring in the vertical direction. In particular, FIG. 6 (b) shows the case where the side wall area is increased by providing many small depressions inside the lower wiring. This depression can be formed by dry etching or wet etching by patterning with photoresist. By doing so, the through-hole resistance becomes
It decreases significantly. FIG. 6 (c) is a view of Z- in FIG. 6 (b).
It is Z 'line sectional drawing.

〔The invention's effect〕

As described above, the present invention reduces the contact area between the lower layer wiring and the upper layer wiring because the upper surface and the side surfaces of the lower layer wiring are in contact with the upper layer wiring even when the miniaturization advances and the wiring width becomes narrower. Therefore, a structure in which the through-hole resistance hardly increases is obtained. Therefore, the semiconductor device can be miniaturized without a delay in switching speed of the semiconductor device or a malfunction, and without a decrease in yield due to a deviation from the standard.

[Brief description of the drawings]

1A and 1B are a plan view and a sectional view, respectively, of a first embodiment of a semiconductor device according to the present invention, and FIGS. 2A to 2K show an example of a manufacturing method according to the present invention. Sectional view, third
FIG. 4 is a cross-sectional view showing another example of the manufacturing method of the present invention, FIG. 4 is a correlation diagram between the opening area of the through hole and the through hole resistance,
FIGS. 5 (a) to 5 (d) show the second, third and third embodiments of the present invention, respectively.
4, plan views of the fifth embodiment, FIGS. 6 (a) and 6 (b) are plan views of the sixth and seventh embodiments of the semiconductor device of the present invention, respectively.
FIG. 6C is a sectional view taken along the line ZZ ′ of FIG.
1A and 1B are a plan view and a sectional view of a conventional semiconductor device. DESCRIPTION OF SYMBOLS 1 ... Lower interlayer insulating film, 2 ... Lower wiring, 3 ... Stopper insulating film, 4 ... Upper interlayer insulating film, 5 ... Through hole, 6 ... Upper wiring, 7 ... Interlayer insulating film, 8 ... …Step,
11 ... release material, 12 ... photoresist.

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] A lower wiring provided on the semiconductor substrate; a lower interlayer insulating film provided on the semiconductor substrate and covering a part of a side surface of the lower wiring; and an upper interlayer insulating film covering the lower interlayer insulating film. A through hole provided in the upper interlayer insulating film to expose an upper surface of the lower wiring and a remaining portion of the side surface; and the upper surface of the lower wiring via the through hole covering the upper interlayer insulating film and the through hole. A semiconductor device comprising: an upper wiring in contact with the remaining portion of the side surface. 2. The semiconductor device according to claim 1, wherein a stopper insulating film is interposed between said lower interlayer insulating film and said upper interlayer insulating film.