JPS58142446A - Data processor - Google Patents

Abstract

PURPOSE:To attain high speed data processing, by summing the content of a register selected at the 1st and 2nd address modification designating sections and avoiding the next step from being starting in using the result as an operand address. CONSTITUTION:In the internal designation of an index register group 301 and a base register group 302, a desired content is read out from each register by the address designation with X and B parts of an instruction word. The base register modification only is designated at the part B, and in the operation of address production when the part A is ''0'', the selected base register information is outputted to a bus 421 via a gate 412 and a displacement section 303 is outputted to a bus 422 via a gate 413. This address is taken as the final address and the next step is omitted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to address generation for a data processing device.

[Technical Background of the Invention] When data processing equipment executes an instruction, operands of () are often included in main memory.

The address (address in virtual memory in a virtual memory system) generation information in the main memory is generally given to the instruction ah. FIG. 1 shows the structure of a conventional command word. Part 01 is the operation code part and is executed.

Specify the contents of the command to be executed. The R1 section specifies a register that holds the first operand related to the actual instruction. The units X, B, and D are involved in the execution of instructions. This is the part that provides the information that creates and addresses the node in main memory that contains the second operand. The 7-data processor has a group of base registers and a group of registers called group index registers, which are used for address generation.

The X part of the instruction word is 1 when its pit content is not zero.
one index register is selected, and the contents of the selected index register are used for address generation. Similarly, part 8 of the instruction word selects one base register when its pit contents are non-zero, and the contents of the selected base register are used for address generation. In other data processing devices, both the B section and the X section may select registers from a group of general-purpose registers and use them as base registers and index registers. Part D is a displacement part, and the contents given there are directly used for address generation.

Figure 12 is a conceptual diagram of address generation, where both the base register and index register are 24 bits, D
It is assumed that s is 12 pits. Assuming zeros in the high order of part D, each selected base register and index
Obtain the address of the register and the 24-bit operand in the D section. (Carries are ignored.) If the X part or the B part is zero, the index register or base register is not used, and O is equivalently added. In a data processing device with such an address generation method, in order to realize address generation,
There are two main theories that can be considered. The first method is
The method has a three-man adder that adds the contents of the index register, the contents of the base register, and the displacement i.D.PA in one step. Then, the second method uses a two-man adder in two steps to first add the first
In the step , two partial sums of the three bottoms are taken, and in the second step, the remaining data 302 in the partial sum are the index register group and the base register group, respectively. The internal designation of each register group is addressed by the X and B parts of the instruction word, so that desired contents are read from each register. 323 is an adder, and 321 is one input bus of the adder 323. When the gate 311 provided between the index register M301 and the bus 321 is opened, the contents of the selected index register are read, and the gate 312 provided between the base register group 302 and the bus 301 is opened. The contents of the selected base register are output onto bus 321. It is assumed that when both gates 311 and 312 are closed, the data supplied from bus 321 to adder 323 is zero. Bus 322 is the other input bus of add@323. This bus 322 has registers.
303.304 are connected through gates 313.314.

The conventional operation of the above configuration will be explained. In the first step of address generation, gates 312 and 313 are Mll. First, the gate 313 is opened and the register 30 holding the disboostment section is transferred to the lower 12 pits of the bus 322.
3 information is provided. At this time, the upper 12 bits of the bus 322 are assumed to be "OI". The -h gate 312 opens when the B part of the instruction word is not "0", selects the B part as an address, and supplies the base register information read from the IJ base register group 302 to the bus 321. When part B is 0°', the gate 312 remains closed and the information on the bus 32↑ becomes O. Adder 323 adds the information input from buses 321 and 322, and the resulting partial sum of the displacement part and base register is held in register 304 via data line 324.

On the same side, the X part of the instruction word is tested. If the X department “
0°', that is, if the index register l1ts is not designated, the partial sum obtained in the first step is used as the generated operand address, and the address generation operation ends. If xsI is not 0'', a second step of address generation is activated. In this second step, gates 314 and 311 are opened. .

The index register group 3 is supplied to the rebus 322, the gate 311 is opened, and the X part is selected as 7 addresses.
The index register information read from 01 is
It is supplied to bus 321. The adder 323 is connected to the bus 321
．． 322 and its output 324 becomes the final operand address generated.

[Problem 1 in the background art: By the way, such addressing method is limited to 7 in the array.
Effectively used for dressing etc. That is, an element of the array is accessed by storing the start address of the array in the base register and storing an offset value from the start in the index register.

In such a case, especially when the bit length of the displacement section is small, the displacement section often has a value of 0°' and addressing is performed using a base register and an index register.

In this case, in the conventional method described above, there are base register modifications and index register modifications, so there are always two
The drawback is that one address is created through two steps.

[Objective and Summary of the Invention] The present invention has been made in view of the above-mentioned drawbacks. When both base register and index register modifications are specified, if the displacement part is ``0°'', the first It is an object of the present invention to provide a data processing device in which, in step 1, a partial sum is created based on the contents of an index register and a base register, and this partial sum can be used as a final address.

[Embodiments of the invention] The present invention will be explained below with reference to the drawings.

FIG. 4 is a 70 block diagram showing the configuration of an embodiment of the present invention. In FIG. 4, the same parts as in FIG. 3 are given the same reference numerals, and their explanation will be omitted. Bus 420: Gate 411
, 412, information is output from the index register group 301 and the base register group 302. Bus 422 has game i-413, 414, 4
15, displacement units 303,
Information from register 304 and base register group 302 is output. 430 is the displacement section 3
03 is a zero detector to determine whether or not it is zero.

Next, the present invention will be explained in detail.

In FIG. 4, when only the base register modification is designated by part B and part X is OII, the address generation operation is performed in exactly the same way as shown in FIG.

That is, in the first step of address generation, the selected base register information is output to the bus 421 via the gate 412, and the displacement section 303 outputs the selected base register information to the bus 422 via the gate 413. The address generated in the first step becomes the final address, and the second step is omitted. cTable 1...(2)
] Table 1 below shows the gate numbers opened to buses 421, 422 in the first step and second step in various cases.

Margin below Table 1 ((1), none of the gates open.

(X2), the second step is not activated.

(13>, don't care, then the command word X
The operation will be explained in the case where both the part and the 8th part are not zero, that is, both the index register modification and the base register modification are specified.

In this case, the result of zero detector 430 is tested. If the displacement part is 0'', as shown in case (4) of Table 1, in the first step, the gate 4
11 and 415 are opened, the adder 323 adds the index register information and the base register information, and since this becomes the final address, the second step is controlled not to be activated. If the displacement part is not "OII", the gates 411 and 413 are opened in the first step as shown in case (5) of Table 1,
An adder 323 adds the index register information and displacement information, and inputs the sum to the register 304. Next, in a second step, gates 412 and 41
4 is opened, the partial sum in register 304 and base register information are added by adder 323, and the final address is obtained.

In this way, by providing a means for supplying the zero detection circuit for the displacement part and the base register to the bus 422, the final address can be determined only in the first step in all cases except for case (5) in Table 1. It becomes possible to generate. This example - (I'', the output of the base register is 2
Although the description has been made so that the sums are output to two adders Panonova 421 and 422, other combinations of additions are also possible.

[Effect of the invention] As is clear from the above explanation, according to the present invention, the conventional 2
Addresses used to be generated by step tightening processing, but except for case (5) in the table, addresses can now be generated in one step in all cases, which has the excellent effect of speeding up data processing. .

[Brief explanation of the drawing]

Figure 1 is a diagram showing the structure of a general instruction word, Figure 2 is a diagram showing an overview of conventional address generation, Figure 3 is a block diagram showing the configuration of a conventional address generation circuit, and Figure 4 is a diagram showing the configuration of a conventional address generation circuit. Applied to data processing 4A of the present invention, 1301... Index register group 302.
...Base register group 303,304...
...Register 411.415...Gate 421.422...Bus 323...Adder (7317) Representative patent attorney Norichika Kensuke (Gyoh% 1 person) )Figure 1Figure 2

Claims (1)

[Claims] The operand part of the instruction word has two register modification specification parts and a displacement part, and -2 is obtained from the first and second register groups based on the information in the first and second register modification specification parts. In a data processing device that generates an operand address by a two-step operation using three pieces of information: one address modification information and the value of the displacement part using a two-man power adder, the displacement part of the instruction word is zero. and the first and second address modification specifying sections specify address modification, and if a zero in the displacement section is detected in the first stage of zero detection, the operand means for controlling the contents of the registers respectively selected by the first and second address modification specification parts in the first step of address generation; 1. A data processing device comprising: a control means for preventing activation of the data processing apparatus.