JPS6313212B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram controller;
In particular, the present invention relates to a microprogram control device that employs pipeline processing to facilitate control.

In a conventional microprogram control device, each stage of processing such as data input, arithmetic processing, and storage is performed under the control of a single control storage device. In this case, the single control storage device described above must monitor and control all processing stages, so in order to precisely control each stage, the number of bits of the instruction input to the control storage device must be increased. The problem is that the control storage device has to be large-scale and expensive in order to accommodate instructions of this huge number of bits. Also, since it is a single control memory, while controlling one stage it cannot control the other stages, and therefore all of the bits that make up the word included in the instruction cannot be used at the same time. The problem is that the bits become useless information at that point.

In view of the above-mentioned problems in the prior art, an object of the present invention is to control each stage of processing such as data input, arithmetic processing, and storage in a pipeline manner using individual control storage devices. To reduce the storage capacity of each of a plurality of control storage devices included in a plurality of control devices included in a microprogram control device, thereby lowering the price of the microprogram control device and making effective use of input bit information. It is in.

In order to achieve the above object, the present invention includes N control storage devices provided corresponding to each of N stages (N is an integer of 2 or more) of processing steps included in pipeline processing. However, the address of the first-stage control storage device of the N-stage control storage device is determined by an externally input instruction or the contents read from the first control storage device, and hereinafter, the address of the second-stage control storage device There is provided a microprogram control device characterized in that the addresses of the control storage devices in the first to Nth stages are determined by the contents read by at least the preceding control storage device of each control storage device.

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a microprogram control device according to the present invention will be described below with reference to the accompanying drawings.
The accompanying drawing is a block diagram showing one embodiment of a microprogram control device that performs three-step processing: data input, addition, and output of the addition result. In the figure, a first control storage device 10 controls a data input processing section 11, a second control storage device 20 controls an arithmetic processing section 21, and a third control storage device controls a calculation result output section 31. control. 1st
The address of the instruction in the control storage device 10 is determined by selecting an address specified from the outside and an address read from the first control storage device in the address selection circuit 12, and inputting the selected address to the first address register 13. , is designated by the address output from the first address register 13. Instructions output from the first control device 10 are stored in the first instruction register 14. Further, address data output from the first control device 10 is input to the address selection circuit 12 and also input to the second address register 22.

An instruction is output from the second control storage device 20 based on address data from the second address register 22 and stored in the second instruction register 23, and address data is output and stored in the third address register 32. is stored in

An instruction is output from the third control storage device 30 based on the address data from the third address register 32 and stored in the third instruction register 35.

According to the command output from the first instruction register 14, data is input to the data input section 11 via the input gate circuit 15, and the addend data is sent to the digit matching circuit 16, and the summand data is sent to the digit matching circuit 17. are input, the exponent parts are matched, and then stored in data registers 18 and 19, respectively.

According to the instruction output from the second instruction register 23, the data from the data registers 18 and 19 is sent to an adder (carry proper adder).
25 and are added, and the result of this addition is stored in register 26.

According to the command output from the third command register 35, the data of the operation result stored in the register 26 is input to the post-shifter 33, normalized, and stored in the result register 34, and then output.

In this way, since the data input processing section 11, arithmetic processing section 21 and output section 31 are controlled by separate control storage devices, each control storage device only needs to control one processing stage, and therefore the storage The capacity can be small and the control can be simplified.

In the above-described embodiment, the number of processing stages is three, but the present invention is not limited to this, and the number of processing stages may be set to two or more as necessary.
Further, the calculation is not limited to addition, but can also be applied to subtraction, multiplication, and division as long as it is a vector calculation.

As is clear from the above description, according to the present invention, since the control storage device only needs to control one processing stage, the storage capacity of the control storage device can be small, and therefore the cost of the microprogram control device can be reduced. is reduced. Furthermore, since each stage can be controlled independently, the storage capacity of each control storage device is not wasted.

[Brief explanation of the drawing]

The accompanying drawing is a block diagram showing one embodiment of a microprogram control device according to the present invention. DESCRIPTION OF SYMBOLS 10... First control storage device, 11... Data input processing unit, 12... Address selection circuit, 13... First address register, 14... First instruction register,
DESCRIPTION OF SYMBOLS 15... Input gate circuit, 16, 17... Digit circuit, 18, 19... Gator register, 20... Second control storage device, 21... Arithmetic processing unit, 22... Second address register, 23... Second instruction register,
25... Adder, 26... Register, 30... Third control storage device, 31... Data output section, 32... Third address register, 33... Post shifter, 34...
Result register, 35...Third instruction register.

Claims (1)

[Claims] 1 Equipped with N control storage devices provided corresponding to each of N stages (N is an integer of 2 or more) included in the pipeline processing, and controlling the first stage of the N control storage devices. The address of the storage device is determined by an instruction input from the outside or the contents read from the first control storage device.Hereinafter, the addresses of the second to Nth control storage devices are determined by the instructions input from the outside or the contents read from the first control storage device. A microprogram control device characterized in that the control storage device is determined based on contents read out by at least a preceding control storage device.