JPS58130554A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a low resistance part or a high resistance part to the titled device, by providing an energy beam reflecting mask on a poly Si pattern, irradiating the beam, and activating ion implanted impurities. CONSTITUTION:An FET is formed by a conventional method. By a high resistance poly Si layer 12, a poly Si gate 61 and a poly Si wiring 62 on a field oxide film 3 are connected. Then, an Al mask 21 is provided, P ions are implanted in the layer 12, the entire surface is irradiated by a laser beam, and the P ions are activated. The laser beam is reflected by the Al, and the implanted part of P is selectively heated. The gate electrode 61 and a high resistance layer 221 are not heated at all. Therefore, the low resistance part is not formed by the infiltration of P into the electrode 61 and the layer 221, and a wiring 22 having load resistance 221 as designed and a low resistance part 222 for a VDD wire is obtained. It is effective when P, As, and B are used for obtaining the low resistance and N, O, and Ar are used for obtaining the high resistance.

Description

[Detailed Description of the Invention] [Technical Background of the Invention and One Point Between] In recent years, with the increasing density and high performance of semiconductor devices, technology using polycrystalline silicon as a load resistor has become popular. #5 has been done. Such a semiconductor device replaces the conventional memory cell (6 transistors) with 4 transistors + 2 transistors.
It is used as a load resistance, and since the bulk load resistance is slowed down by providing it on the transistor through an insulating film, it is 4 in terms of N.
The biggest advantage of this technology is that it reduces the area of the transistor by changing its structure.
There is a method used in the word twin mode (v, I) to significantly shorten the access time of the memory.
) to (f).

(1) After forming a field oxidation film 1 having a p+ inversion prevention region 1 at the bottom of a P-type silicon substrate JK by iR oxidation method, the field oxide film 1 is formed into a w5ft'L cross-shaped substrate 1 surface. On the other hand, a thermal oxidation treatment is applied to grow a gorge film 4 which will become an enemy line (r-), and a polycrystalline silicon layer 5 is further deposited, and for example, phosphorus is thermally diffused into the polycrystalline silicon P-5 (M
(a) shown).

ω) Next, photo-etch the polycrystalline silicon NIIjff
Turning from 1K/middle to the dirt electrode 61 and, for example, v
, D line charter-6m is formed, and the oxide film 4 is selectively etched using this electrode-1 as a mask to form r-) oxide 8F, and then f-1 electrode-1 and field oxide jlJ
As a k-mask, a + type source and drain region 8.9 was formed by thermally diffusing a droplet onto the exposed substrate 1 (see Fig. 1(b)).
).

(iM) Next iteration, CVD-8iO□Ill all over
JOtJll, r-meter electrode 61 and wiring 4N) 6
1 on the first CVL)-8102M JO by photolithography yc and opening part Jc.

After forming Il, an undoped polycrystalline silicon layer is deposited on the entire surface, and then it is connected to the P-metal electrode 61 and the wiring 6s through the opening JJIIJJI to form a nine-high resistance. polycrystalline silicon/4 turns 12
9 (shown in Figure 1 (C) 1).

(N) Rite, #2 OCVD-1110 on the entire surface
Deposit 2 films 11 and 9% vDD line wiring wiring 6 connections K
Connect high resistance polycrystalline silicon/200th on turn J1
The VD-19102 film J1 is selectively removed and exposed by photolithography, and then phosphorus is selectively diffused into the high resistance polycrystalline silicon/conductor J1 by, for example, poct diffusion, to form a low resistance film. Part 14 and resistance part 14#'
A polycrystalline silicon wiring 14 having a
d) As shown in the diagram), the low resistance section 14 is the vDD line arrangement.
The high resistance part 14 is used as a load resistance.

(V) Then, the entire surface was coated with the second so cvn-sio,
After depositing 1j, the part corresponding to the opening JJ, negative #k t7L J 4 s O#l WT OC
VD-810□1114 J J.

A contact hole J61+16g is opened in 1j, and ? The first to I corresponding to the source and drain regions 8 and 9 of the type
A 3 (D CVD1iO□rl+ J O, J J
.

Sixteen contact holes (the source contact hole is not shown) were opened across the semiconductor.

Next, 3rd OCVD-810□MJ5 After vacuum-depositing 4CAL Ml on the entire surface and butter-coating it to form AA patterns @77 to J9, phosphor-added glass (pea) was applied to the entire surface. A semiconductor device was manufactured by depositing Shirin 20 (as shown in Figure 1).However,
According to the above-mentioned conventional method), there are nine semiconductor devices obtained.
As shown in the first evil (・), and-! Since the load resistor 141 made of polycrystalline silicon is in contact with the dirt electrode 6 made of polycrystalline silicon containing a high concentration of v4 (or arsenic) in the lower layer via the opening JJ, rely'-)
Impurities in the electrode pass through its contact surface to the load resistance 141.
spread to. Historically, the low resistance section 74 for the vDD line. The second OCVD-810 diffusion mask is also used during phosphorus diffusion during formation.
Lateral diffusion occurs from the boundary of the membrane 11 to the load resistor 141. As a result, the load resistor 741 does not achieve the high resistance of the designed value and does not achieve sufficient performance.In particular, when the load resistor 1
Since the diffusion rate of impurities in the polycrystalline silicon constituting 41 is about one order of magnitude higher than that in single crystal silicon, the high resistance region of the load resistance is substantially reduced or reduced due to the diffusion of phosphorus from both sides. The lower r-
) The impurity in the electrode 141 is phosphorus, and if heat treatment at 1000°C is performed for 60 minutes after forming the load resistor 1, more than 15 JIm of phosphorus will enter the load resistor 141 and cause defects. In most high-density devices that use crystalline silicon as a load resistance, the load resistance O1k is 10 μm or less, and considering that the higher the density, the longer the length becomes. There's a problem.

For this reason, it is conceivable to use arsenic with small diffusion ridges as an impurity, but it is not possible to avoid the above-mentioned defects due to large or small ridges.

Furthermore, although it is effective to keep the heat treatment mass temperature low after the formation of the load resistor, it has a negative effect on the performance of the device and does not lead to inherent instability within the solution.

[Purpose of the invention]

9 semiconductor device 0I equipped with a polycrystalline silicon wiring having resistance heat and a low resistance part to serve as a load resistance through the design value of the present invention line.
lli construction method.

[#i praise of invention]

In the present invention, a mask material that reflects an energy beam is selectively formed on four turns of low-resistance polycrystalline silicon, and one impurity is selectively ion-implanted into a skeleton polycrystalline silicon pattern using this mask material. By irradiating the energy beam and activating the ion-implanted impurities into the mask material with a dragon luer alignment, there is no lateral diffusion of impurities and a high resistance part with a negative # resistance exceeding the design value is created. The goal is to obtain a semiconductor device having a polycrystalline silicon layer that forms a low-resistance portion.

Examples of mask materials used in the above method include Aj,
Examples include No.W + Ts.

Among the impurities used in the above method, examples of rounding impurities for lowering resistance include phosphorus, arsenic, etc., and impurities for increasing resistance such as nitrogen, oxygen, and argon cicada. Examples of the energy beam used in this method include a Lede beam, an electron beam, and an ion beam.

[Embodiments of the invention]

Example 1 Process 1iK-9 similar to the conventional methods (1) to (1) described above.
A high-resistance polycrystalline silicone/teitan J1 was formed (as shown in FIG. 2(a)).

Then, a 2 am (D Al(Nicum film II) film was applied to the entire surface.
After evaporation, the Al1=U film IJ on the portion where the low resistance portion was to be formed was selectively removed. Next, aluminum @1
Example of polycrystalline silicon exposed using 1 as a mask I-7
3 to accelerate phosphorus at voltage 109 K@V, F”-sd
Ion implantation with 4k14 of i 3 X l O/c-. After that, ions are implanted by irradiating the entire surface with, for example, an extreme Radhe beam to activate the polycrystalline silicon layer #2 having a low resistance part 22 and a high resistance part XZ.
At this time, the energy and irradiation time of the radar beam were sufficiently controlled so as not to apply heat to the resistor (load resistor) 121.

Next, after removing the Al 1 = U film 2, the film was deposited using CVD-810, the contact hole was opened, the AA wiring was formed, and the maintenance was performed using the same method as described above. −
After going through Oboro no Hikari & Co., Ltd., he manufactured the Chihiro Body Equipment Tube.

According to the present invention, ff1f phosphorus is introduced into the polycrystalline silicon pattern J2tlL by ion implantation means. It's cloudy. In addition, by using -C as an aluminum-21F mask material that reflects the Laser beam, it is possible to selectively anneal the phosphorus implanted area with the Laser beam and heat only the implanted area locally.
Moreover, the high resistance part of polycrystalline silicon that contacts the dirt electrode 61 made of polycrystalline silicon with low resistance [h4 The round shape that is not heated at all, from the skeleton electrode-1] Impurities can be prevented from diffusing into the high resistance portion 111. In addition, it is possible to prevent the resistance of the load resistance from becoming low due to the oozing of phosphorus due to the heat cycle, which was a problem with the conventional method, and it is possible to prevent the resistance of the load resistance from decreasing due to the oozing of phosphorus due to the heat sink, which was a problem with the conventional method.
A polycrystalline silicon wiring 1j having a low resistance portion 21 for the D line is formed.

Example 2 J) K arsenic was ion-implanted in place of the phosphorus used in Example 1 at an acceleration voltage of 40@V at a l/-1 amount of 4 x 10"/-0*, and then a semiconductor was prepared using the same process 1. 9. Manufacture the device.

In Example 2, arsenic having a small diffusion coefficient was used as an impurity, and nine semiconductors were obtained, including polycrystalline silicon wiring in which a load resistance was formed with good reproducibility.

III/A Example 3 The high resistance polycrystalline silicon pattern of Example 1 was replaced with phosphorus! 4 turns of low-resistance polycrystalline silicon were formed, and an aluminum film was deposited on the entire surface. After that, the aluminum film was selectively removed on the planned high-resistance portion. Next, the aluminum film was masked. As a low resistance polycrystalline silicon Δtar yK nitrogen at an accelerating voltage of 100 V, P-ze amount 3
Ion implantation was performed under the condition of

According to Example 3, there is no reduction in the load resistance due to oozing of O phosphorus in the polycrystalline silicon/container, and the resistance is increased by the cutter annealing, so that nitrogen is uniformly distributed.
Since the dale size of polycrystalline silicon can also be controlled, a polycrystalline silicon wiring having a load resistor with a desired resistance value and a low resistance portion can be formed.

〔Effect of the invention〕

As described in detail above, according to Kuyoku Ippon #14, the high resistance part and the low resistance part are made with high dimensional precision, and the resistance value of the high resistance part is also precisely controlled to form a 9 polycrystalline silicon wiring. Well, the improvement of device yield and 1IIIil! It is important to provide a method for manufacturing semiconductor devices that can be

[Brief explanation of drawings]

Fig. 1 (1) to (•) are cross-sectional views showing the manufacturing process of a semiconductor device according to the conventional method, and Fig. 2 (a) and 2) are part of the manufacturing process of the semiconductor device in the embodiment IK of the present invention. FIG. J...pail silicon substrate, 1...feel)'
ml exhibition, 6! ... r-) electrode, σ-electrode, v0 twin wiring, r... r-1 oxide film, 8... y-black region, 9... train region, J O, J J, JJ
・CVD-8103 edition, 11...High resistance polycrystalline silicon pattern, 17-1g...Mu4 arrangement 1, JJ-
・Alkenium exhibition (mask material), 22. ...High resistance part, XS, ...Low resistance part, 22...Polycrystalline silicon distribution p.

Claims (1)

[Claims] 1. Polycrystalline silicon interconnection W forming a high-resistance part and a low-resistance part
In the manufacture of semiconductor devices equipped with I, high resistance or #
a step of selectively forming a T-spout material that reflects the energy beam on the multi-connected iV reconno mother turn of the fiti resistor;
This process involves selectively ion-implanting impurities into polycrystalline silicon using a grade mask material, and irradiating the entire surface with an energy beam to activate the ion-implanted impurities. Il! *How to use a semiconductor device as l1It. 2. A method for manufacturing a semiconductor device with one stacked ridge arrangement in which the percentage value is phosphorus, arsenic, and bog/ as rounded impurities for lower resistance. 34I + resistance rounded non-1II4A product, acid-based,
A method for manufacturing a semiconductor device in the first product range of the % evacuation model using argon as the % image.