JPS58124273A - Thin film silicon transistor - Google Patents

Abstract

PURPOSE:To reduce a threshold voltage and a leak current between a source and a drain and to obtain high mutual conductance due to the increase in carrier mobility, by providing a thin film of ZnS between a thin film of silicon and an amorphous insulating substrate. CONSTITUTION:When the ZnS thin film 6 is provided between the silicon thin film 13 and the amorphous insulating substrate 5, an interface level due to lattice misalignment of the silicon thin film 13 and the ZnS thin film 6 becomes very small, and the effect of instability due to movable cation and the like can be eliminated. Meanwhile the interface level is present at the interface between the ZnS thin film 6 and the amorphous insulating substrate 5, but even though the charges are induced in the ZnS thin film due to the interface elevel, the mobility of said charges is very small and the movable charges are not obtained. Therefore, the back channel effect can be eliminated and the threshold voltage and the leak current between the source and the drain can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to high performance silicon thin film transistors with low threshold voltage and high transconductance.

Conventionally, silicon thin film transistors on an amorphous insulating substrate have been manufactured by depositing an amorphous or polycrystalline silicon thin film directly on the amorphous insulating substrate and using this amorphous or polycrystalline silicon thin film. Ta. Additionally, in 1979, a method called graphoepitaxy that could grow silicon single crystal thin films on amorphous insulating substrates was developed, but this method also involves depositing silicon thin films directly onto the underlying amorphous insulating substrates. ing. FIG. 1 shows an energy band diagram in a structure in which a silicon thin film and an amorphous insulating substrate are in direct contact.

Here, 1 is a gate electrode region, 2 is a gate insulating film, 3 is a silicon thin film region, and 4 is an amorphous insulating substrate. In this case, there are many interface units at the interface between the silicon thin film 3 and the core substrate 4, and the bands of the silicon thin film region at the interface between the silicon thin film region 3 and the substrate 4 are influenced by the interface units and move. Due to a phenomenon in which electrons are induced, the so-called back channel effect, the threshold voltage of a thin film transistor increases and the leakage current between the source and drain increases. Further, due to the deterioration of the interface characteristics between the silicon fi1m and the substrate, the device breakdown voltage of the thin film transistor decreases. Furthermore, in amorphous silicon or polycrystalline silicon on an amorphous insulating substrate, a decrease in carrier mobility is observed due to poor crystallinity, and there is a drawback that the mutual conductance of a thin film transistor cannot be increased. On the other hand, in the graph-o-epitaxy method, it is necessary to have periodic grooves on the surface of the amorphous insulating substrate. The drawback is that the surface irregularities and cracks that occur in the thin film transistor cause deterioration in thin film transistor characteristics and decrease in yield.

In order to eliminate these drawbacks, the present invention makes it possible to realize a high-performance silicon thin film transistor by interposing a ZnS thin film between a silicon thin film and an amorphous insulating substrate.

In order to achieve the above object, the present invention provides a silicon thin film transistor characterized in that a ZnS thin film is interposed between a silicon thin film and an amorphous insulating substrate.

Next, embodiments of the present invention will be described with reference to the accompanying drawings. The embodiments are merely illustrative, and various changes and improvements may be made without departing from the spirit of the invention.

The second example shows an embodiment of the present invention. In the figure, 5 is an amorphous insulating substrate, 6 is a ZnS thin film, 7 is a source region, 8 is a gate insulating film, 9 is a drain region, 10 is a source electrode, 1
1 is a gate electrode, and 12 is a drain electrode. An energy band diagram with this configuration is shown in FIG. here,
1-3 is a silicon thin film region. Silicon thin film 1-3
By providing the ZnS thin film 6 between the amorphous insulating substrate 5 and the amorphous insulating substrate 5, one of the bands in the silicon thin film region 13 on the amorphous insulating substrate side is tilted toward the side with lower energy as shown in FIG. Electron induction is suppressed. This means that the electron affinities of silicon and ZnS are each 4.01 eV.

It is determined from the relationship between 3.9 eV and the band gaps of silicon and ZnS being 1.1 eV and 3.54 eV, respectively. Furthermore, the lattice constants of silicon crystal and ZnS thin film are 5.409 A and 5, respectively.
．． 42A, the lattice constant deviation is about 0.2%, and the interface state due to the lattice mismatch between the silicon thin film and the ZnS thin film becomes very small. Furthermore, the influence of instability caused by motive cations, which is a problem with amorphous insulating films, can be eliminated.

On the other hand, there is an interface state at the interface between the ZnS thin film and the amorphous insulating substrate;
Even if charges are induced in the thin film, the mobility of the charges within the ZnS thin film is very small and does not become a mobile charge. That is,
The presence of the ZnS thin film eliminates the cross-channel effect that occurs between the silicon thin film and the amorphous insulating substrate.
It is possible to reduce the threshold voltage and source-drain leakage current. Here, since the band gap of the ZnS thin film is as large as 3.54 eV and the carrier mobility is extremely low, it can be regarded as an insulating layer with respect to a silicon thin film transistor.

Furthermore, the ZnS thin film also has <
Since it is oriented in the Ill > direction and has a lattice constant that matches that of silicon crystal, it is possible to grow single-crystal silicon thin films on ZnS thin films by ordinary molecular beam epitaxial method or OVD method, and it is possible to grow thin films with high carrier mobility. It has high mutual conductance as a transistor. Further, as the interface characteristics between the silicon thin film and the ZnEl thin film are improved, the device breakdown voltage of the thin film transistor can be increased.

It goes without saying that the structure of the embodiment shown in FIG. 2 can be multilayered. In this case, an insulating layer is interposed between the first layer structure and the second (5) layer structure.

As explained above, by interposing the ZnS thin film between the silicon thin film and the amorphous insulating substrate, the threshold voltage and source-drain leakage current of the silicon thin film transistor can be reduced. Fortunately, it is possible to make a silicon thin film into a single crystal, and by increasing carrier mobility, it is possible to realize a silicon thin film transistor with high mutual conductance.

[Brief explanation of drawings]

Fig. 1 is an energy band diagram of a conventional structure in which a silicon thin film and an amorphous insulating substrate are in direct contact, Fig. 2 is a cross-sectional view of an embodiment of the present invention, and Fig. 3 is a structure according to the present invention. An energy band diagram is shown. DESCRIPTION OF SYMBOLS 1... Gate electrode region, 2... Gate insulating film, 3...
...Silicon thin film region, 4...Amorphous insulating substrate, 5.
...Amorphous insulating substrate, 6...Zn8 thin film, 7...source region, 8...gate insulating film, 9...drain region, 10...so(r, '+ - sumi pole, 11... Gate electrode, 12... Drain electrode, 1... Silicon thin film area patent applicant (7) Figure 1 Figure 2 Figure 3 Procedural amendment (voluntary) March 2, 15, 1980 Commissioner of the Japan Patent Office Shima 1) Haruki Tono1, Indication of the case (,-/' 1981 Patent Application No. 61052, Title of the invention Silicon thin film transistor 3, Relationship with the amended person case Patent applicant name (422) ) Nippon Telegraph and Telephone Public Corporation 4, agent address: 7-5-1o Nishi-Shinjuku, Shinjuku-ku, Tokyo 160 Japan (The thickness is preferably 0.1 to 1 pm).

Claims (1)

[Claims] A silicon thin film transistor characterized in that a ZnS thin film is interposed between a silicon thin film and an amorphous insulating substrate.