JPH0346369A - Insulated gate type field effect transistor - Google Patents

Abstract

PURPOSE:To accelerate operation of a transistor by forming a semiconductor layer having permittivity larger than that of a silicon substrate in a region including a channel region of an insulated gate type field effect transistor. CONSTITUTION:A silicon oxide film 2 as a gate insulating film is formed on the surface of a P-type silicon substrate 1, and a gate electrode 3 is formed thereon. An N-type layer 4 as source. drain is formed on the substrate 1 through the electrode 3. A semiconductor layer having permittivity larger than that of the substrate is formed in a region including a channel region of an insulated gate type field effect transistor formed on the substrate 1. In this case, the permittivity of the semiconductor layer formed in the channel region is large. Thus, an electric field which operates in a direction perpendicular to the channel is alleviated to suppress surface dispersion of carrier, thereby improving its mobility.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an insulated gate field effect transistor.

[Conventional technology]

In a conventional insulated gate field effect transistor, as shown in FIG. 3, a silicon oxide film 2 is formed as an insulating film on, for example, a P-type single silicon substrate 1, and a gate electrode 3 is formed on this. There is. Then, an N-type layer 4 as a source/drain is formed on the silicon substrate 1 so as to sandwich the gate electrode 3 therebetween.

[Problem to be solved by the invention] The conventional insulated gate field effect transistor described above has the following problems:
By applying a voltage between the silicon substrate 1 and the gate electrode 3, the energy band on the surface of the silicon substrate 1 is bent (band bending), a channel is formed, and the transistor is operated. Therefore, carriers within the channel are attracted to the silicon-oxide film interface by an electric field perpendicular to the band bending, and are scattered there, resulting in a reduction in mobility and a problem in that the operating speed of the transistor is reduced.

An object of the present invention is to provide a transistor with improved operating speed.

[Means to solve the problem]

In the transistor of the present invention, a semiconductor layer having a higher dielectric constant than the silicon substrate is formed in a region including the channel region of an insulated gate field effect transistor formed on a silicon substrate.

[Effect] In this configuration, since the semiconductor layer formed in the channel region has a large dielectric constant, the electric field acting perpendicularly to the channel is relaxed, suppressing surface scattering of carriers and improving their mobility. do.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, showing an example applied to an N-channel insulated gate field effect transistor. In the figure, a silicon oxide film 2 as a gate insulating film is formed on the surface of a P-type silicon substrate 1, and a gate electrode 3 is formed thereon. Further, an N-type layer 4 as a source/drain is formed on the silicon substrate 1 sandwiching the gate electrode 3. Furthermore, in the channel region sandwiched between these N-type layers 4, Ge (germanium) ions are implanted into the surface portion of the silicon substrate 1 to form a high dielectric constant Ge.
Forming the implant N5.

Note that this Ge injection layer 5 is selectively formed before forming the gate electrode 3 and the N-type layer 4.

According to this configuration, a channel is formed in the vicinity of the silicon-silicon oxide film due to the voltage applied to the silicon substrate 1 and the gate electrode 3. On the other hand, the electric field E perpendicular to the channel changes the surface charge density appearing in the channel by Q, Ge
If the dielectric constant of the injection layer 5 is ε, then according to Gauss's theorem,
Since E=Q/ε, the high dielectric constant Ge injection layer 5
By sandwiching them, the electric field E can be kept low.

Incidentally, the relative permittivity of GeO is 16.0, which is about 1.3 times the relative permittivity of silicon, which is 11.9, so the electric field E can be suppressed to about 74%. As a result, this structure reduces surface scattering of carriers, maintains high mobility, and achieves high-speed transistor operation.

FIG. 2 is a longitudinal sectional view of a second embodiment of the invention.

A high dielectric constant semiconductor layer 6 such as Ge is formed on the entire surface of a P-type silicon substrate by a method such as molecular beam epitaxy, and a silicon oxide film 2. Gate electrode 3. Then, an N-type layer 4 as a source and drain is formed to constitute an N-channel insulated gate field effect transistor.

In this example, since different semiconductor layers 6 are formed by epitaxial growth, the thickness of this semiconductor layer 6 can be accurately controlled, and the dielectric constant in this portion can be configured to a desired value with high precision. . As in the first embodiment, this reduces surface scattering of carriers, ensures high mobility, and enables high-speed transistor operation.

〔Effect of the invention〕

As explained above, in the present invention, a semiconductor layer having a higher dielectric constant than a silicon substrate is formed in a region including the channel region of an insulated gate field effect transistor, so that the semiconductor layer is used in a direction perpendicular to the channel. This has the effect of reducing the electric field acting on the surface, suppressing surface scattering of carriers, improving their mobility, and increasing the speed of transistors.

[Brief explanation of drawings]

FIG. 1 is a vertical cross-sectional view of a first embodiment of the present invention, FIG. 2 is a vertical cross-sectional view of a second embodiment of the present invention, and FIG. 3 is a vertical cross-sectional view of a conventional insulated gate field effect transistor. . 1... P-type silicon substrate, 2... silicon oxide film,
3... Gate electrode, 4... N-type layer, 5... Ge injection layer, 6... Ge semiconductor device

Claims (1)

[Claims] 1. In an insulated gate field effect transistor in which a gate insulating film and a gate electrode are formed on the main surface of a silicon substrate, and a source and drain are formed on the silicon substrates sandwiching this gate electrode, the region including the channel region is . An insulated gate field effect transistor comprising a semiconductor layer having a higher dielectric constant than the silicon substrate.