JPS631072A - Thin-film field-effect transistor - Google Patents
Thin-film field-effect transistorInfo
- Publication number
- JPS631072A JPS631072A JP14270186A JP14270186A JPS631072A JP S631072 A JPS631072 A JP S631072A JP 14270186 A JP14270186 A JP 14270186A JP 14270186 A JP14270186 A JP 14270186A JP S631072 A JPS631072 A JP S631072A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate insulating
- effect transistor
- film
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005669 field effect Effects 0.000 title claims description 14
- 239000010409 thin film Substances 0.000 title claims description 9
- 239000004065 semiconductor Substances 0.000 claims abstract description 17
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 11
- 239000010408 film Substances 0.000 claims description 25
- 230000000694 effects Effects 0.000 claims description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 239000000470 constituent Substances 0.000 claims 1
- 230000005684 electric field Effects 0.000 claims 1
- 239000000463 material Substances 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 229910052760 oxygen Inorganic materials 0.000 claims 1
- 239000001301 oxygen Substances 0.000 claims 1
- 229910052710 silicon Inorganic materials 0.000 claims 1
- 239000010703 silicon Substances 0.000 claims 1
- 239000011521 glass Substances 0.000 abstract description 3
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 2
- 230000003247 decreasing effect Effects 0.000 abstract description 2
- 230000006866 deterioration Effects 0.000 abstract description 2
- 238000003486 chemical etching Methods 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 6
- 239000000969 carrier Substances 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910005898 GeSn Inorganic materials 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 238000001994 activation Methods 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000005685 electric field effect Effects 0.000 description 1
- 238000001803 electron scattering Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000011160 research Methods 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は薄膜電界効果トランジスタに関する。[Detailed description of the invention] (Industrial application field) The present invention relates to thin film field effect transistors.
（従来の技術）
近年、水素を含む非晶質シリコンを半導体層とする薄膜
トランジスタ・アレイをスイッチング素子として用いた
デイスプレィパネルの研究開発が各所で行われている。(Prior Art) In recent years, research and development of display panels using thin film transistor arrays having hydrogen-containing amorphous silicon as a semiconductor layer as switching elements has been carried out in various places.
従来の薄膜トランジスタ（第４図）においてはゲート絶
縁膜１３とチャネルを構成する半導体層１５とが直接接
触している構造が採用されている。この場合には第３図
に示すようにゲート電圧の印加により、キャリヤの蓄積
されるチャネル部がこの界面近傍に集中して形成される
ために、このチャネル部を走行するキャリヤはこの界面
での界面準位や、ゲート絶縁膜中の捕獲準位にトラップ
される。特に非晶質半導体を用いた場合、これらの準位
の密度が大きく、薄膜トラレジスタの特性変動や特性の
バラツキの原因となっていた。A conventional thin film transistor (FIG. 4) employs a structure in which a gate insulating film 13 and a semiconductor layer 15 constituting a channel are in direct contact. In this case, as shown in FIG. 3, by applying a gate voltage, a channel region in which carriers are accumulated is formed in a concentrated manner near this interface. It is trapped in the interface level or the trap level in the gate insulating film. In particular, when an amorphous semiconductor is used, the density of these levels is high, causing variations in the characteristics of the thin film resistor and variations in the characteristics.
（発明が解決しようとする問題点）
結晶Ｓｉを用いたＭＯ８型電界効果トランジスタｉｃお
いては、ゲート絶縁膜とチャネル部とを分離する工夫が
試みられており、たとえばｒＭＯｓデバイスＪ（徳山ａ
著：工業調査会： １９７３／８／２０発行） Ｐ１９
３に「チャネルドープＪなる方法が紹介されている。こ
ればゲート絶＃ｌ膜側より、ホウ素（Ｂ）、リン（Ｐ）
等の元素をイオン、インプランチーシランすることによ
り、チャネル部のキャリヤ分布、従ってポテンシャル分
布を変化させるものであって、キャリヤの走行するチャ
ネル部を絶縁膜との界面より分離したものである。しか
るに非晶質半導体を用いた電界効果トランジスタに対し
ては、イオン・インプランテーシ曹ン後の活性化プロセ
ス（熱アニール）が適用できないため、この方法は不適
切であった。(Problems to be Solved by the Invention) In an MO8 field effect transistor IC using crystalline Si, attempts have been made to separate the gate insulating film and the channel part.
Author: Industrial Research Association: Published August 20, 1973) P19
3 introduces a method called channel doping.This method involves doping boron (B) and phosphorus (P) from the gate isolation film side.
By ionizing or implanting silane elements such as, the carrier distribution and therefore the potential distribution in the channel portion are changed, and the channel portion in which carriers travel is separated from the interface with the insulating film. However, this method was inappropriate for field effect transistors using amorphous semiconductors because the activation process (thermal annealing) after ion implantation cannot be applied.
また、特開昭５９−１１７２６５号には、非晶質半導体
層として非晶質・シリコンを用いた電界効果トランジス
タにおいて、ゲート絶縁膜を上記非晶質半導体層との間
に介在層を設ける技術が開示されている。しかし、この
技術は非晶質Ｓｉ層より水素原子がゲート絶縁膜へ入り
こまない介在層を形成した技術であり、界面準位を低下
させる上でのメリットは少なかったっ
本発明は、非晶質半導体、特に非晶質シリコン゛ を用
いた電界効果トランジスタ１こおいて、キャリヤの走行
するチャネル部とゲート絶縁膜の間を実質的に分離し、
従来技術においてこの界面において形成された界面準位
により生じていた特性の劣悪さ、変動を抑制し、良好な
電気特性を有する電界効果トランジスタを提供するもの
である。Furthermore, Japanese Patent Laid-Open No. 59-117265 discloses a technique in which an intervening layer is provided between the gate insulating film and the amorphous semiconductor layer in a field effect transistor using amorphous silicon as the amorphous semiconductor layer. is disclosed. However, this technology forms an intervening layer that prevents hydrogen atoms from entering the gate insulating film rather than an amorphous Si layer, and has little merit in lowering the interface state. In a field effect transistor 1 using a semiconductor, especially amorphous silicon, a channel portion in which carriers travel and a gate insulating film are substantially separated,
The object of the present invention is to suppress the deterioration and fluctuation of characteristics caused by the interface states formed at this interface in the prior art, and to provide a field effect transistor having good electrical characteristics.
（問題点を解決するための手段）
本発明は、チャネル部を構成する非晶質半導体と、ゲー
ト絶縁膜の間に、該非晶質半導体の禁制帯幅より大きい
禁制帯幅を有する介在層を連続的に形成し、かつ該非晶
質半導体端部より該絶縁膜端部に対して、この介在層の
禁制帯幅の値が増加するように構成することを特徴とす
る電界効果トランジスタである。(Means for Solving the Problems) The present invention provides an intervening layer having a forbidden band width larger than the forbidden band width of the amorphous semiconductor between the amorphous semiconductor constituting the channel portion and the gate insulating film. A field effect transistor characterized in that the intervening layer is formed continuously and configured such that the value of the forbidden band width of the intervening layer increases from the end of the amorphous semiconductor to the end of the insulating film.
（作 用）
上記した構造の電界効果トランジスタにおいては、キャ
リヤの走行するチャネル部がゲート絶縁膜との界面より
分離されて形成されるため、界面準位の影響を受け（こ
くくなる。またゲート絶縁膜中の捕獲準位によるキャリ
ヤの捕獲も、介在層により減少させることが可能となる
。この結果、ｖｔｈの変動及びｖｔｈの不均一性などが
著しく改善される。(Function) In a field effect transistor having the above structure, the channel portion in which carriers travel is formed separated from the interface with the gate insulating film, so it is affected by the interface state (becomes difficult). The intervening layer can also reduce carrier capture by trap levels in the insulating film.As a result, variations in vth and non-uniformity in vth are significantly improved.
（実施例）
第１図１こ本発明の一実施例を示す。ガラス基板１’
１上ｌこＭｏ １００ＯＡをスパッターし、ゲートｇ衡
１２を形成する。次ＩこプラズマＣＶＤにより、ゲート
絶縁膜としてＳ ｉＯｘ １３をｌ１１２０ Ｏｒａｍ
堆積する。次にＳｉＨ，２０ＳＣＣＭ、Ｈ，２００ＳＣ
ＣＭを一定としＮＨ，を２０ ＳＣＣＭからｏ ＳＣＣ
Ｍまで連続的に減少させ膜厚が３ Ｑ ｎｍのＳｉＮ膜
１４を堆積させた。(Embodiment) FIG. 1 shows an embodiment of the present invention. Glass substrate 1'
Sputter 100 OA of Mo on top of 1 to form a gate 12. Next, SiOx 13 was deposited as a gate insulating film by plasma CVD.
accumulate. Next, SiH, 20SCCM, H, 200SC
With CM constant, NH, from 20 SCCM to o SCC
A SiN film 14 having a film thickness of 3 Q nm was deposited by decreasing the thickness continuously to M.
引き続きこの膜の上に連続的にａ−８ｉ１５を２５００
＾、 ｎ＋ａ −８ｉ １５を５０ＯＡ堆積させた。ト
ランジスタ部としてａ−８ｉの島を形成した後に、Ｍｏ
５００ＡとＡ１１／ｉｎを蒸着しソース・ドレイン電
極１７を形成する。チャネル部のｎ＋ａ−８ｉをケミカ
ルドライエツチングにより除去する。Subsequently, 2500 g of a-8i15 was continuously applied on this film.
^, n+a -8i 15 was deposited at 50OA. After forming an a-8i island as a transistor part, Mo
Source/drain electrodes 17 are formed by evaporating 500A and A11/in. The n+a-8i in the channel portion is removed by chemical dry etching.
第２図に、本発明によるトランジスターのエネルギー図
を示す。第３図１こ従来例によるトランジスターのエネ
ルギー図を示す。第３図においてゲートに正電圧を印加
することにより、ａ−８ｉとゲート絶縁膜との間に電子
が電界効果により誘起されチャンネルが形成される。し
かし、ゲート絶縁膜とａ−８ｉの界面には、ゲート絶縁
膜用の原料ガスによる残留不純物、格子不整合による欠
陥等によるトラップが多数存在している。このため界面
付近においては電子の移動度が小さくなり、又、電子が
トラップに捕獲されることによるｖｔｈ変動が生じやす
いという欠点がある。FIG. 2 shows an energy diagram of a transistor according to the invention. FIG. 3 shows an energy diagram of a conventional transistor. In FIG. 3, by applying a positive voltage to the gate, electrons are induced between a-8i and the gate insulating film due to the electric field effect, and a channel is formed. However, at the interface between the gate insulating film and a-8i, there are many traps due to residual impurities due to the source gas for the gate insulating film, defects due to lattice mismatch, and the like. For this reason, there is a drawback that the mobility of electrons decreases near the interface, and vth fluctuations are likely to occur due to electrons being captured by traps.
これに対して、第２図の本発明のバンド図においては、
バンドの極小がゲート絶縁膜との界面から離れているた
めｌこ、チャンネル部付近では界面準位によるトラップ
が少なく、欠陥も少ない。このため、電子の散乱が減る
ため移動度が大きくなり、又ｖｔｈ変動が減少し、ＴＰ
Ｔ％性が向上した。On the other hand, in the band diagram of the present invention shown in FIG.
Since the minimum of the band is far from the interface with the gate insulating film, there are fewer traps due to interface states near the channel portion and fewer defects. For this reason, electron scattering is reduced, resulting in increased mobility, and vth fluctuations are reduced, resulting in TP
T% property improved.
更に本発明では、ａ−８ｉＮとａ−８ｉを連続的に形成
しているため、チャンネル領域のａ−８ｉはプラズマＣ
ＶＤの放電の起動時における欠陥の多い膜でなく、バル
クと同様なａ−８ｉがチャンネル部になるため、特性の
向上が著しかった。Furthermore, in the present invention, since a-8iN and a-8i are formed continuously, a-8i in the channel region is exposed to plasma C.
The characteristics were significantly improved because the channel portion was made of a-8i, which is similar to the bulk, instead of a film with many defects at the time of starting VD discharge.
なお、本実施例ではゲート絶ＲＭをＳｉＯとしたが、Ｓ
ｉＯに限らず、ＳｉＮ、Ａち０８等でも良い。又、形成
方法はプラズマＣＶＤによらずスパッター等、他の形成
方法でも良い。又、界面のグレーデツド層はＳｉＮとａ
−８ｉ の組み合わせに限らず、グレーデツド層が半
導体より大きいパッドギャップをもてばどのような組み
合わせでも効果がある。例えば、ＳｉＣとａ−８ｉ、Ｓ
ｉＮ又はＳｉＣとＳ ｉ Ｇｅ 、ＧｅＳｎ等の組み合
わせでも良い。In this example, the gate disconnection RM was made of SiO, but S
It is not limited to iO, but may also be SiN, Achi08, etc. Further, the forming method may be other forming methods such as sputtering instead of plasma CVD. In addition, the graded layer at the interface is made of SiN and a
Not limited to the -8i combination, any combination is effective as long as the graded layer has a larger pad gap than the semiconductor. For example, SiC and a-8i, S
A combination of iN or SiC and SiGe, GeSn, etc. may also be used.
なお、ＴＰＴの構造は本発明のようなスタガー型に限ら
ず、コプラナー型でも同様の効果が得られる。Note that the TPT structure is not limited to a staggered type as in the present invention, but a coplanar type can also provide similar effects.
本発明によれば、非晶質半導体を用いた電界効果トラン
ジスタにおいて、良好な電気特性を有する電界効果トラ
ンジスタを得ることができる。According to the present invention, in a field effect transistor using an amorphous semiconductor, a field effect transistor having good electrical characteristics can be obtained.
第１図は本発明の一実施例を示す図、第２図は本発明に
よるＴＰＴのエネルギーバンド図、第３図及び第４図は
従来例を示す図である。
１１・・・ガラス基板、１２・・・ゲート’に極、１３
・・・ゲート絶縁膜、１４・・・グレーデツド層、１５
・・・半導体、１６・・・ｎ％導体、１７・・・ソース
拳ドレイン。FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is an energy band diagram of a TPT according to the present invention, and FIGS. 3 and 4 are diagrams showing a conventional example. 11... Glass substrate, 12... Pole on gate', 13
...Gate insulating film, 14...Graded layer, 15
...Semiconductor, 16...n% conductor, 17...source fist drain.
Claims (3)
ンジスタにおいて、チャネルを形成する前記半導体層と
、ゲート絶縁膜との間に、そのエネルギ、バンドギャッ
プ値が、上記半導体層より上記ゲート絶縁膜に向って増
加するような介在層を構成することを特徴とする薄膜電
界効果トランジスタ。(1) In a thin film field effect transistor using an amorphous silicon semiconductor film, the energy and bandgap value between the semiconductor layer forming a channel and the gate insulating film are lower than that of the semiconductor layer. A thin film field effect transistor comprising an intervening layer that increases toward the film.
くとも炭素、窒素あるいは酸素のうちの１元素を含む非
晶質材料であることを特徴とする特許請求の範囲第１項
記載の薄膜電界効果トランジスタ。(2) The thin film electric field according to claim 1, wherein the intervening layer contains silicon as a constituent element and is an amorphous material containing at least one element of carbon, nitrogen, or oxygen. effect transistor.
特徴とする特許請求の範囲第１項記載の薄膜電界効果ト
ランジスタ。(3) The thin film field effect transistor according to claim 1, wherein the thickness of the intervening layer is 5 to 100 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14270186A JPS631072A (en) | 1986-06-20 | 1986-06-20 | Thin-film field-effect transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14270186A JPS631072A (en) | 1986-06-20 | 1986-06-20 | Thin-film field-effect transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS631072A true JPS631072A (en) | 1988-01-06 |
Family
ID=15321546
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14270186A Pending JPS631072A (en) | 1986-06-20 | 1986-06-20 | Thin-film field-effect transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS631072A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02218166A (en) * | 1989-02-17 | 1990-08-30 | Toshiba Corp | Thin film transistor |
| US5034340A (en) * | 1988-02-26 | 1991-07-23 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5041888A (en) * | 1989-09-18 | 1991-08-20 | General Electric Company | Insulator structure for amorphous silicon thin-film transistors |
| US5148248A (en) * | 1987-10-06 | 1992-09-15 | General Electric Company | Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays |
| US5196912A (en) * | 1988-10-28 | 1993-03-23 | Casio Computer Co., Ltd. | Thin film transistor having memory function and method for using thin film transistor as memory element |
| US5272361A (en) * | 1989-06-30 | 1993-12-21 | Semiconductor Energy Laboratory Co., Ltd. | Field effect semiconductor device with immunity to hot carrier effects |
| US6050827A (en) * | 1982-12-29 | 2000-04-18 | Sharp Kabushiki Kaishi | Method of manufacturing a thin-film transistor with reinforced drain and source electrodes |
-
1986
- 1986-06-20 JP JP14270186A patent/JPS631072A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6050827A (en) * | 1982-12-29 | 2000-04-18 | Sharp Kabushiki Kaishi | Method of manufacturing a thin-film transistor with reinforced drain and source electrodes |
| US5148248A (en) * | 1987-10-06 | 1992-09-15 | General Electric Company | Dual dielectric field effect transistors for protected gate structures for improved yield and performance in thin film transistor matrix addressed liquid crystal displays |
| US5034340A (en) * | 1988-02-26 | 1991-07-23 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5065202A (en) * | 1988-02-26 | 1991-11-12 | Seikosha Co., Ltd. | Amorphous silicon thin film transistor array substrate and method for producing the same |
| US5196912A (en) * | 1988-10-28 | 1993-03-23 | Casio Computer Co., Ltd. | Thin film transistor having memory function and method for using thin film transistor as memory element |
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