JPS581217A - Driving circuit for field effect transistor - Google Patents
Driving circuit for field effect transistorInfo
- Publication number
- JPS581217A JPS581217A JP9920781A JP9920781A JPS581217A JP S581217 A JPS581217 A JP S581217A JP 9920781 A JP9920781 A JP 9920781A JP 9920781 A JP9920781 A JP 9920781A JP S581217 A JPS581217 A JP S581217A
- Authority
- JP
- Japan
- Prior art keywords
- current
- winding
- transistor
- flows
- transformer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33538—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only of the forward type
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Continuous-Control Power Sources That Use Transistors (AREA)
- Dc-Dc Converters (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は、スイッチングレギュレータ等に用いるFET
(電界効果型トランジスタ)の駆動回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention provides an FET for use in switching regulators, etc.
(field effect transistor) drive circuit.
従来のスイ、チングレギ、レータは例えば第1図の様に
構成され、メイントランス(主変成器)TIの1次側に
直列に接続され光パワーMO8FgTQ3のオン期間を
ドライブトランス(駆動変成器)〒1を介して制御する
ことKより出力電圧0UTt−一定化している。メイン
トランスT1の1次巻線には入力(直流電源)INが接
続され、ま九該トランスのクランプ巻線の一端と入力I
Nの他端との間にはダイオード)が接続される。また該
トランスTIの2次側にはダイオードD4 e Di
sインダクタンスL1、容量C4からなる平均値整流回
路RECが接続される。ドライブトランス〒1の第2
巻線1$IPETQsの駆動用巻線で、そのゲート、ソ
ース間に抵抗R4′1−介して接続される。また第1巻
線■に線容量C重と直列FC!IpmトランジスタQt
# Q雪のコレクタ、エヤツタ間が接続される。これ
らのトランジスタ(b −Q諺は発振制御回路C0NT
tによりて交互、に駆動される。Conventional switches, chinglegs, and regulators are configured as shown in Figure 1, for example, and are connected in series to the primary side of the main transformer TI, and are used to control the on-period of the optical power MO8FgTQ3. By controlling K through 1, the output voltage 0UTt- is kept constant. An input (DC power supply) IN is connected to the primary winding of the main transformer T1, and one end of the clamp winding of the transformer and the input I
A diode) is connected between the other end of N and the other end of N. Furthermore, a diode D4 e Di is connected to the secondary side of the transformer TI.
An average value rectifier circuit REC consisting of an s-inductance L1 and a capacitance C4 is connected. Drive transformer〒1 2nd
Winding 1 is a driving winding of IPETQs and is connected between its gate and source via a resistor R4'1-. Also, FC in series with line capacitance C in the first winding ■! Ipm transistor Qt
# The Q snow collector and air filter are connected. These transistors (b-Q proverbially refer to the oscillation control circuit C0NT
It is driven alternately by t.
概略動作を説明する。発振制御回路C0NT、は出力バ
ルスムでトランジスタQ1t−駆動し、を九パルスムと
逆相のパルスBでトランジスタQ* t 駆動する。そ
して、トランジスタQ1がオンの期間に補助電源からQ
t −CB−Iの経路で電流(以下消勢電流と呼ぶ)が
流れ、容量C!は図示極性に充電される。このとき第2
巻線IK発生す−る電圧はiFI’rQsのゲート、ソ
ース間を逆バイアスするので、(bはオフである。これ
に対しA−I、(ロー)、B=H(ハイ)となってトラ
ンジスタQ1がオン(Qlはオフ)すると、容量CIの
電荷はQ!のコレクタからエギ、りに向う方向に放電す
る。この時第1巻線IK流れる電流(以下付勢電流と呼
ぶ)Kよシ2次巻隷属にはFly Qlt”順バイアス
する電圧が誘起されて偽はオンとなる。トランジスター
がオンのとき入力INの端子11丁雪の1次巻線、Q3
、端子すの経路で電流が流れ、これはT、の2次巻線に
電圧を誘起させてD4、LhC,の経路で電流を流し、
コンデンサCat−充電する。なおトランスの巻線に付
した・印はコイルの巻始めを示す。トランジスタQsが
オフのとき、1次巻線に誘起する電圧で端子1)sDl
、1次巻線の延長部、端子すの経路で電流が流れ、紋巻
線の電圧を電IN(IN)電圧にクランプする。マ九こ
のときインダクタンスL1に誘起する電圧はLl 1C
a e Diの経路に電流を流し該インダクタンスに誘
起する電圧を吸収する。トランジスタQ3がオンオフす
る毎に上記のことが繰シ返され、DC(直流)−DC変
換を行なう。The general operation will be explained. The oscillation control circuit C0NT drives the transistor Q1t- with the output pulse, and drives the transistor Q*t with the pulse B having the opposite phase to the nine pulses. Then, during the period when transistor Q1 is on, Q
A current (hereinafter referred to as deenergizing current) flows through the path t - CB - I, and the capacitance C! is charged to the polarity shown. At this time, the second
Since the voltage generated by the winding IK reverse biases the gate and source of iFI'rQs, (b is off. On the other hand, A-I (low) and B=H (high). When the transistor Q1 is turned on (Ql is turned off), the charge in the capacitor CI is discharged from the collector of Q! in the direction toward the edge.At this time, the current flowing through the first winding IK (hereinafter referred to as the energizing current) is A voltage that forward biases Fly Qlt is induced in the secondary winding slave, and the false turns on. When the transistor is on, the primary winding of the input IN terminal 11, Q3
A current flows in the path of terminal S, which induces a voltage in the secondary winding of T, causing current to flow in the path of D4, LhC,
Capacitor Cat - Charge. Note that the mark on the transformer winding indicates the beginning of winding of the coil. When the transistor Qs is off, the voltage induced in the primary winding is the terminal 1) sDl.
, an extension of the primary winding, a current flows in the path of the terminal, clamping the voltage of the crest winding to the voltage IN (IN). At this time, the voltage induced in the inductance L1 is Ll 1C
A current is passed through the path of ae Di and the voltage induced in the inductance is absorbed. The above process is repeated every time the transistor Q3 is turned on and off, thereby performing DC (direct current)-DC conversion.
直流出力OU’rの電圧値は整流回路RECでトラフ入
出力02次出力を平均値整流したものであり、トランス
T、の巻数比、1次電圧、および1次巻線の通電期間に
関係するから、その値が低下したときはFieTQsの
オン時間を長くシ、逆に上昇したときはFIT Qsの
オン時間を短縮することで安定化できる。このため出力
OUTの一部(電圧値)が増幅器および比較器などを備
える発振制御回路C0NTIK帰還され、パルスム、B
のデユーティを制御する(周期は一定にしておく)。The voltage value of the DC output OU'r is obtained by rectifying the trough input/output 0 secondary output to an average value using the rectifier circuit REC, and is related to the turns ratio of the transformer T, the primary voltage, and the energization period of the primary winding. Therefore, when the value decreases, the on-time of FieTQs is lengthened, and when the value increases, it can be stabilized by shortening the on-time of FITQs. Therefore, a part (voltage value) of the output OUT is fed back to the oscillation control circuit C0NTIK, which includes an amplifier and a comparator, etc.
(keep the cycle constant).
この装置では主電源系とトランジスタらの制御系との絶
縁が問題である。即ちドライブトランスTIおよびメイ
ントランス?、01次、2次間は完全に絶縁されている
が、直流出力OUTの電圧管検出する系と発振制御回路
C0NT、はこのtまでは絶縁されず、そして補助電源
つまシQ3制御系電源も結局は入力INからとる必要が
あるので、 IN。In this device, insulation between the main power supply system and the control system including transistors is a problem. That is, the drive transformer TI and the main transformer? , 01st and 2nd order are completely insulated, but the DC output OUT voltage tube detection system and oscillation control circuit C0NT are not insulated up to this point, and the auxiliary power supply Q3 control system power supply is also isolated. In the end, it is necessary to take it from the input IN, so IN.
OUT間が絶縁できない恐れがある。これを絶縁するた
めには、(1)1部に商用絶縁トランスと整流装置を介
在させるが1+はトランスttむ補助DC−DCコンバ
ータを介在させて補助電源とするか、又は(2)Y部に
フォFカプラなどの直流回路で動作可能な絶縁手段を介
在させる必要がある。しかしながら補助電源の入力が直
流である場合は(1)の商用絶縁トランスの使用は実現
不可能であシ、その場合状補助コンバータを使用するこ
とになるが、これは部品点数が多いので得策ではない。There is a possibility that insulation between OUTs cannot be achieved. In order to insulate this, (1) a commercial isolation transformer and a rectifier should be interposed in part 1, but an auxiliary DC-DC converter including a transformer tt should be interposed in part 1+ to serve as an auxiliary power source, or (2) part Y should be used as an auxiliary power supply. It is necessary to interpose an insulating means that can be operated with a DC circuit, such as a photo-F coupler. However, if the input of the auxiliary power supply is DC, it is not possible to use a commercial isolation transformer in (1), and in that case an auxiliary converter must be used, but this is not a good idea because it requires a large number of parts. do not have.
この点け)のフォトカップラは有用な手段であるが、こ
れは長期的に見て特性変動を生じることが予想され、安
定性メ問題となる。Although this photocoupler is a useful means, it is expected to cause characteristic fluctuations over the long term, leading to stability problems.
本発明は、ドライブトランスを有効に活用して上述し九
問題を解決しようとするもので、その特徴とするところ
は駆動トランスの第1巻線に一方向の付勢電流と逆方向
の消勢電流とを交互に流し、該トランスの第2巻線にゲ
ート、ソース間管接続した電界効果型トランジスタに対
して、該付勢電流通電時にゲート電荷を蓄積し該消勢電
流通電時に該ゲート電荷を引抜いて該トランジスタをオ
ン、オフするようにしてなる電界効果型トランジスタの
駆動回路において、誼駆動トランスに第3巻線を設け、
そして該第1巻線に付勢電流が流れている期間に峡第3
巻線に強制消勢電流を流したときは該電界効果型トラン
ジスタのゲート電荷が強制的に引抜かれるようにしてな
る点にある。以下、図示の実施例を参照しながらこれを
詳細に説明する。The present invention attempts to solve the above-mentioned nine problems by effectively utilizing a drive transformer.The present invention is characterized by an energizing current flowing in one direction and a deenergizing current flowing in the opposite direction in the first winding of the drive transformer. When the energizing current is applied, the gate charge is accumulated, and when the energizing current is applied, the gate charge is In a drive circuit for a field effect transistor, which turns the transistor on and off by pulling out the transistor, a third winding is provided in the drive transformer,
Then, during the period when the energizing current is flowing through the first winding, the third
The point is that when a forced deactivation current is passed through the winding, the gate charge of the field effect transistor is forcibly drawn out. This will be explained in detail below with reference to illustrated embodiments.
第2図は本発明の第1の実施例を示す。本発明ではドラ
イブトランスT1に第3巻線璽を設け、この第3巻隷属
に消勢電流量、を流してFIT (bを強制的にオフさ
せるようKLl、このようにすればトランステ10絶縁
作用で、前記絶縁問題は簡単に処理できる。第3巻隷属
に線容量C3、ダイオードへ、トラyジスタQ4t′I
/II!続L%該トランジスタQ4にパルス幅制御回路
coN’r雪を接続する。また本回路ではトランジスタ
Q3のペース抵抗R,に容量CIを並列接続しているが
、これは次の理由による。即ちトランジスタQsはFE
Tであってこれは電圧制御型であり、ゲート容量を充電
したのちは電流を流さなくてもゲート電圧を維持できる
。そとで抵抗−は高抵抗としてトランジスタChの常時
のペース電流、従うてコレクタ電流は小とし、トランジ
スターがオンになる(このとき偽もオン)ときのみコン
デンサC雪を通して大きなペース電流を流しコレクタ電
流従りてコンデンサCIの放電電流iIt大とする。FIG. 2 shows a first embodiment of the invention. In the present invention, the drive transformer T1 is provided with a third winding, and a deenergizing current is passed through the third winding to forcibly turn off FIT (KL1). Then, the above insulation problem can be easily handled.The third volume is connected to the line capacitance C3, to the diode, and to the transistor Q4t'I.
/II! A pulse width control circuit coN'r is connected to the transistor Q4. Further, in this circuit, a capacitor CI is connected in parallel to the pace resistor R of the transistor Q3 for the following reason. That is, the transistor Qs is FE
This T is a voltage control type, and after charging the gate capacitance, the gate voltage can be maintained without flowing current. On the other hand, the resistor - is a high resistance, and the constant pace current of the transistor Ch, so the collector current is small, and only when the transistor is turned on (false is also on at this time), a large pace current is passed through the capacitor C, and the collector current is Therefore, the discharge current iIt of the capacitor CI is made large.
第3図は各部の動作波形図で、中央より左側がトランジ
スタQ4が作動しない第1図と同様の状態である。図中
、A、Bは発振制御回路C0NTHの出力で、互いに逆
相のパルスである。本例ではこのパルス列の周期〒は一
定で、デユーティも一定であるとする。II(Q鵞)は
トランジスタQmのペース電流、vGl(Qりはそのコ
レクタ、エミッタ間電圧である。1.は図示方向に流れ
るとき前述した付勢電流(CIの放電電流)となシ、逆
方向に流れるとき消勢電流(CIの充電電流)となる。FIG. 3 is an operating waveform chart of each part, and the left side of the center shows a state similar to FIG. 1 in which the transistor Q4 does not operate. In the figure, A and B are the outputs of the oscillation control circuit C0NTH, and are pulses with opposite phases to each other. In this example, it is assumed that the period of this pulse train is constant and the duty is also constant. II (Q) is the pace current of the transistor Qm, vGl (Q is the voltage between its collector and emitter). When it flows in the direction, it becomes a deenergizing current (CI charging current).
Vmg (Qa )はトランジスタq4のペース、エミ
、り間電圧であり、電流1.は図示方向に流れるとき前
述した強制消勢電流(Csの放電電流)となり、逆方向
に流れるときC,の充電電流となる。I@s 1liF
ET Qsのゲート、ソース間電流、vGlはゲート、
ソース間電圧、IDはドレイン電流、vDlはドレイン
、ソース間電圧である。Vmg (Qa) is the voltage between the base and emitter of transistor q4, and the current 1. When flowing in the direction shown in the figure, it becomes the aforementioned forced deenergizing current (discharging current of Cs), and when flowing in the opposite direction, it becomes a charging current of C. I@s 1liF
The current between the gate and source of ET Qs, vGl is the gate,
The voltage between the source, ID is the drain current, and vDl is the voltage between the drain and the source.
トランジスタQ4で制御しない場合には、1周期T内の
FIT Qsのオン時間〒QWはトランジスタ(hのオ
ン時間に依存する一定値をとる。これに対レトランジス
ターで制御するとFET Qsのオン時間To夏′は短
縮される。即ち、トランジスタQtがオンして第1巻線
■に消勢電流−1,が流れる時、第3巻線厘に流れる充
電電流−1,によって容量C3はダイオードへを通して
図示極性に充電される。一方、パルス幅制御回路C0N
T*は出力電圧OUTを基準値と比較するパルス幅変調
(PWM)回路で、出力電圧OUTが基準値を上回れば
その差に応じたパルス幅の出力Vmm (Qa )をト
ランジスタQ4のペース、工2.タ間に印加する。この
緒果トランジスタT4がオンし、容量C3の電荷を放電
させる。なおパルス幅制御回路CON〒雪はトランスT
雪の2次側から電源をとって同期がとられており、出力
Vmg (Q4 )を生じるタイ建ングはトランジスタ
Qsのオン期間(B=Hの期間)である。容量Csの放
電電流は第3巻線厘に流れる強制消勢電流輸となる。こ
の電流i、が流れるときにはトランジスタQ嘗がオンし
ていて第1巻線Iには付勢電流11が流れている。しか
LAtlによる磁束に打勝てば第3巻隷属に誘起される
電圧がFWT Qlのゲートから電荷を引抜くことがで
き該ygTQse強制的にオフできる。本回路では前述
のようにペース抵抗R1と並列に容量C3を接続して該
抵抗R鵞e大としているので、電流1、ラミ流1mの定
常値より簡単に大にできる。なおFli:TQsは−H
ゲートに電荷が蓄積されればそれが放電されない限シ敢
えて充電電流を流さなくともオン状態を維持し、従って
定常的にはペース電流11(Q鵞)は不安であるが、実
際にはゲート電荷がリークするのでそれを補う程度に高
抵抗RgKよりて僅かにペース電流を流しておく、第3
図のT、叢′はこの様にして短縮され九PE’rQsの
オン時間である。出力OUTの平均値電圧V・は主変成
器T鵞の2次側電圧Vs VC対し、トランスの巻線の
抵抗分及びダイオードの電圧降下を無視するとき、′l
。When not controlled by the transistor Q4, the on-time of the FET Qs within one period T takes a constant value depending on the on-time of the transistor (h).If controlled by a pair of transistors, the on-time To of the FET Qs In other words, when the transistor Qt is turned on and a deactivating current -1 flows through the first winding 2, the charging current -1 flowing through the third winding causes the capacitor C3 to pass through the diode. The pulse width control circuit C0N is charged to the polarity shown.
T* is a pulse width modulation (PWM) circuit that compares the output voltage OUT with a reference value. 2. The voltage is applied between the two terminals. As a result, the transistor T4 turns on and discharges the charge in the capacitor C3. In addition, the pulse width control circuit CON〒Snow is a transformer T
Synchronization is achieved by taking power from the secondary side of the snow, and the tie construction that produces the output Vmg (Q4) is the on period of the transistor Qs (the period when B=H). The discharge current of the capacitor Cs becomes a forced deenergizing current flowing to the third winding. When this current i flows, the transistor Q is on and the energizing current 11 flows through the first winding I. However, if the magnetic flux by LAtl is overcome, the voltage induced by the third volume slave can extract the charge from the gate of FWT Ql, and the ygTQse can be forcibly turned off. In this circuit, as described above, the capacitor C3 is connected in parallel with the pace resistor R1 to make the resistance R larger, so that it can be easily made larger than the steady value of the current 1 and the lamination current 1 m. Note that Fli:TQs is -H
If charge is accumulated in the gate, it will remain on even if no charging current is applied as long as it is not discharged.Therefore, the pace current 11 (Q) is unstable in a steady state, but in reality, the gate charge leaks, so a small pace current is passed through the high resistance RgK to compensate for it.
T, plexus' in the figure is thus shortened to the on-time of nine PE'rQs. The average voltage V of the output OUT is the secondary voltage Vs VC of the main transformer T, and when ignoring the resistance of the transformer winding and the voltage drop of the diode, 'l
.
の関係にあるので、ToMがT、買′に減少することで
V・は低下する。本例の回路は、1点鎖線内の回路がメ
イントランスT、02次側にあるため、フォトカプラ方
式と同様に発振制御回路C0NT、側の補助電源を補助
コンバータ等を経ずに直接供給できる。Therefore, when ToM decreases to T, buy', V. decreases. In the circuit of this example, since the circuit within the dashed line is on the main transformer T, secondary side, the auxiliary power supply for the oscillation control circuit C0NT, side can be directly supplied without going through an auxiliary converter, etc., similar to the photocoupler method. .
本例は容量C3の充電電源をドライブトランスT1の第
1巻線側とした点に特色がある。This example is characterized in that the charging power source with the capacity C3 is placed on the first winding side of the drive transformer T1.
これに対し、第4図に示す本発明の他の実施例は容量C
sの充電電源をメイントランス丁鵞の第2二次巻線とし
友ものである。巻線Wはその追加され□た第2二次巻線
で、容量Csは抵抗R,およびダイオード)を通して充
電する。DIは容量Csの放電経路に順方向に介在した
ダイオードである0本例の回路で一本動作原理は第2図
と変らない。第3図に相当する本回路のタイムチャート
の要部(変る部分)を第5図に示す。In contrast, another embodiment of the present invention shown in FIG.
The charging power source for s is the second secondary winding of the main transformer. The winding W is the added second secondary winding, and the capacitor Cs is charged through the resistor R and the diode. DI is a diode interposed in the forward direction in the discharge path of the capacitor Cs, and the operating principle is the same as in FIG. 2. The main parts (changed parts) of the time chart of this circuit corresponding to FIG. 3 are shown in FIG.
尚、いずれの実施例においても第1巻線Iの極性を逆に
すればトランジスタQ!tオンにして容量CIK充電す
る電流が付勢電流となり、t7’t)ランジスタGh?
オンにして容量CIから放電する電流が消勢電流となる
。この場合でも第3巻線の強制消勢電流杜常に第1巻線
に付勢電流が流れる期間に流すものであシ、またこれを
有利にするためにはトランジスタQl側のベース抵抗R
,に容量を並列接続する( Cmは除去する)。また駆
動巻隷属を複数にすることで同時に複数のFETを駆動
できることは明らかである。さらに本発明のFIT駆動
回路は上述し九スイッチングレギ、レータのみならず、
トランジスタを4個組合せ光フルブリッジ回路等にも適
用できる。In any of the embodiments, if the polarity of the first winding I is reversed, the transistor Q! The current that turns on t and charges the capacitor CIK becomes the energizing current, and t7't) transistor Gh?
The current discharged from the capacitor CI when turned on becomes the deactivating current. Even in this case, the forced energizing current in the third winding must always be applied during the period when the energizing current flows in the first winding, and in order to make this advantageous, the base resistance R on the transistor Ql side is
, connect the capacitors in parallel (Cm is removed). Furthermore, it is clear that a plurality of FETs can be driven at the same time by having a plurality of drive windings. Furthermore, the FIT drive circuit of the present invention includes not only the above-mentioned nine switching legs and rotors, but also
It can also be applied to optical full-bridge circuits, etc. in which four transistors are combined.
以上述べ友ように本発明によれば、FHTと駆動、制御
、絶縁の機能會持九せた1個のドライブトランスを組み
合せるととによシ、例えば入力電圧が直流、交流の区別
なく高周波まで安定なスイッチングレギュレータを容易
に構成することが出来る。特にFIC〒はバイポーラト
ランジスタの電流駆動と違い電圧駆動であり、ゲート容
量の充放電電流しか流れず駆動電力が非常に小さい。又
、蓄積時間がない為数百KHz以上のスイッチングが可
能である利点がある。As mentioned above, according to the present invention, it is possible to combine an FHT with a single drive transformer having the functions of drive, control, and insulation, so that the input voltage can be high frequency regardless of whether it is direct current or alternating current. It is possible to easily construct a stable switching regulator. In particular, the FIC is voltage driven, unlike the current drive of bipolar transistors, and only the charge/discharge current of the gate capacitance flows, and the driving power is very small. Furthermore, since there is no storage time, switching at a frequency of several hundred KHz or more is possible.
第1図は従来のスイッチングレギュレータの一例を示す
回路図、第2図および第3図は本発明の一実施例を示す
回路図および動作波形図、第4図および第5図は本発明
の他の実施例を示す回路図および動作波形図である。
図中、T1はドライブトランス(駆動変成器)、1〜璽
は第1〜嬉3巻線、偽はFET(電界効果型トランジス
タ)である。
出願人 富士通株式会社FIG. 1 is a circuit diagram showing an example of a conventional switching regulator, FIGS. 2 and 3 are circuit diagrams and operation waveform diagrams showing an embodiment of the present invention, and FIGS. 4 and 5 are circuit diagrams showing an example of a conventional switching regulator. FIG. 2 is a circuit diagram and an operation waveform diagram showing an embodiment of the present invention. In the figure, T1 is a drive transformer, 1 to 3 are first to third windings, and T1 is a FET (field effect transistor). Applicant Fujitsu Limited
Claims (1)
消勢電流とを交互に流し、該トランスの第2巻線にゲー
ト、ソース間を接続した電界効果型トランジスタに対し
て、核付勢電流通電時にゲート電荷を蓄積し該消勢電流
通電時に該ゲート電荷を引抜いて該トランジスタをオン
、オフするようにしてなる電界効果型トランジスタの駆
動回路において、該駆動トランスに第5巻線を設け、そ
して峡第1巻線に付勢電流が流れている期間に該第3巻
線に強制消勢電流を流したときは該電界効果型トランジ
スタのゲート電荷が強制的に引抜かれるようにしてなる
こと1*徴とする電界効果型トランジスタの駆動回路。An energizing current in one direction and a deactivating current in the opposite direction are alternately passed through the first winding of a drive transformer, and the field effect transistor has its gate and source connected to the second winding of the transformer, In a drive circuit for a field effect transistor, which accumulates a gate charge when the core energizing current is applied and draws out the gate charge when the deactivating current is applied to turn the transistor on and off, the drive transformer is provided with a fifth volume. A wire is provided so that when a forced deenergizing current is passed through the third winding while an energizing current is flowing through the first winding, the gate charge of the field effect transistor is forcibly drawn out. A field-effect transistor drive circuit with 1* characteristics.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9920781A JPS581217A (en) | 1981-06-26 | 1981-06-26 | Driving circuit for field effect transistor |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9920781A JPS581217A (en) | 1981-06-26 | 1981-06-26 | Driving circuit for field effect transistor |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS581217A true JPS581217A (en) | 1983-01-06 |
JPS6222347B2 JPS6222347B2 (en) | 1987-05-18 |
Family
ID=14241200
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9920781A Granted JPS581217A (en) | 1981-06-26 | 1981-06-26 | Driving circuit for field effect transistor |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS581217A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4744020A (en) * | 1986-05-22 | 1988-05-10 | Honeywell Information Systems Italia | Switching mode power supply |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5127850A (en) * | 1974-08-09 | 1976-03-09 | Nippon Kokan Kk | HITAISHOCHOKUSENGATAKOYAITA OYOBI SONOSEIZOHOHO |
JPS5612123A (en) * | 1979-07-10 | 1981-02-06 | Nec Corp | Electric-current feedback type driving circuit |
-
1981
- 1981-06-26 JP JP9920781A patent/JPS581217A/en active Granted
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5127850A (en) * | 1974-08-09 | 1976-03-09 | Nippon Kokan Kk | HITAISHOCHOKUSENGATAKOYAITA OYOBI SONOSEIZOHOHO |
JPS5612123A (en) * | 1979-07-10 | 1981-02-06 | Nec Corp | Electric-current feedback type driving circuit |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4744020A (en) * | 1986-05-22 | 1988-05-10 | Honeywell Information Systems Italia | Switching mode power supply |
Also Published As
Publication number | Publication date |
---|---|
JPS6222347B2 (en) | 1987-05-18 |
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