JP3302808B2 - Switching power supply - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switching power supply device used for various electronic devices, and more particularly to a high-speed driving of a switching circuit element on a primary side of a power conversion transformer.

[0002]

2. Description of the Related Art In recent years, in power supply devices for various electronic devices, in order to improve power conversion efficiency and reduce the size of the device, AC input power is rectified into DC power, and the DC power is used as a basis. 2. Description of the Related Art A so-called switching power supply device is widely used in which power is converted into high-frequency power by intermittent use of a power semiconductor element or the like, and power is transferred by a small power conversion transformer to obtain a DC output.

In order to improve power conversion efficiency,
A PWM power control method in which a control signal is given to a power semiconductor element as a duty ratio (hereinafter, referred to as PWM) signal has become common.

In such a power supply device, the potential of the control signal generating section and the potential of the power control section are often significantly different, and it is necessary to provide electrical insulation. As a technique therefor, a method of performing signal transfer using a photocoupler, which is an optical insulating means, is also used. However, the phototransistor section of the photocoupler is difficult to respond at high speed, and the signal transfer speed is usually about 10 KHz. However, in order to improve the precision and size of the power control device and reduce noise,
The higher the PWM signal transfer rate, the better the increase. Therefore, the signal transmission speed of the photocoupler has become insufficient.

[0005]

To this end, as shown in the circuit diagram of the conventional switching power supply of FIG. 6, a circuit for inserting an isolation transformer T1 between a control circuit and a power control circuit has been devised as a signal transmission means. Have been.

In this circuit, a signal transmission transformer is used to insulate the primary circuit and the secondary circuit. Therefore, a magnetic material having a low loss in a high frequency region is used for the transformer, and the winding structure and the number of windings are devised. This makes it possible to obtain the required high-frequency signal transmission characteristics.

As described above, by using an insulating transformer for transferring a PWM signal, a high-speed PWM signal transfer circuit can be realized relatively easily.

However, when the PWM signal is not transferred, for example, the transistor of TR5 is cut off, so that the transformer T1 is in a high impedance state, and
The bias of the transistor of R2 and TR3 becomes unstable, and the MOS-FET (Metal Oxide Semiconductor) of TR4
There were drawbacks such as the malfunction of the Field Effect Transistor).

Further, even when transferring the PWM signal, the driving impedance is high, so that the accumulated charges in the transistors TR2 and TR3 cannot be completely discharged, so that the switching speed is low and the switching frequency has to be lowered. There was also.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and has as its object to provide a switching power supply device in which the switching speed of the primary side of a power conversion transformer is further increased. It is.

[0011]

In order to achieve the above object,
Therefore, according to the present invention, the switching power supply device is described in the following (1).
Configure as follows. (1) switching power supply enter the duty ratio signal to the power semiconductor device having the primary side of the power conversion transformer and a signal transmission transformer and the power conversion transformer for controlling the output from the power conversion transformer secondary side an apparatus, the ratio signal oscillation control circuit when entering the time ratio No. Ritsushin into the primary side winding of the signaling transformer, a duty ratio signal inputted from the secondary winding of the signal transmission transformer the power semiconductor element drive circuit and the signal the power amplifier circuit connected to said power amplifier circuit and the secondary side winding of the transmitting transformer and the power semiconductor device having a power amplifier for power output to the control terminal of the power semiconductor element Bei and control means for controlling the operation example, the system
The control means is constituted by a field effect transistor.
Input of the duty ratio signal to the primary winding of the signal transmission transformer
Depending on the condition, the secondary winding of the signal transmission transformer is short-circuited
Switching power that may or may not
Source equipment.

[0012]

According to the above arrangement, when there is no drive level input of the duty ratio drive signal in the signal transmission transformer, the output side of the signal transmission transformer is short-circuited by the control means, so that the power semiconductor drive circuit and the power semiconductor element Can be prevented, and the power conversion transformer can be driven and output at a higher speed than before.

[0013]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a switching power supply according to the present invention will be described with reference to embodiments.

(First Embodiment) FIG. 1 is a circuit diagram showing a first embodiment of the present invention. The circuit diagram of the embodiment described later (FIGS.
The same reference numerals shown in FIG. 5) indicate the same components.

In FIG. 1, T1 is an insulating transformer for transmitting a PWM signal, and TR1 is a junction FET for short-circuiting a winding of the transformer. D1 is a diode for clamping a back electromotive voltage of the signal transmission transformer T1, and R1 is a damping resistor for absorbing the back electromotive force of the signal transmission transformer T1. TR2 and TR3 are transistors for driving the MOS-FET of TR4, and TR4 performs power switching according to the driving waveform, and the power is applied to T2.

T2 is an insulating transformer for power conversion,
The output is rectified by diodes D3 and D4, and a DC output is obtained by a filter including a choke coil CH1 and a capacitor C3.

C2 is an electrolytic capacitor for absorbing power supply ripple. R5 and R6 are voltage-dividing resistors connected to the output terminal, and the midpoint thereof is connected to the detection terminal of IC1 which is an output voltage detection feedback element and connected to P2 shown in IC2.
A detection voltage is applied to the WM oscillation control circuit.

IC2 has a sawtooth wave generating circuit and generates a pulse corresponding to the feedback voltage, and its output is connected to the base of the transistor of TR5. The collector of the transistor TR5 is connected to the primary winding of the signal transmission transformer T1, and transfers the drive waveform to the main switching element TR4.

Next, the operation will be described.

When each input voltage is applied to the DC 130 V input terminal and the auxiliary power input terminal, the PWM oscillation control circuit IC2
Operates, a PWM waveform is applied to the base of the transistor of TR5, the transistor TR5 switches, and the current flowing through the primary winding of the signal transmission transformer T1 is turned on and off.
Then, a voltage is generated in the secondary winding of the transformer T1.

The voltage generated in the secondary winding of the transformer T1 is applied to the base of the transistor TR2 via the resistor R1. Since the input voltage accumulates electric charge in the capacitor C1 via the resistor R2, a voltage sufficient to operate the transistors TR2 and TR3 is generated at both ends of the capacitor C1, so that the power MOS-FET of the TR4 is generated.
A predetermined pulse width is applied to the gate of the MOS-FET, the MOS-FET is turned on and off, and a chopping current flows through the primary winding of the T2 converter transformer for power conversion. This gives 2
A chopping voltage is generated at both ends of the next winding and D3 and D
4 is rectified by the diode 4 and smoothed by the LC filter of the choke coil CH1 and the capacitor C3 to be a DC voltage, and a voltage is generated between the output terminals.

The voltage generated here is input from the voltage dividing circuit composed of resistors R5 and R6 to the voltage detecting element of IC1, and the error signal is fed back to IC2 of the PWM oscillation control circuit. When the output voltage is high, the pulse width becomes narrow. When the output voltage is low, the pulse width is controlled to be widened, and the output voltage is stabilized.

In the second primary winding of the transformer T2, a voltage corresponding to the winding ratio with respect to the first primary winding of the transformer T2 is generated.
The voltage is rectified by the diode D2 and the capacitor C
1 and supplied as the operating voltage of the transistors TR2 and TR3.

Here, when the PWM signal becomes high potential, the transistor TR5 is turned on, a voltage is applied to the primary winding of the signal transmission transformer T1, and a voltage is generated in the secondary winding of the transformer T1. This voltage raises the gate voltage of the Pch-FET TR1 to a positive potential through the resistor R1, and the TR1 is reverse-biased, the junction FET TR1 enters a high impedance state, and the current passing through the resistor R1 is the transistor T1.
It flows into the base of R2.

Since the base current flows from the transformer T1, the transistor TR2 is raised until the emitter voltage of the transistor TR2 becomes substantially equal to the voltage generated by the secondary winding of the transformer T1.
The gate voltage of MOS-FET No. 4 is raised and MO of TR4 is raised.
The S-FET is turned on and a drain current flows.

When the PWM signal becomes low potential, the base current of the transistor TR5 disappears, the transistor TR5 is turned off, the current of the primary winding of the transformer T1 is cut off, and the secondary winding of the transformer T1 is inverted from the positive potential and inverted. A potential in the direction is generated. With this potential, the diode of D1 turns on and the resistor R1
A regenerative current flows via the. The current flowing at this time fixes the potential of the resistor R1 at a negative potential, the gate potential of the TR1 also becomes a negative potential, turns on the Pch-FET TR1 and forcibly sets the base potentials of the transistors TR2 and TR3 to the ground potential.

For this reason, the transistor TR3 sucks the charge charged in the gate of the transistor TR4 into the emitter through the resistor R3, rapidly discharges the gate-drain voltage of the MOS-FET of the transistor TR4, turns off the transistor TR4, and cuts off the drain current. I do.

The above operation is repeated to turn on / off the TR4 of the MOS-FET which is the main switch element, thereby controlling the output power.

In the power supply device of the above embodiment, when the output is to be stopped by an external control signal or the like, the PWM signal is stopped to stop the power switching TR4 of the main switch element.

Next, the operation and effect of this embodiment will be described.

In the conventional example shown in FIG. 6, after the switching operation of the transistor TR5 is stopped,
A back electromotive voltage is generated by the exciting current of the transformer T1, the diode D1 is turned on, and the exciting current of the transformer T1 is discharged via the diode D1.

Therefore, on the secondary winding side of the transformer T1,
While the exciting current of the diode D1 continues to flow, a reverse bias is applied to the transistors TR2 and TR3 by the back electromotive force. Then, the exciting current continues to be discharged, and when the exciting current finally disappears, the potential difference between the terminals of each winding disappears, and the signal transfer transformer T1 becomes the impedance of the transformer's own inductance, and both the primary and secondary windings are very low. The state becomes high impedance.

In this phenomenon, the better the characteristics of the signal transmission transformer T1, the more the impedance rises when there is no signal. As a result, the base terminals of the transistors TR2 and TR3 connected to the secondary winding of the transformer T1 are in a floating state and are susceptible to external induction. In a switching power supply or the like, when the primary side switch voltage reaches several hundred volts and the potential is induced to the base circuit of the transistors TR2 and TR3 in a floating state, a noise voltage is generated at the emitters of the transistors TR2 and TR3.

The noise voltage of the MOS-F of TR4
The ET gate is driven, TR4 malfunctions, and the drain voltage of TR4 oscillates due to noise. Oscillation of the drain voltage of the power switch element of the transistor TR4 generates noise, and the noise is guided to the base circuit of the transistors TR2 and TR3 in a high impedance state. Such a noise induction loop is completed, and the conventional apparatus has a problem that the circuit is abnormally oscillated by the noise loop and the operation of the circuit is not stopped even though the PWM signal is stopped by the external control input.

However, in the embodiment of the present invention, FIG.
As shown in the figure, the source of the Pch-FET of the transistor TR1 is connected to the base circuit of the transistors TR2 and TR3 via the resistor R7, the drain of the transistor TR1 is grounded, and the gate is the resistor R1.
When the gate of the Pch-FET of the TR1 is reverse-biased with respect to the signal of the positive potential when the transformer T1 is in the operating state, the drain of the FET of the TR1
A high impedance state is established between the sources with respect to the transformer T1 and the resistor R1, and the signal generated in the secondary winding of the transformer T1 is transmitted to the bases of the transistors TR2 and TR3.

When the drive signal of the transistor T1 is at a low potential, the FET gate potential of the TR1 becomes zero bias, the resistance between the drain and the source of the TR1 becomes low, and the base potentials of the transformer T2 and the transistor TR3 are almost grounded. The transistor TR3 sinks the current to discharge the electric charge charged in the transistor TR4.

When the PWM signal is no longer supplied to the transformer T1 due to an external oscillation stop signal, the transformer T1 is turned off.
Since the voltage between the secondary windings of No. 1 is no longer generated,
The gate potential of the ch-FET becomes zero bias and T
A low impedance state is established between the drain and source of R1, and the drive transistors TR2 and TR2 of TR4 are driven.
3 can be grounded with low impedance.

With respect to the impedance of the secondary winding when the PWM input of the transformer T1 is stopped, the ground impedance of the base circuit at the zero bias of the FET of the TR1 is very low. Occurs, the potentials of the base circuits of the transistors TR2 and TR3 hardly fluctuate, so that the gate potential of the transistor TR4 is almost fixed to the ground potential.
Since the gate potential of the ET does not fluctuate, occurrence of a malfunction can be prevented.

(Second Embodiment) FIG. 2 is a circuit diagram of a second embodiment of the present invention.

In the first embodiment shown in FIG. 1, when the PWM signal rises or the like, the FET of TR1 is not completely reverse-biased and the signal transmission transformers T1 to T1 until the potential is stabilized.
A current flows through the FET of R1, resulting in an increase in power loss of the PWM drive transistor TR5 and an increase in the transformer capacity of T1.

Therefore, in the second embodiment, the Pch of TR1 is
-By taking the gate signal of the FET from the front side of the resistor R1, the signal applied to the gate of the FET of TR1 can be applied earlier than the source side, and the conduction state of the FET changes at the same time the potential of the PWM signal is switched. The current from the resistor R1 is directly applied to the base circuits of the transistors TR2 and TR3.

At the moment when the potential is switched from the high potential to the low potential, the gate of TR1 is forward-biased first, so that the base current of the transistors TR2 and TR3 is drawn through the resistor R1. Transistor TR to extract base current directly from source at high speed
2 and the switching time of TR3 can be made shorter than in the first embodiment.

By connecting as described above, the PWM drive signal from TR5 can be efficiently transferred to transistors TR2 and TR2.
3 and the power loss of the transistor TR5 and the transformer T1 can be reduced.

(Third Embodiment) FIG. 3 is a circuit diagram of a third embodiment in which the driving frequency is increased.

The voltage of the base circuit can follow the PWM drive signal from the transistor TR5 at a high speed by adding the transistor TR1. However, the transistors TR2 and TR3 are bipolar transistors, and the base current accumulation time. The output voltage switching speed is reduced.

Therefore, in this embodiment, as shown in FIG. 3, by adding diodes D6 and D7, the transistor TR is added.
2, the storage time is shortened by driving the transistor TR2 in an unsaturated manner, and the diode TR5 is also added to the transistor TR3 to perform the unsaturated drive and match the speed of the transistor TR2.

At the moment when the switching speed is increased and the bipolar transistor is switched from a high potential to a low potential as a device, the gate of the transistor TR1 is forward-biased earlier than the base potential of the transistor TR2, and passes through the resistor R1. Therefore, the base current of the transistor TR3 does not pass through the resistor R1 but flows directly from the source of the FET TR1.
The switching time of R3 can be reduced, and the MOS-
The gate drive waveform of the FET can be speeded up.

(Fourth Embodiment) FIG. 4 is a circuit diagram of a fourth embodiment of the present invention.

In the third embodiment shown in FIG. 3, since a high-speed circuit by the FET TR1 is added to the transistor TR3, the signal generated in the secondary winding of the transformer T1 switches from a high potential to a low potential. At this moment, there is a concern that the transistor TR3 is turned on earlier than the transistor TR2 is turned off by the operation of the transistor TR1 so that the accumulated charge in the transistor TR2 cannot be completely discharged and a through current flows from the transistor TR2 to the transistor TR3. In order to eliminate this, a diode D8 is added to the base circuit of the transistor TR2, and when the output potential of the transformer T1 decreases, the accumulated charge is drawn from the base of the transistor TR2 to the transformer T1 side via the resistor R1. From the turning on of the transistor TR3, the transistor TR
2 is turned off to prevent a through current from flowing, and TR
The power loss is not increased even if the drive frequency of the MOS-FET No. 4 is increased.

(Fifth Embodiment) FIG. 5 is a circuit diagram of a fifth embodiment of the present invention.

In this embodiment, the element of the transistor TR1 is not limited to a Pch-FET element, but is a Pch-MOS-FET having a voltage-driven type and a depletion + enhanced type (normally-on type).
And the operation is the same as that of the J-FET.

By using a MOS-FET for TR1, a forward current at the time of forward bias of TR1 can be prevented from flowing out from the gate, the driving power of the transistor TR5 and the transformer T1 can be reduced, and the transistor of the T1 transformer or TR5 can be reduced. Can be downsized.

[0053]

As described above, according to the present invention,
By providing a control circuit for short-circuiting the winding by the FET between the secondary winding of the PWM signal transmission transformer and the drive circuit of the power semiconductor element, the transformer of the transformer can be used in the state of the input signal.
Since the next winding can be automatically short-circuited or open-circuited at a high speed, the switching speed of the circuit for driving the power semiconductor element can be increased.

Further, when the PWM signal is stopped, the secondary winding of the signal transmission transformer can be automatically short-circuited. There is an effect that a malfunction of the semiconductor element can be prevented and a stable power supply circuit can be formed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a second embodiment.

FIG. 3 is a circuit diagram of a third embodiment.

FIG. 4 is a circuit diagram of a fourth embodiment.

FIG. 5 is a circuit diagram of a fifth embodiment.

FIG. 6 is a circuit diagram of a conventional switching power supply device.

[Explanation of symbols]

C1 bypass capacitor C2 smoothing capacitor C3 smoothing capacitor D1 reverse bias diode D2 rectifier diode D3, D4 output voltage rectifier diode D5 to D8 speed-up diode CH1 voltage smoothing choke coil IC1 output voltage detection element IC2 PWM oscillation control circuit R1 drive stage drive resistance R2 Starting resistance R3 Driving resistance R4 to R6 Voltage detection resistance R7 Current limiting resistance T1 Insulation transformer for signal transmission T2 Insulation transformer for power conversion TR1 Winding short-circuit element (Pch J-FET, MOS-
FET) TR2 drive transistor TR3 drive transistor TR4 MOS-FET for power switching TR5 PWM drive signal switching transistor

Claims (1)

(57) [Claims] 1. A switching device comprising a signal transmission transformer and a power conversion transformer, wherein a time ratio signal is input to a power semiconductor element provided on a primary side of the power conversion transformer to control output from a secondary side of the power conversion transformer. the power supply device, the ratio signal oscillation control circuit when entering the time ratio No. Ritsushin into the primary side winding of the signaling transformer, a duty ratio signal inputted from the secondary winding of the signal transmission transformer the power and the power semiconductor element drive circuit having a power amplifier for output power to the control terminal of the semiconductor element, wherein the secondary winding of the signal transmission transformer and the connected to the power amplifier circuit power amplifier circuit and the power semiconductor Control means for controlling the operation of the element.
The control means is constituted by a field effect transistor.
And a duty ratio signal to the primary winding of the signal transmission transformer.
The secondary winding of the signal transmission transformer according to the input state of
A switching power supply characterized in that the switching power supply is or may not be short-circuited .