JPS581202A - Controller - Google Patents

Abstract

PURPOSE:To reduce the power consumption more at power failure for a controller inporporated in a processor, by increasing the period of an interruption time at power failure and its waiting time. CONSTITUTION:The system in provided with a power failure clock CL2 and a clock switching circuit 9. When a power failure is detected with a power failure detecting circuit 5, a detection signal DE is given to a clock switching circuit 9, which switches the clock of a clock generating circuit 1 from CL1 to CL2. The period of the clock CL2 is taken longer than the period of the clock CL1, resulting that the WAIT state of a microprocessor is ketp longer, allowing to reduce the power consumption. Further, the signal DE is given to the microprocessor 2 via an I/O device 4, allowing the processor 2 to reduce the power consumption more with the power failure processing which has shorter processing time than the normal processing.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device 1 using a processing device such as a microprocessor that is normally operated by an AC power source and operated by a battery or the like during a power outage. Regarding the expression.

Generally, in a device that compensates for a power outage using a battery or the like, it is strongly recommended that the power consumption during one power outage compensation be as small as possible due to the relationship between one compensation time and battery capacity.

FIG. 1 is a block diagram showing a conventional example of a control device using, for example, a microprocessor. FIG. 2 is a flow chart for explaining its operation.

In the first wI, l is a clock generator, 2 is a microphone processor, 3 is a WAIT (standby) circuit, 4 is an input/output device (Ilo), s is a power failure detection circuit, and 6 is a power supply j11
circuit, 7 is a battery, and 8 is a switching circuit. Accepts the interwoven signal IN and disables subsequent interrupts (■) 0 Microphone pp setter 2 performs predetermined processing based on a predetermined program ((ri), WAIT
When the instruction is executed (■), the WAI T
The command signal WTI is sent to the WAIT@path 3. The microprocessor 2 receives the WAIT signal W from the circuit 3.
T enters the WAIT state and sets the primary interlaced signal IN to a state where reception is possible (0)1 Check whether there is an interrupt request (ro), and if there is an interrupt request, return to ■ and perform the same operation as above. Repeat, and if there is no request, wait until the next request. Micro precessor 2 is WAI
The power consumption in the T state is lower than in other operating states, so by doing the above, the power consumption cost can be reduced. 2 is operated by power from the AC snowfield circuit 6 in normal times, but when a power outage is detected by the power outage detection circuit 5, the power supply 16 is switched to the battery 7 by the switching circuit 8, and power is supplied from the battery 7. supply. Therefore, even in the event of a power outage, the Microsive ρ Senna 2 can program the program in the same way as described above and perform the prescribed processing.However, in this method, the power consumption during power on and power outage is the same, so In order to extend the power outage compensation time, it is necessary to increase the battery capacity. However, increasing the capacity requires a larger space and complicates the charging circuit.

Therefore, an object of the present invention is to further reduce the power consumption of a control device incorporating a processing device such as a microprocessor during a power outage.

The above objects are as follows: (1) According to the present invention, the interrupt time period during a power outage of a control device incorporating a processing device that is operated by a fixed periodic interrupt signal and driven by battery compensation during a power outage is lengthened, and the processing device increase the waiting time of
In other words, this is achieved by lengthening the low power consumption time.

Embodiments of this invention will be described below with reference to the drawings. ◇ ssm is a block diagram showing an embodiment of this invention, and FIG. 4 is a flowchart explaining the operation of FIG. 2
Components that are the same as those in the figure are indicated with the same number.

As is clear from these figures, this invention is the first. !
[When the conventional method explained by
In addition to adding a remote switching circuit 9, a power failure detection signal t is added.
DLL can be detected by the microphone gas input +2 via l10 (input/output device) 4, and has a function to determine whether there is a power outage or not (see flowchart ■ in Figure 4). This is what I did.

In other words, during normal power supply, the same operation as described above is performed, but when one power outage is detected by the power outage detection circuit 5, the test detection signal DB is given to the switching circuit 9, so that the clock is switched. The circuit 9 switches the output of the clock generation circuit 1 from CL to CL. Here, if the period of the power failure CL is made longer than the period of the RITA TSUTTA CL during one energization, the WAIT state of the microprocessor becomes longer by 1, and power consumption can therefore be reduced. Furthermore, this power outage detection signal DI is sent via I10@place 4! Power failure processing (3 mW σ
), power consumption can be further reduced.

Note) Other points are the same as those described in FIG. 1 or FIG. 2, and will therefore be omitted.

As described above, 1. According to the present invention, it is possible to achieve even lower power consumption than in the conventional control device in which the microprocessor is operated by battery compensation during a power outage to perform predetermined processing. When compensating for a power outage for the same amount of time, the battery capacity can be reduced. In other words, if the capacity of one battery is the same, the power failure compensation time can be made longer than before.

Note that the present invention is applicable to general devices having the same configuration as above, that is, it is necessary to operate the processing device (ii) during a power outage.

[Brief explanation of drawings]

Figure 2g is a block diagram showing a conventional example C of a control device using a microprocessor; Figure 2g is a flowchart for explaining the operation of Figure 1; Figure 3 is a block diagram showing an embodiment of the present invention; 4wJ is a flowchart for explaining the operation of FIG. 3. 0 Symbol explanation 1... Clock generation circuit, 2... Microb stomach processor, 3... WAI circuit. , 4...
... l10 (input/output device), 5 ... power failure detection path) 6 ... power supply circuit, 7 ... battery, 8 ... switching M path, 9... four-way switching circuit-IN...interconnected signal, WT
...WAIT (standby) signal, WTI...
...WAIT command signal, DB...data bus, AB...address bus, DB...
-・Power failure detection signal, CL, , CL,...-rip
Ivy Signal Agent Patent Attorney Akio Namiki Agent Patent Attorney Kiyota Matsuzaki 1 Figure 2 Figure 3

Claims (1)

[Claims] During normal operation, it is activated by an interrupt signal of a predetermined cycle, and when a predetermined processing operation is completed, it enters a standby state, and the next interrupt signal releases the standby state and performs a predetermined processing operation. In a control device comprising a processing device that receives power from a backup power source and operates according to the same procedure as in normal times, the time period of the interrupt signal is switched depending on normal times and power outages. A control device characterized in that: (1) a means is provided, and (1) when a power outage occurs, the time period of the interrupt signal is made longer than in normal times, thereby (1) the standby time of the processing device is lengthened;