JPS59168511A - Detecting system of service interruption for sequencer - Google Patents

Abstract

PURPOSE:To detect easiy the factor for a service interruption when a sequence operation is wrong by storing the information showing the generation of the service interruption in case a service interruption longer than a prescribed period of time of detected. CONSTITUTION:A processing circuit 1 which receives a signal from an input device 5 and delivers the signal to an output device 6 detects the service interruption of a power supply 2. Then the circuit 1 stores the data on the service interruption to a memory 3 backed up by a battery 4 before the voltage drop of the supply 2 exceeds the working limit of the processor 1. A flag showing the service interruption is set up and stored in the memory 3. When the service interruption lasts longer than a prescribed period of time, e.g., 10ms, the operation of the processor 1 is discontinued until the service interruption is over with the service interruption flag set up. When the service interruption is over within a prescribed period, a normal sequence is reset after the service interruption flag on the memory 3 is reset. A display device 7 displays the state of the service interruption flag on the memory 3 and therefore displays the generation of a service interruption longer than a prescribed period of time.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a method for detecting a power outage in a sequencer.

PRIOR ART There is a conventional sequencer 1d1 that is configured to continue full operation even if a power outage occurs for a short predetermined period of time. In such prior art, malfunctions occur when erroneous signals are manually applied to the sequencer during the power outage. The problem was that the sequencer operator did not know the cause of such malfunctions.

Purpose An object of the present invention is to provide a power outage detection method for a sequencer that detects all occurrences of a power outage when there is a risk that all erroneous signals may be input due to a power outage.

Example FIG. 1 is a block diagram of one embodiment of the present invention.

The sequencer has a processing circuit 1 including a microcomputer and the like. This processing circuit 1 is powered by a power source 2. This electricity 12 may cause a power outage. A memory 3 such as a random access memory included in the processing circuit 1 is so-called back-amplified by a storage battery 4 so that the entire storage state can be maintained even in the event of a power outage of the power supply 2. A signal is inputted to the processing circuit 1 from an input device R5, and a calculated signal is outputted to an output device 6. A display device 7 is connected to the processing circuit 1 .

When the power supply 2 is normal, the processing circuit 1 receives a signal from the human power device 5 and outputs the signal to the output device 6, thereby operating an external device (not shown).

This processing circuit 1 detects a power outage in the power supply 2, and
When an abnormality is imminent, the power supply 2 actually turns on the processing circuit 1.
It is configured to perform an interrupt operation and perform all the operations shown in FIG. 2 earlier than the operation limit of 1 is exceeded, that is, within the period during which the processing circuit 1 continues its normal operation.

Information is stored in the memory 3 of the processing circuit 1 as shown in the memory map shown in FIG. In this memory 3,
The contact points XO, Xi, X2,..., the output contacts YO, Yl, Y2,..., and the internal relay CRO,
Information regarding CRI, CR2, . . . is allocated and stored. When a power outage occurs, the power outage flag CRO, which is an internal one, is set to logic "1" and sent.

The operator of the sequencer must select the sequence program A that should be executed when power supply 2 is normal as shown in Figure 4, and when the power is restored after a power outage of 10m5ec or more, for example, for a predetermined period of time. The sequence program B that should be updated is stored in the memo IJ3. During normal operation, the power outage flag CRO is logic "0", so the jump instruction JMP is not executed. In this way, the operation of sequence program A is repeated. Jump instruction JMP is sequence program Ai step J
This is an instruction to interrupt and execute sequence program B without executing up to MPE. After a power outage continues for a predetermined period of time, for example 10m5ec or more,
When the power outage is restored, sequence program B is executed. At the end of this sequence program B, internal relay CR8 becomes logic "1", and power failure flag CRO is reset to logic "0". As a result, the normal sequence program A will be executed when the next cycle is executed. That is, when the power is restored, the sequence program B' is executed once, and then the normal sequence program Ai during normal operation is repeatedly executed.

In FIG. 2, when a power outage occurs, steps n1 to n2
, input contact X1 output contact Y, and internal relay C
Save the R data so that it does not change. In step n3, the power outage flag CRO', which is one of the internal relays, is
Cent to i logical "1". Therefore, in step n3a, a predetermined period of time, for example, 10 m5ec' (z) is counted. After this predetermined period of time has elapsed, it is determined in step n4 whether or not the power outage continues.

If the power outage is not sustained, that is, the power outage state is 10m.
If less than 5 ec occurred, step n
5, the power failure flag CRO is reset to logic "0", the interrupt operation is terminated from step n6, and the normal sequence program A is continued. When the power outage continues for a predetermined time or more, the process moves from step n4 to step n7, and the power outage flag CRO is set.'1
．． The operation stops in the current state. This cent state of the power outage flag CRO is maintained by the action of the storage battery 4. When the power is restored after a power outage lasting longer than a predetermined time, the jump command is executed as described above, and the sequence program B is executed. Thereafter, the normal sequence program A is repeatedly executed as described above.

At a predetermined time h, for example 10m5ee as mentioned above
Therefore, even if a power outage occurs, there is almost no possibility that an incorrect human input signal will be given to the sequencer. Therefore, normal operation can continue in its entirety. If the power outage 1 continues for a predetermined period of time or longer, there is a risk that the sequencer will receive all incorrect signals. At this time, the display device 7 displays that the power outage flag CRO is logical "1". Therefore, when a sequence operation is erroneous, it is easy to fully determine whether or not the cause is due to a power outage.

Effects As described above, according to the present invention, all power outages that have lasted longer than a predetermined time are detected and all information on the occurrence of power outages is stored, so when the sequencer makes an erroneous operating sound, It is easy to investigate the cause.

[Brief explanation of drawings]

Fig. 1 is a block diagram of one embodiment of Fukumei, Fig. 2 is a flowchart for explaining its operation, Fig. 3 is a diagram showing the entire memory map of the memory 3, and Fig. 4 is a diagram showing the power outage flag CRO.
FIG. 2 is a diagram for explaining the entire operation using. 1... Processing circuit, 2... Power supply, 3... Memory, 4
...Storage battery 5, 5...Input device, 6...Output device, 7...Display device Agent Patent Attorney Kei Nishi Part 3 Figure 4

Claims (1)

[Claims] A power outage detection method for a sequencer that detects a power outage that lasts for a predetermined period of time or more and stores all information indicating the occurrence of a power outage in a storage means that maintains the memory state even during the power outage.