JPS58119622A - Clip for solid state laminated electronic circuit part - Google Patents

Clip for solid state laminated electronic circuit part

Info

Publication number
JPS58119622A
JPS58119622A JP217282A JP217282A JPS58119622A JP S58119622 A JPS58119622 A JP S58119622A JP 217282 A JP217282 A JP 217282A JP 217282 A JP217282 A JP 217282A JP S58119622 A JPS58119622 A JP S58119622A
Authority
JP
Japan
Prior art keywords
clip
electronic circuit
laminated electronic
laminate
solid state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP217282A
Other languages
Japanese (ja)
Inventor
高田 正昭
駿介 佐々木
有末 一夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP217282A priority Critical patent/JPS58119622A/en
Publication of JPS58119622A publication Critical patent/JPS58119622A/en
Pending legal-status Critical Current

Links

Landscapes

  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 本発明は、ラジオ受イI!情等の電子機器の実装におい
て、固体槓1−電子回路部品(回路モジュール)?各種
目1i&構成基板□(rC入セラ、tツク他)へ半田寺
を用いて′畦気的機械的に接続するためのクリップに#
jIJするものである0従来からチップ部品(抵抗・コ
ンデンサ・インダクhfス)とこれらの複合部品におい
ては。
DETAILED DESCRIPTION OF THE INVENTION The present invention provides radio receiver I! In the implementation of electronic devices such as computers, solid-state components 1-electronic circuit components (circuit modules)? Attach # to the clip for mechanically connecting each type 1i & component board □ (rC-containing ceramic, ttsuk, etc.) using solder pads.
Conventionally, chip parts (resistors, capacitors, inductors) and their composite parts have been used.

構造上、内部電極と外部電極を有し、その外部電也はム
f −P(i等の導体ペーストを塗布し焼成したものが
一般的である。しかし、この導体ペーストによる外部電
極形成の場合、固体積層シ子回路部品では、積層誘電体
がある為、外部電儂の配置上、各電憔間に浮遊容量が生
じ、本来所望する電気特性を得ることが因嬌であった0
本発明は、このよう碌従来の問題点に鑑み。
Structurally, it has an internal electrode and an external electrode, and the external electrode is generally coated with a conductive paste such as Muf-P(i) and fired. However, when forming the external electrode with this conductive paste, In solid-state laminated circuit components, since there is a laminated dielectric material, stray capacitance occurs between each electric conductor due to the arrangement of external electric currents, making it difficult to obtain the desired electrical characteristics.
The present invention has been made in view of these conventional problems.

浮遊容量を小さくする工夫會構じた構造のクリップを提
供するものである。
The present invention provides a clip with an ingenious structure that reduces stray capacitance.

以下1図面を用いて本発明の一実1MylIにつき説明
する。第1図を第2図は固体積層電子回路部品のコンデ
ンサ形成部分を示しており、積層体(1)内の内部電極
(2)、(3)は妨電体層(4)を介してコンデンサ(
C1)を栴成し、外部電極の端子(6) (6)に接続
されている。同様に端子<8)’(97闇にコンデンサ
(C2)が形成さnている。縞3図は該積層体上に形成
さnる電子−路装置It、を示しており、端子L5) 
(6) (7) (9) +tQが回路構成基板へのM
I!続用端子となる。4J4図は隠子回路図である。こ
こで端子(句(IQは電子回路では増幅回路の入力用端
子となり。
Hereinafter, one example of the present invention, 1 MylI, will be explained using one drawing. Figure 1 and Figure 2 show the capacitor formation part of a solid-state multilayer electronic circuit component, and the internal electrodes (2) and (3) in the laminate (1) are connected to the capacitor through the anti-disruption layer (4). (
C1) and is connected to the terminal (6) (6) of the external electrode. Similarly, a capacitor (C2) is formed at the terminal <8)' (97 in the dark. The third stripe shows the electronic path device It formed on the laminate, and the terminal L5)
(6) (7) (9) +tQ is M to the circuit configuration board
I! Serves as a connection terminal. Figure 4J4 is a hidden circuit diagram. Here, terminal (Phrase (IQ) is the input terminal of the amplifier circuit in electronic circuits.

本来コンデンサ(C1)で所望するriを設定すること
になるが、端子(5)は内部ta層との接続上導体ペー
ストで形成することになるoしかし、端で約10P1%
度の値が得られている(誘電体がBaTiesで、t 
−400α端子(5)09間ピッチ1.25 m。
Originally, the desired ri would be set with the capacitor (C1), but the terminal (5) would be formed with conductive paste to connect with the internal TA layer.
(The dielectric is BaTies and the value of t
-400α terminal (5) pitch between 09 and 1.25 m.

電子(51QO塗布面槓1×2m、爆子四と隣接する内
部電権虐間寸法がQ、5 uのとき)。
Electron (51QO coating surface 1 x 2 m, when the internal electric power abuse dimension adjacent to bomb 4 is Q, 5 u).

この浮遊各音を小さくする方法として1例えばfs框体
層の一1部に轟接する部分にガラス等の低誘電体層を介
在させて、端子(至)を導体ペーストで形成する方法等
があるが、いずれも作業性が悪く、工根威が増加し、コ
ストアップとなる。又ガラスの場合、N電率は7〜15
のil金有しており、幼果的でない0 本発明Fi、端子としてクリップを用いて浮遊容量を小
さくシ、かつ作業性良く端子を形成するので声?、そn
らの実施例を講5図及至第11図に示す。第5図、第6
図及び第8図は積層体(1)のa面部(6)とクリップ
調量に、積層体(1)より4低い誘電率の空気層α81
t−確実に介在させるようにしている(空気の誘電率#
−1)。第7図はクリップllBの積層体(1)の側面
5o3Jの当接部に低誘電率材料をコーティングしてい
るもので。
One way to reduce these stray sounds is to interpose a low dielectric layer such as glass in the part that contacts one part of the fs frame layer, and form the terminal with conductive paste. However, both methods have poor workability, increase labor costs, and increase costs. In the case of glass, the N electric rate is 7 to 15.
The present invention uses clips as terminals to reduce stray capacitance, and forms terminals with good workability. , son
Examples of these are shown in Figures 5 to 11. Figures 5 and 6
The figure and Fig. 8 show an air layer α81 with a dielectric constant 4 lower than that of the laminate (1) in the a-plane part (6) of the laminate (1) and the clip metering.
t - Ensures that the air is present (dielectric constant of air #
-1). FIG. 7 shows a clip llB in which the abutting portions of the side surfaces 5o3J of the laminate (1) are coated with a low dielectric constant material.

クリップ製造途中のフープ材状態で一括して塗布できる
ものである@ また、別の方法として、第12図の如く、積層体(1)
の側面部回に低誘電率材料(5)をコーティングするこ
ともできる◎具体的な方法としては。
It can be applied all at once while the hoop material is still in the process of being manufactured.@Also, as another method, as shown in Fig.
It is also possible to coat the side surface of the material (5) with a low dielectric constant material (5) ◎Specific method.

ガラス材料等全焼きつける方法、1M脂等を溶剤を使用
して塗布する方法等がある。この第12図の方法の利点
Ifi、従来の導体ペーストで端子を形成する方法で景
求されるところの積層体上面と91m血のエツジ部にお
けるガラス等の低誘電体層及び導体ペーストの接続のm
実装を必景としないため作業性がよく、工程数も減少す
る点である。さらに第12図のクリップ形状に、第51
第6図、第8図、第9図等の形状を用いれば低M[*材
料との接触面積が減り浮遊容量はさら[減少するという
利点も生まnる0 第9図はクリップ(支)の中央部近辺に穴−をあけて、
該積層体(1)との接触rki横を小さくしたものであ
る。
There are methods such as a method of completely baking the glass material, a method of applying 1M fat or the like using a solvent, etc. The advantage of the method shown in Fig. 12 is that the connection between the low dielectric layer such as glass and the conductive paste at the upper surface of the laminate and the 91m edge, which is required by the conventional method of forming terminals with conductive paste, is improved. m
Since it does not require mounting, it is easy to work with and reduces the number of steps. Furthermore, the 51st
If shapes such as those shown in Figures 6, 8, and 9 are used, the contact area with the material will be reduced and the stray capacitance will be further reduced.Figure 9 shows the clip (support). Make a hole near the center of the
The contact rki side with the laminate (1) is made smaller.

なお、第6図、@8図、第13図、 l!14図はクリ
ップのガタッキを押えるために突起の形状を極々変化さ
せたものである0 藁5図、第6図、第8図、第9図、第13図「及び第1
4図については、クリップ製造工程途中のプレス加工時
に同時加工が可能なものであり。
In addition, Figure 6, @Figure 8, Figure 13, l! In Figure 14, the shape of the protrusion has been drastically changed to suppress the looseness of the clip.
Regarding Figure 4, simultaneous processing is possible during press processing during the clip manufacturing process.

きわめてコストを安く製作できるものである。It can be manufactured at extremely low cost.

第101及び第11図は単にクリップ(2)をコ字形と
しないで一各棟回路構成基板に応じて挿入用埋込用等に
対応できる応用展開例を示している0以上の結果1例え
は!g51Nに乃(すような寸法のクリップ(胸を用い
ると、浮遊容量は約IP?と導体ペーストの/にするこ
とができる。
Figures 101 and 11 show an example of application development in which the clip (2) is not simply U-shaped but can be used for insertion or embedding depending on each circuit board. ! Using a clip (chest) with dimensions like g51N, the stray capacitance can be approximately IP? and / of the conductive paste.

0 以上実施例に詳述したような構成の本発明クリップ警用
いると、コンデンサ機能を有する固体積層電子回路部品
を、十分な電気時性を持ちかつ容易に各種回路構成基板
へ実装すること−できる。
0 By using the clip of the present invention having the structure detailed in the embodiments above, a solid laminated electronic circuit component having a capacitor function can be easily mounted on various circuit component boards with sufficient electrical stability. can.

【図面の簡単な説明】[Brief explanation of the drawing]

編1図は、固体積層゛1子(ロ)路部品のコンデンサ形
成部分の平面図、第2図は同断面図、第3図は積層体上
に形成さnる電子回路配置図、@4図は電子回路の回路
図、@5図及至第11図は本発明クリップを例示するも
のであって、講5(1)は積層体%(6)は側面部、(
迄はクリップ、a和は空気層である◎ 弁理士 山 本   孝・・ 手 続 補 正 書(方式) l 事件の表示 昭和57年 特許 願第 002172  号2発明の
名称 固体積層電子i踏部品用クリップ 3 補正をする者 事件との関係   特許    出願人住 所 大阪府
門真市大字門真1006番地4代理人 昭和57 年 4 月 9 日(発送日 昭和57年4
月27日)明細書第6頁第11行目〜第14−行目「纏
も図・・・・・・・図である。」とあるな、[第5図乃
至第14図れ本発明に係るクリックを例示するものであ
って、第5図乃至第14図の休)はクリップ側面図、第
5図乃至第14図の(ロ)はクリップ平面図である。」
と訂正する。 手 続 補 正 書(自発) 特許庁長官島田春樹殿 l !11件の表示 昭和57年 特許 願第 002172  号2発明の
名利。 固体積層電子回路部品用クリップ 3 補正をする者 事件との関係    特許    出願人住 所 大阪
附門真市大字門真1006番地氏 名 (582)  
松下知器産業株式会社(名称) 4代理人 昭和   年   月   日(発送日 昭和  年 
 月   日)鈎補正の内容 (1)明細書第3頁第1行目〜第2行目r @子(6)
(6)(7)(9)(X J ト4 ルt、r m (
−(6) (8)(7) (8> (9)(jQ Jと
訂正する。 (り  明細書#!4頁館3行目〜第4行目「第5図乃
至第11図」とあるを、「飢5図乃至第14図」と訂正
する。 (3)明細書第6頁第1行目 「導体ペーストの」とあるを、[導体ペーストにて桐成
した場合の」と訂正する。 (4)  図面の第1図及び第7−←)(B)を別紙の
とおシ訂正する。
Figure 1 is a plan view of the capacitor forming part of the solid laminate circuit component, Figure 2 is a sectional view of the same, and Figure 3 is a layout diagram of the electronic circuit formed on the laminate. The figure is a circuit diagram of an electronic circuit, and Figures 5 to 11 illustrate the clip of the present invention.
Up to is a clip, and a sum is an air layer.◎ Patent attorney Takashi Yamamoto... Procedural amendment (method) l Indication of the case 1982 Patent application No. 002172 2 Name of invention For solid laminated electronic i-step parts Clip 3 Relationship with the case of the person making the amendment Patent Applicant Address: 1006-4 Kadoma, Kadoma City, Osaka Prefecture Agent April 9, 1982 (Delivery date: April 1982)
April 27th) Page 6 of the specification, lines 11 to 14, it says, ``The matte is also a figure...'' 5 to 14 are side views of the clip, and FIGS. 5 to 14 (b) are plan views of the clip, illustrating such a click. ”
I am corrected. Procedural amendment (voluntary) Haruki Shimada, Commissioner of the Patent Office! Showing 11 items 1982 Patent Application No. 002172 2 Benefits of the invention. Clip for solid-state laminated electronic circuit components 3 Relationship with the amended case Patent Applicant Address 1006 Kadoma, Kadoma City, Osaka Name (582)
Matsushita Chiki Sangyo Co., Ltd. (Name) 4 agents Month, Day, Showa (Delivery date Showa)
Date) Contents of hook correction (1) Specification page 3, lines 1 to 2 r @child (6)
(6) (7) (9) (X J to4 t, r m (
- (6) (8) (7) (8> (9) (j Q J (3) In the first line of page 6 of the specification, the phrase “of conductor paste” has been corrected to read “When paulownia is formed with conductor paste.” (4) Figures 1 and 7-←)(B) of the drawings shall be corrected as shown in the attached sheet.

Claims (1)

【特許請求の範囲】[Claims] (1)  内部電*1−と誘電体1−と禎1m して4
成した少くともひとつのコンデンサ機能を有する横1一
体において、該積層体の内部電極と接続していない少な
くともひとつ以上の外tf[続用の端子引出11極とし
て、該槓)一体の側面部へ当接する部分が該積層体の誘
電体より低い誘嵯率の材料ノーを介在できるようにした
ことを%鹸とする面体積層電子回路部品用クリップO
(1) Internal electric current *1-, dielectric material 1- and 1m long and 4
At least one external TF that is not connected to the internal electrode of the laminate [as a terminal drawer for connection 11 poles] is attached to the side surface of the integrated body, which has at least one capacitor function. A clip O for surface-laminated electronic circuit components in which the abutting part can be interposed with a material having a dielectric constant lower than that of the dielectric of the laminate.
JP217282A 1982-01-09 1982-01-09 Clip for solid state laminated electronic circuit part Pending JPS58119622A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP217282A JPS58119622A (en) 1982-01-09 1982-01-09 Clip for solid state laminated electronic circuit part

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP217282A JPS58119622A (en) 1982-01-09 1982-01-09 Clip for solid state laminated electronic circuit part

Publications (1)

Publication Number Publication Date
JPS58119622A true JPS58119622A (en) 1983-07-16

Family

ID=11521941

Family Applications (1)

Application Number Title Priority Date Filing Date
JP217282A Pending JPS58119622A (en) 1982-01-09 1982-01-09 Clip for solid state laminated electronic circuit part

Country Status (1)

Country Link
JP (1) JPS58119622A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7834502B2 (en) 2005-04-04 2010-11-16 Hiromichi Kinoshita Rotating mechanism

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7834502B2 (en) 2005-04-04 2010-11-16 Hiromichi Kinoshita Rotating mechanism

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