JPS58118099A - Controlling device - Google Patents

Abstract

PURPOSE:To increase an amount of preventive maintenance information without damaging the performance, by performing the parity inspection in utilizing a period when no normal operation is performed. CONSTITUTION:A micro instruction read out to a parity inspecting circuit 9 is subjected to a parity inspection, and, when a parity error is detected, the fact that a parity error exists is stored in a parity error storing section 91 and the fact is informed to a scan command circut 10, but the micro instruction itself is inhibited to be inputted into a multiple input-output controlling circuit by a gate 15. After the fact of the parity error is informed to the multiple input- output controlling circuit 6, the fact is reported to a CPU as response information 120 by a reporting circuit 16, and the CPU can make a preventive maintenance work based on the response information 120.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a control device, and more particularly to a control device that is fully equipped with a storage device and is largely controlled by a central processing unit.

In recent years, there has been a remarkable decentralization of hardware functions in information processing devices, and the central processing unit functions as a master controller, and various control devices are installed to control lower-level control.
Most of the things are left up to you. The control device is often equipped with all kinds of storage devices such as tables, microprogram storage devices, stack memories, buffer memories, and circuit state storage circuits.

Conventional control devices of this type include a parity check circuit that performs all parity checks on data read from a built-in storage device, and when the parity check circuit detects a parity error, the fact of the parity error is transmitted to a central processing unit. and an error reporting circuit for reporting errors.

In such a conventional configuration, except during maintenance, the control device controls the storage device R' based on instructions from the central processing unit.
Since parity check is performed only when reading Fr,
The drawback is that there is little information for preventive maintenance and the reliability of the control device is low.

SUMMARY OF THE INVENTION An object of the present invention is to provide a control device that can increase the amount of preventive maintenance information without compromising performance.

The device of the present invention is a control device which is controlled by a central processing unit, and includes a parity check circuit that performs all parity checks on data read from the storage device, and a control device that performs a parity check on data read out from the storage device, and a control device that controls the storage device and the central processing unit. an empty detection circuit that detects that the storage device is not being accessed; and a scanning circuit that scans all addresses of the storage device and sequentially reads out the stored contents to the parity check circuit when the empty detection circuit detects that the storage device is not being accessed. , and a reporting circuit for reporting the fact of the parity error to the outside when the parity side circuit detects a parity error.

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram showing an entire embodiment of the present invention, and FIG. 2 is a block diagram showing the relationship between a higher-level device and a lower-level device in this embodiment.

Referring to FIG. 2, there are three input/output devices 201 to 208, 301 to 308 (not shown), and 4 in this embodiment.
To any number of units from 01 to 408 (not shown) -
Human output control signals 211 to 218 (212 to 217 can control numbering. Each controlled input/output device receives status signals 221 to 228, 321 to 328 (not shown), 4
21 to 428 (not shown) are returned to the corresponding multiple input/output control device 200, 300, 400. These status signals 221-228, 321-2328.421-42
8 is the state of the input/output device in a series of controls based on one input/output command? For example, the signal indicates whether the motor of the magnetic disk device has reached a normal rotation speed, whether or not the back is being energized, and whether data transfer has been completed. Is the multi-person output control device 200, 300, 400 an erroneous signal generated during such a control process? It is reported to the central processing unit 100 as response information 120.

Each input/output Xll control device has a degree of 200, 300.
Similarly to the central processing unit 100, the data processor 400 outputs all addresses 180 and stores them in the main memory 50 based on the memory control signal 140 and the memory response signal 150 thereto.
It is possible to write all of the write data 160 to 0 or to read all of the read data 170 from the main memory device 500.

5- Next, referring to FIG. 1, this embodiment has a control storage circuit 1
, two human output control devices 2.3, a control information storage circuit 4, a command storage circuit 5, a multiple input/output control circuit 6, an empty detection circuit 7, and two parity check circuits 8, 9. , a scan command circuit 10, an address register 11, a scan address register 12, a step circuit 13, and two gates 1.
4. This is a multiple input/output control device including a terminal 15 and a reporting circuit 16. Parity check circuits 8 and 9 include parity error storage units 81 and 91, respectively.

First, at the time of system startup, the central processing unit 100
The same applies to 01 to 408, hereinafter input/output device 2.
A microinstruction 130 that deals with input/output commands to issue all operations to be performed by the microcommands 01 to 208).
is stored in the control storage circuit 1.

During system operation, the central processing unit 100 asynchronously outputs input/output instructions 110' to the instruction storage circuit 5, and the instruction storage circuit 5 stacks all of these instructions.

6- This completed input/output command is sent to the multiple input/output control circuit 6.
In response to an instruction from , the signal is read out to the parity check circuit 8 in a first-in, first-out manner, subjected to a parity check, and then input to the multiplex output control circuit 6 .

In part, each status of the input/output devices 201-208 is notified to the control information storage circuit 4 and the empty detection circuit 7 by eight status signals 221-228. Multiple input/output control circuit 6
When an input/output command is input, the control information storage circuit 4 reads out the status sound of the input/output device related to the input input/output command from among the input/output device states stored in the control information storage circuit 4.

Furthermore, in response to the state of the input/output device read out from the control information storage circuit 4, the multiplexed input/output control circuit 6 passes through the address register 11 and the gate 14 to the control storage circuit 1.
is accessed and read out to the entire parity check circuit 9 of the microinstruction corresponding to the input/output instruction being input.

The parity check circuit 9 performs a parity check on the read microinstruction, and then inputs it to the multiple input/output control circuit 6 via the gate 15. As a result of the parity check in the parity check circuits 8 and 9, if no parity error is detected, the multiplex input/output device 6 sends the input/output control circuit 2 or 3 to the input/output control circuit 2 or 3 according to the input microinstruction. Control signals based on the input/output devices 201 to 204 or 205 to 208 respectively controlled are supplied with input/output control signals 211 to 21.
4 or 215 to 218, and a plurality of input/output devices can all be operated in parallel.

Either parity check circuit 8 or 9 has a parity error b
If i detects a parity error, the parity error storage unit 81 or 91j! to be memorized. The multiplex output control circuit 6 prevents the supply of microinstructions read from the control storage circuit 1 to the input/output control circuits 2 and 3 in response to a signal from the parity error storage section 81 or 91. , informs the reporting circuit 16 of the fact of the parity error.

Now, the human output control circuit 2 or 3 each has a control signal 2
11-214 and 215-218 as input/output devices 201-2
04 and 205 to 208, a part of these control signals 211 to 218, such as the seek operation of the magnetic disk device, is also output to the empty detection circuit 7 to detect the empty detection target item. Set all values. As mentioned above, the status of the input/output device is also reported to the empty detection circuit 7, but the status of this input/output device is the value of the target item set in the empty detection circuit 7, in the above example, While the seek operation of the magnetic disk device is not completed, the empty detection circuit 7 outputs the empty signal 7'.
is sent to the scan command circuit 10 and the multiple input/output control circuit 6.

When the scan command circuit 10 receives the received signal 7', it outputs the scan command 10''f to the step circuit 13, gate 14, and gate 15. (Last address from last run)
starting from , incrementing the scan address register 12;
All addresses in the control storage circuit 1 are cycled through. gate 14
outputs the contents of the food address register 12 to the control storage circuit 1 instead of the address register 111 and stores all the contents of the food address register 12.
9- Scans the response and causes the parity check circuit 9 to extract the entire microinstruction.

A parity check is performed on the microinstruction read out by the parity check circuit 9, and when a parity error is detected, the entire fact of the parity error is stored in the parity error storage section 91, and the scan command circuit 1o is notified. The microinstructions themselves are blocked by gate 15 from entering the multiple output control circuit.

The fact of the parity error reported to the multiplex output control circuit 6 is reported to the central processing unit 100 as response information 120 by the report @ 16, and the central processing unit 100 performs preventive maintenance based on this response information 120. can be taken.

When the multi-person output control circuit 6 receives the empty signal 7', it reads the next microinstruction from the total control storage circuit 1 and repeats the operation as described above.

Therefore, whether or not the multi-control storage circuit 1 is being accessed can be determined by whether or not the empty signal 7' is generated.

In addition, in the non-implemented l+ month, sky detection and scanning -1
0- Although only the control memory circuit 1 is targeted for reading/parity checking, it is easily possible to target only the instruction memory circuit 5 or both the control memory circuit 1 and the instruction memory circuit 50 in the same way. . Further, although the parity error fact is reported to all central processing units 100, it may be reported to other devices such as an operator console or maintenance equipment.

According to the present invention, by adopting the above configuration, a parity check of a storage device is performed only when the control device reads out sound from the storage device based on a command from the central processing unit (during normal operation). Since the parity check can be performed using the time when normal operation is not being performed, the amount of preventive maintenance information can be increased without any loss in performance.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, and FIG. 2 is a diagram showing the relationship of this embodiment with other devices. In the figure, 1... control storage circuit, 2, 3...
...Human output control circuit, 4...Control information storage circuit, 5...Command storage circuit, 6...Multiple input/output control device, 7... Empty detection circuit, 7'/old/
・Empty signal, 8.9・Old...Parity check circuit, 81.9
1...Parity error storage section, 10...
Scan command circuit, 10'... Scan command, 11...
・°...Address register, 12...River/scanning address register, 13...Group/stepping side %, 14.15...
...gate, 16...report circuit, 1oo old
・Central processing unit, 11o・Group・I/O command, 12o・
Old...Response information, 130...Micro instruction, 2
00,300. I prisoner 400...Multiple input/output control device, 201-208...Input/output device, 21
1-218...Person output control signal, 221-22
8... Status signal, 5oo... Raw memory device! , 140... memory control signal, 15o...
...Memory response signal, 160...Write data, 170...Read data, 18o...Group...
address. Mine Z box

Claims (3)

[Claims] (1) In a control device that is fully equipped with a storage device and is controlled by a central processing unit, a parity check circuit that performs all parity checks on data read from the storage device and the storage device are not accessed. an empty detection circuit for detecting the parity check circuit; 1. A control device comprising: a reporting circuit for reporting the fact of a parity error to the outside when the parity check circuit detects all parity errors. (2) The control device is an input/output control device that controls all input/output devices, and the storage device is a command storage circuit that stores all input/output instructions from the central processing unit. The control device described in (1). (3) The control device is an input/output control device that controls an input/output device, and the storage device is a control storage circuit that stores in advance microinstructions corresponding to input/output instructions. The control device according to paragraph (1).