JPS5811731B2 - hand tai souchi no seizou houhou - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention makes it possible to completely form an ohmic contact between an impurity diffusion layer provided in a semiconductor substrate and a wiring electrode made of aluminum (AI), etc. in the production of a semiconductor integrated circuit. The present invention relates to a method of manufacturing a semiconductor device that is free from the risk of short-circuiting between interconnections.

In the production of semiconductor integrated circuits, forming an ohmic contact between an impurity diffusion layer provided in a silicon substrate and an AI film for wiring is a very important process. An insulating layer corresponding to a bolt may be formed, which has a significant effect on yield, especially as the degree of integration becomes higher and the size of the contact hole becomes smaller.

From the conventional contact window opening process to the AI wiring process,
To explain with reference to FIGS. 1A to 1D, first, a silicon oxide film (hereinafter referred to as 5i02 film) is formed on the silicon substrate 1 and on the high concentration impurity diffusion layer 2 formed in the silicon substrate 1.
A photosensitive resin pattern (hereinafter referred to as a photoresist pattern) 4 is formed on the 5i02 film 3 in order to form a contact window in the 5i02 film 3 on the diffusion layer 2 (FIG. 3A).

Next, using the photoresist pattern 4 as an etching mask, the 5i02 film 3 is etched on to form the contact hole 5.
(Figure B).

After this, the photoresist pattern 4 is removed (C) in the same figure.
Thereafter, it is cleaned and an AI film 6 is deposited (D in the same figure).

However, from step B of removing photoresist pattern 4 to step A
A thin insulating layer 1 is naturally formed on the exposed surface of the diffusion layer 2 up to step C of depositing the I film 6, and the AA vapor deposited film 6 and the diffusion layer 2 are separated from each other.

Although the film thickness of this insulating layer T is very thin, several tens of angstroms, it is difficult to break down during heat treatment at about 450 to 550°C to make ohmic contact between the Al film 6 and the diffusion layer 2. When the number of contact holes increases due to higher integration, the yield rate is significantly adversely affected.

The present invention was made in view of the conventional problems, and by first forming a thin alloy layer only on the surface of the impurity diffusion region, ohmic contact between the impurity diffusion layer and the metal wiring is facilitated, and integrated circuits can be improved. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the yield when the degree of integration is increased, the size of contact holes is reduced, and the number of contact holes is increased.

The present invention will be described below based on examples together with the drawings.

2A to 2F are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device of the present invention, in which the steps are shown on the silicon substrate 11 and on the high concentration impurity diffusion layer 12 formed in the silicon substrate 11. 5i02 film 13 is formed, and the above-mentioned Si on the diffusion layer 12 is
A photoresist pattern 14 is formed on the O2 film 13 (
Figure A).

In this state, using the photoresist pattern 14 as an etching mask, the 5i02 film 13 is etched with, for example, a hydrofluoric acid-based etching solution to expose a part of the diffusion layer 12 and form a 510g film pattern 15 (FIG. )
.

Next, the top of the photoresist pattern 14 and the exposed diffusion layer 1 are
Thin A with a film thickness of 50 to 2000 augestroms on top of 2.
A J film 16 is deposited (C in the same figure).

Then, while removing the photoresist pattern 14,
The AI film 16 on the photoresist pattern 14 is lifted on to obtain an AI film pattern 1T (FIG. D).

Then, heat treatment is performed at 450 to 1000°C to form the diffusion layer 1.
A shallow alloy layer (alloy region) 1B of silicon and Al film pattern 17 is formed (E in the same figure).

Finally, in order to draw out the electrode from the diffusion layer 12, AI
A wiring film 19 is deposited (FIG. F).

In this case, even if a thin insulating film layer is formed on the surface of the alloy region 18, since this insulating film layer is a reaction product of the alloy layer 18, heat treatment at 450 to 550° C. is performed to separate the diffusion layer 12 and the AJ wiring. The film 19 can make complete ohmic contact.

According to the method shown in FIG. 2, 5i02
5if because there is no Al film pattern 17 on the film 15.
No AJ remains on the t-film 15, and there is no risk of short-circuiting between the AI wiring films 19.

As explained above, since the method for manufacturing a semiconductor device of the present invention forms a shallow alloy layer on the surface of the impurity diffusion layer, the insulating layer naturally formed on the alloy layer can be removed by low-temperature heat treatment. Ohmic contact between the diffusion layer and the wiring metal can be easily formed by removing the previously thin insulating film, and as integrated circuits become more highly integrated, contact holes become smaller and more numerous. In particular, it is highly effective in eliminating poor contact between the wiring metal and the impurity diffusion layer and improving the manufacturing yield of integrated circuits.

Furthermore, in the present invention, a metal film for alloying is formed only on the impurity diffusion region, and unnecessary metal due to alloying does not remain on the insulating film.

Therefore, there is no risk of short circuits occurring between wiring metals, which is convenient for manufacturing high-density semiconductor devices.

[Brief explanation of drawings]

1A to 1D are process sectional views showing a conventional semiconductor device manufacturing method, and FIGS. 2A to 2F are process sectional views showing an embodiment of the semiconductor device manufacturing method of the present invention. 11...Silicon substrate, 12...Impurity diffusion layer, 13...5i02 film, 14...
...Photoresist pattern, 16...Al film,
18...Alloy region, 19...AJ wiring film.

Claims (1)

[Claims] 1. A step of forming an insulating film having an opening above the impurity diffusion region on a surface of a semiconductor substrate having an impurity diffusion region; a step of forming a metal film only on the surface of the impurity diffusion region exposed to the opening; A heat treatment step of forming an alloy layer of the semiconductor substrate and the metal film on the surface of the impurity diffusion region in the opening, and a step of selectively forming wiring electrodes on the alloy layer and the insulating film. A method for manufacturing a featured semiconductor device.