JPS6122031B2 - - Google Patents
Info
- Publication number
- JPS6122031B2 JPS6122031B2 JP1560179A JP1560179A JPS6122031B2 JP S6122031 B2 JPS6122031 B2 JP S6122031B2 JP 1560179 A JP1560179 A JP 1560179A JP 1560179 A JP1560179 A JP 1560179A JP S6122031 B2 JPS6122031 B2 JP S6122031B2
- Authority
- JP
- Japan
- Prior art keywords
- etching
- film
- metal
- substrate
- metal film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 26
- 238000005530 etching Methods 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 238000000034 method Methods 0.000 claims description 15
- 239000004065 semiconductor Substances 0.000 claims description 9
- 238000000992 sputter etching Methods 0.000 claims description 9
- 229910045601 alloy Inorganic materials 0.000 claims description 4
- 239000000956 alloy Substances 0.000 claims description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 229910052782 aluminium Inorganic materials 0.000 description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 5
- 238000009826 distribution Methods 0.000 description 4
- 238000004544 sputter deposition Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012495 reaction gas Substances 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
Description
【発明の詳細な説明】
本発明は基板上に被着された金属膜のエツチン
グ方法の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improved method for etching metal films deposited on substrates.
集積回路（IC）等の半導体装置の製造に於い
て、極めて微細な電極或るいは配線等の金属パタ
ーンを形成するに当つては、反応性スパツタエツ
チング等のドライエツチング法が用いられる。 In the manufacture of semiconductor devices such as integrated circuits (ICs), dry etching methods such as reactive sputter etching are used to form extremely fine metal patterns such as electrodes or wiring.
従来、この反応性スパツタエツチングの実施に
際しては、半導体基板上に被着された被エツチン
グ金属膜上に、直接レジストのマスクパターンを
形成し、これをスパツタリング装置内に配置し
て、該レジストをマスクとして被エツチング金属
膜を選択エツチングすることが行なわれている。 Conventionally, when performing this reactive sputter etching, a resist mask pattern is formed directly on a metal film to be etched deposited on a semiconductor substrate, and this is placed in a sputtering device to remove the resist. Selective etching of a metal film to be etched is carried out using a mask.
しかしながら、このような方法においては、被
処理半導体基板の表面においてその周縁部近傍と
中央部とでは、スパツタリング時の電界分布、温
度分布及び反応ガス分布（供給量分布）等が異
り、特に該被処理基板の周縁部近傍では電界の集
中、反応ガスの供給、交換量がその中央部に比較
してはなはだ大きい。このため該被処理基板の周
縁部近傍と中央部とでは、被エツチング金属膜の
被エツチング量（エツチングレート）に大きな差
を生じ、該被処理基板の周縁部の金属膜は、該基
板の中央部に比較して過剰にエツチングされてし
まう。 However, in such a method, the electric field distribution, temperature distribution, reaction gas distribution (supply amount distribution), etc. during sputtering are different between the vicinity of the periphery and the center of the surface of the semiconductor substrate to be processed. Near the periphery of the substrate to be processed, the concentration of the electric field, the supply of reactive gas, and the amount of exchange are much larger than in the center. For this reason, there is a large difference in the amount of etching (etching rate) of the metal film to be etched between the vicinity of the periphery and the center of the substrate, and the metal film at the periphery of the substrate is at the center of the substrate. The etching is excessive compared to the other parts.
本発明は上記問題点に鑑み、被処理基板上に被
着された金属膜全面のエツチングレートを一定す
るような反応性スパツタエツチング方法を提供し
ようとするものである。 In view of the above-mentioned problems, the present invention provides a reactive sputter etching method that makes the etching rate constant over the entire surface of a metal film deposited on a substrate to be processed.
このため本発明によれば、基板上に被着された
金属膜上に絶縁層を介してエツチングマスクを配
設した後、前記金属膜をスパツタエツチングする
ことを特徴とするエツチング方法が提供される。 Therefore, according to the present invention, an etching method is provided, which comprises disposing an etching mask on a metal film deposited on a substrate via an insulating layer, and then sputter etching the metal film. Ru.
以下本発明を実施例により詳細に説明する。 The present invention will be explained in detail below using examples.
第１図乃至第４図は本発明によるエツチング処
理法の一実施例を示す工程断面図である。 1 to 4 are process cross-sectional views showing one embodiment of the etching treatment method according to the present invention.
本発明によれば、例えばIC等の半導体素子の
電極或るいは配線パターンを形成するに際して、
先づ第１図に示すように、素子の形成を完了した
（素子の形成状態は図示せず）シリコン基板１表
面を覆う二酸化シリコン（SiO2）層２に通常のフ
オトエツチング法により電極コンタクト用窓３を
形成した後、第２図に示すように該半導体基板１
の上面全体に蒸着或るいはスパツタリングにより
約１〔μｍ〕程度のアルミニウム（Al）膜４を
被着形成し、更に該アルミウム膜４表面に陽極酸
化或るいは酸素（O2）プラズマによるアツシング
等により100〜300〔Å〕程度の厚さに酸化アルミ
ニウム層５を形成する。次いで第３図に示すよう
に該酸化アルミニウム層５に厚さ１〔μｍ〕程度
のフオトレジスト膜からなるエツチングマスク６
を形成させた後、該シリコン基板１をスパツタリ
ング装置内に配置し、0.1〔Torr〕程度の圧を有
せしめた四塩化炭素（CCl4）或るいは三塩化硼素
（BCl3）等の反応ガス中に於いて該基板の高周波
スパツタエツチングを行う。この結果第４図に示
すようにシリコン基板１上にアルミニウムの電極
或るいは配線パターン７を形成させる。 According to the present invention, for example, when forming electrodes or wiring patterns of semiconductor elements such as ICs,
First, as shown in FIG. 1, a silicon dioxide (SiO 2 ) layer 2 covering the surface of a silicon substrate 1 after the formation of an element has been completed (the state of formation of the element is not shown) is etched for electrode contact by the usual photo-etching method. After forming the window 3, the semiconductor substrate 1 is removed as shown in FIG.
An aluminum (Al) film 4 of approximately 1 [μm] thickness is formed on the entire upper surface by vapor deposition or sputtering, and the surface of the aluminum film 4 is then subjected to anodic oxidation or ashing with oxygen (O 2 ) plasma, etc. The aluminum oxide layer 5 is formed to a thickness of about 100 to 300 Å. Next, as shown in FIG. 3, an etching mask 6 made of a photoresist film with a thickness of about 1 [μm] is applied to the aluminum oxide layer 5.
After forming the silicon substrate 1, the silicon substrate 1 is placed in a sputtering device, and a reactive gas such as carbon tetrachloride (CCl 4 ) or boron trichloride (BCl 3 ) is heated to a pressure of about 0.1 [Torr]. In the process, the substrate is subjected to high frequency sputter etching. As a result, an aluminum electrode or wiring pattern 7 is formed on the silicon substrate 1 as shown in FIG.
前述の如く、反応性スパツタエツチングに於け
る半導体基板の中央部と周辺部に於けるアルミニ
ウム膜のエツチング量の不均一性は、エツチング
開始の時期に発生せしめられるが、前記のように
アルミニウム膜上に形成された酸化アルミニウム
層は、反応ガスのラジカルで叩かれると、酸化ア
ルミニウム層とアルミニウム膜との界面にラジカ
ルの電荷を中和せしめるような負の電荷が蓄積さ
れ、該電荷の量は酸化アルミニウム層表面を叩く
前記反応ガスのラジカル量に比例する。従つてエ
ツチング開始時期により多くのラジカルの集中す
る半導体基板周辺部には、より多く負電荷が蓄積
されラジカルの衝突量をより多く抑制するように
なるので、エツチング開始時期に於けるアルミニ
ウム膜のエツチングレートは基板内に於いて均一
化され、基板の周辺部に於いて、従来発生してい
た電極或るいは配線パターンのオーバーエツチン
グの発生がなくなる。 As mentioned above, non-uniformity in the amount of etching of the aluminum film between the center and the periphery of the semiconductor substrate in reactive sputter etching occurs at the beginning of etching. When the aluminum oxide layer formed thereon is bombarded with radicals from the reactive gas, negative charges are accumulated at the interface between the aluminum oxide layer and the aluminum film to neutralize the charges of the radicals, and the amount of the charges is It is proportional to the amount of radicals of the reaction gas hitting the surface of the aluminum oxide layer. Therefore, more negative charges are accumulated in the peripheral area of the semiconductor substrate where more radicals are concentrated at the time of starting etching, and the amount of collision of radicals is suppressed to a greater extent. The etching rate is made uniform within the substrate, and over-etching of electrodes or wiring patterns that conventionally occurs at the periphery of the substrate is eliminated.
上記実施例はシリコン基板上に形成されたアル
ミニウム膜のエツチングについて説明したが、本
発明の方法は上記以外の他の金属或るいは合金膜
上に、同種金属又は異種金属の酸化膜層を形成せ
しめて実施した場合にも同様の効果が得られる。 Although the above embodiment describes the etching of an aluminum film formed on a silicon substrate, the method of the present invention can form an oxide film layer of the same kind of metal or a different kind of metal on other metals or alloy films other than those mentioned above. A similar effect can be obtained if the method is implemented at least.
又本発明のエツチング方法はシリコン基板以外
の他の基板上の金属膜のエツチングにも勿論適用
可能である。 Furthermore, the etching method of the present invention can of course be applied to etching metal films on substrates other than silicon substrates.
以上説明したように本発明によれば反応性スパ
ツタエツチングに於いて、基板全面に形成されて
いる金属膜に対して均一なエツチングレートが得
られるので、微細な電極或るいは配線パターン
を、基板全面にわたつて正確に形成することがで
き、、半導体装置の製造歩留りの向上、信頼性の
向上に極めて有効である。 As explained above, according to the present invention, in reactive sputter etching, a uniform etching rate can be obtained for the metal film formed on the entire surface of the substrate. It can be formed accurately over the entire surface of the substrate, and is extremely effective in improving the manufacturing yield and reliability of semiconductor devices.
第１図乃至第４図は本発明によるエツチング方
法の実施例を示す工程断面図である。
図に於いて、１はシリコン基板、２はSiO2
層、３はコンタクト用窓、４はアルミニウム膜、
５はAl2O3層、６はレジスト膜、７は配線パター
ン。
1 to 4 are process cross-sectional views showing an embodiment of the etching method according to the present invention. In the figure, 1 is a silicon substrate, 2 is a SiO 2
layer, 3 is a contact window, 4 is an aluminum film,
5 is an Al 2 O 3 layer, 6 is a resist film, and 7 is a wiring pattern.
Claims (1)
し、該金属膜あるいは合金膜上に次の反応性スパ
ツタエツチングにおけるラジカルの衝突により、
当該ラジカルの衝突量を抑制する負電荷を界面に
蓄積するための、同種金属又は異種金属の表面酸
化膜を形成し、更に、該表面酸化膜上にエツチン
グマスクを形成した後に反応性スパツタエツチン
グを施し、該表面酸化膜に引き続き前記金属膜あ
るいは合金膜をエツチングすることを特徴とする
金属膜のエツチング方法。1. A metal film or alloy film is formed on a semiconductor substrate, and by collision of radicals in the next reactive sputter etching on the metal film or alloy film,
A surface oxide film of the same kind of metal or a different kind of metal is formed in order to accumulate negative charges at the interface to suppress the amount of collision of the radicals, and an etching mask is formed on the surface oxide film, followed by reactive sputter etching. 1. A method for etching a metal film, which comprises etching the metal film or alloy film subsequent to the surface oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1560179A JPS55107781A (en) | 1979-02-13 | 1979-02-13 | Etching method for metal film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1560179A JPS55107781A (en) | 1979-02-13 | 1979-02-13 | Etching method for metal film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55107781A JPS55107781A (en) | 1980-08-19 |
| JPS6122031B2 true JPS6122031B2 (en) | 1986-05-29 |
Family
ID=11893233
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1560179A Granted JPS55107781A (en) | 1979-02-13 | 1979-02-13 | Etching method for metal film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55107781A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3400918B2 (en) | 1996-11-14 | 2003-04-28 | 東京エレクトロン株式会社 | Method for manufacturing semiconductor device |
-
1979
- 1979-02-13 JP JP1560179A patent/JPS55107781A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55107781A (en) | 1980-08-19 |
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