JPS58112372A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor device appropriate for high density formation with a narrow gate width, by using an ion implanted mask which does not have adverse influences to a substrate due to positional slippages and thermal denaturations. CONSTITUTION:On a semi-insulating compound semiconductor substrate 1, an Al nitride film 12 is formed into a film thickness of 4,000Angstrom , and then a window for a self-alignment type FET forming region is opened. Next, Si<+> ions are implanted into the FET forming region by an ion implantation, with the AlN film 12 as a mask. Thereafter, with the mask deposited, an SiO2 film 13 is deposited as a protection film on the semiconductor substrate 1, and thereafter an annealing is performed resulting in the formation of an N type active layer 3. This SiO2 film 13, if thin approx. 1,000Angstrom , does not generate the thermal denaturation, while it is rather effective to prevent the denaturation due to As dissociation, etc. on the surface of a compound semiconductor substrate of GaAs, etc. by a heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more specifically, to a method for manufacturing a semiconductor device, and more specifically, to perform self-alignment (self-alignment) on a compound semiconductor substrate.
The present invention relates to a method for manufacturing a semiconductor device that allows a field effect transistor (FET) of the lf aligmm@nt- type to be formed with high precision without misalignment of a mask pattern during ion implantation.

(2) Background of the Technology With the recent development of semiconductor integrated circuits, it is necessary to manufacture semiconductor devices with higher density and higher reliability.

In the manufacture of so-called "cross-dart" field effect transistors using compound semiconductors such as GaAs, it is necessary to make the gate width as narrow as possible to achieve high density. Therefore, if a so-called self-aligned structure in which a high-density region is formed by ion implantation using the r-) electrode as a mask is used, a problem arises in mask alignment. In other words, in order to form such a field effect transistor with a dirt width narrower than the current one, it is necessary to improve the alignment accuracy of the ion implantation mask used to form the active region and the source/drain high concentration regions. It becomes a trap that requires improvement.

(3) Conventional technology and problems ! Figure 1 shows a self-aligned structure in the prior art.

In order to explain the manufacturing method of a heavy field effect transistor, this is a diagram showing a cross section of the main part. First, a semi-insulating compound semiconductor (GaAm) base
Silicon dioxide (8102) film 2 is placed on Ll to a thickness of about 40 mm.
001, and then a window for the PET formation region is opened (see figure (a)).The thickness of the 8102 film 2 is such that it can be sufficiently effective as a mask in ion implantation. , the above 5in2! Using #2 as a mask, silicon ions (8
1") is implanted by ion implantation using conventional techniques.

After that, the 8102 film 2 used as a mask was processed.

Then, a protective film (810□ film) with a thickness of 100 OX is attached to the surface of the semiconductor substrate, and then annealing is performed to activate the silicon ions to be implanted, and nW! An r-to-electrode &4 is formed in the n-type region above the ridge where the FIT formation region (active layer) 3 is formed (same (b)).
).

After that, a 5102 film is again deposited as an ion implantation mask, a window is opened in the region where the high concentration layer is to be formed, and then silicon ions (81") are implanted to a high degree of depth using the ion implantation method using a conventional technique. (Figure (C)).

Next, after removing the ion implantation mask 5tO2 film 5, a StO□ film (not shown) is deposited on the semiconductor substrate 1 as a protective film, and then annealing is performed to form an n+ high concentration layer 6.7. Then, after removing the protective film (sto2 film), a source electrode 8 and a drain electrode 9 are formed in the high concentration regions 6 and 7 for the source and drain, respectively, to create an FET (FIG. 2(d)). In the above-mentioned conventional technology, as described below, the mask alignment accuracy in forming an ion implantation mask is usually limited to 1 to 2 μm, so there is a drawback that the mask may be misaligned.

That is, when the S content 0□ film 5 is deposited as a mask in the ion implantation for forming the high concentration layer shown in FIG. 1(C), and then the high concentration layer forming region is etched,
As shown by the broken line in the same figure, the mask/quantity turn may shift. This misalignment of the mask-to-arm turn is caused by the difference between the n-type layers 3 and 1.
If a misalignment occurs with the layer 6.7, and this misalignment occurs in the r-) width direction, the effect of reducing the source/drain extraction resistance will be diminished in that FET. (e.g. #-15μm or less), completed FET
In the case of an integrated circuit, the characteristics of the integrated circuit are unstable and the integrated circuit cannot operate normally, which causes problems in terms of manufacturing yield and device reliability.

On the other hand, in order to prevent the mask from shifting, the SiO2 film 2 shown in FIG. It is possible to reuse it as

However, when the thick 5102 film is connected to a compound semiconductor substrate such as GaAs, it causes significant thermal denaturation due to the generation of internal stress. There is a serious problem in that the portions of the substrate surface that are in contact with the sto and ferrules become electrically conductive. Therefore, the force-measure method cannot be used to solve the above-mentioned mask-quantity turn deviation.

As explained above, in the conventional technology, it is not possible to solve the misalignment of the ion implantation mask, which not only leads to a decrease in the reliability of semiconductor devices, but also hinders the increase in the density of integrated circuits. It is also °.

(4) Purpose of the Invention In view of the above-mentioned problems in the prior art, the present invention provides an ion implantation mask that does not adversely affect the substrate due to positional deviation and thermal denaturation. An object of the present invention is to provide a method for manufacturing a semiconductor device suitable for

(5) Structure of the Invention In order to achieve the above object, the inventor of the present application focused on the fact that 90nm aluminum (A/N) does not cause heat consumption in compound semiconductor substrates, and based on this fact, the inventor of the present application @ AJN
Provided is a method for manufacturing a semiconductor device, characterized in that a film is commonly used as an ion implantation mask for forming a quantitatively active layer and an n+ type high degree layer. Note that thermal denaturation by AjN will be explained in the following examples.

(6) Embodiment of the Invention Figure 2 is a cross-sectional view of the main parts of a semiconductor device for explaining an embodiment of the method of the present invention. show.

Referring to the stripe diagram 2, an aluminum nitride (mujN) film 12 is coated on a semi-insulating compound semiconductor substrate 1 with a film thickness of, for example, 4,000 yen.
The film is formed to have a film thickness of X, and a window for a self-aligned field effect transistor formation region is opened.

It should be noted that such mucking can be easily accomplished using conventional machining and cutting techniques.

Next, as in the prior art, silicon ions (s
t'') using the AJN film 12 as a mask, the FET is
The formation region is implanted by ion implantation (Fig. 2(a)).
').

After that, silicon dioxide (8102) is applied as a protective film to the surface of the car pattern semiconductor substrate l with the mask 12 still attached.
After depositing the film 13, annealing is performed to form the n-type active layer 3.
((b) in the same figure). This S io2 film 13 is
Although not essential in the present invention, if it is as thin as about 1000X, it will not cause any heat costs as described below, but it is more effective to prevent degeneration due to dissociation of As on the surface of a compound semiconductor substrate such as GaAs due to heat treatment. effective.

The reason why it is possible to perform IT annealing with the mask 12 attached is because as shown in FIG.

Figure 3 shows 5102 or AJN! ! When used as a membrane,
This is a diagram showing the dependence of the activation rate of implanted ions on the film thickness after the fcGmAs substrate is coated with the protective film and heat treated after ion implantation, and I is 810.
Activation rate when covered with A/N, and ■ indicate activation rate when covered with A/N, respectively.

Referring to the figure, AjN ll [the activation rate during use is 80-
This shows that there is no heat cost caused by the AJN film. On the other hand, the activation rate when using 5so2II is 0.1ttrII (-If at D@thickness is 10
However, if the film thickness is larger than that, the activation rate increases again at ζ and stabilizes at a value of 140%. When the activation rate exceeds 100%, it means that more carriers are generated than the number of implanted ions, and therefore indicates that the substrate is fervent.

As mentioned above, since AIN causes thermal denaturation, there is no need to remove it before annealing, unlike Sl02g in the prior art, and therefore, the problem of misalignment of nine mask turns, which is a problem in the prior art, is avoided. is resolved.

As mentioned above, after the n-type active layer was formed by annealing with an AJN ion implantation mask that does not cause thermal degeneration regardless of the film thickness (Fig. 1112)), an annealing preservation film (8102 film) was formed. 13 is removed, and then a gate electrode 4 is formed on the n-type active layer, and then high-concentration SI+ is implanted by ion implantation as the entire 12 parts of the AAIN film 12 still attached (FIG. 1(e)). )--Next, a 5LO2 film, which is thin enough not to cause thermal denaturation, is attached to the surface of the vehicle heavy semiconductor substrate as a protective film and then annealed to form an n+ high concentration layer 6.7 in a self-aligned manner.

Finally, the 5IO2 film 11 is removed, and source and drain electrodes 8.9 are formed on the n+ high concentration layer (FIG. 4(d)).

(7) Effects of the Invention As explained above, according to the method of the present invention, a self-alignment type FET can be formed without misalignment of the ion implantation mask. The width has also been reduced from the conventional 5 μm to about 1 μm in the present invention! It becomes possible to reduce the size to L, which not only contributes to higher density of integrated circuits (LSI, VLSI), but also improves the reliability of semiconductor devices, which has a great effect on semiconductor 1k111 manufacturing.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a semiconductor device for explaining a method of manufacturing a self-alignment field effect transistor in the prior art, and FIG. 2 is a cross-sectional view of a semiconductor device for explaining a method of manufacturing a field effect transistor according to the present invention FIG. 3, which is a sectional view of the main part of the device, is an l/# diagram showing the dependence of the activation rate of implanted ions in the GaAs substrate on the film thicknesses of the silicon dioxide film and the aluminum nitride film. 1...Compound semiconductor substrate, 2.5.13...Silicon dioxide film, 3...mli active layer, 4...Dart electrode, 6.7...n+high II! 8... Source electrode, 9... Drain electrode, 12... Aluminum nitride film. Patent applicant represented by Fujitsu Limited Patent attorney Hiroshi Matsuoka 1. ．． ．． ．． :,・'C”
ljj Figure 1; l゛(b) Figure 1(d Figure 2(Q)

Claims (1)

[Claims] In a method for forming a field effect transistor on a compound semiconductor substrate, an aluminum nitride film is deposited on the semiconductor substrate, and a window for forming an element region is opened using the aluminum nitride film as a mask. After that, a protective film is attached to the surface of the substrate and heat treatment is performed to form an active layer region. After removing the protective film, a gate electrode is formed in the region, and then a gate electrode is formed in the region. Impurity implantation is carried out using the aluminum ζ nitride film and the dirt electrode as one mask, and after that, a protective film is attached to the surface of the wrinkled semiconductor substrate, and a step of forming a source/drain high conductivity region by heat treatment is performed, and the above protective film is removed. 1. A method of manufacturing a semiconductor device, comprising the step of forming source and drain electrodes in a high concentration region.