JPS58111434A - High-speed switch circuit - Google Patents

Abstract

PURPOSE:To attain excellent operation even for capacitive load such as floating capacitance, by providing an MOS-FET for turning-on/off operations of switching and performing the switching with a low impedance to the load. CONSTITUTION:When an input signal is inputted to a signal input terminal 9, a gate voltage compensating the leading is applied to a gate of the MOS-FET10 via a pulse transformer 11 and a diode 12 to turn on the FET10 and to short- circuit both ends of a load 4. When the input signal is set on next, a gate voltage driving a switching element 15 via a pulse transformer 16 is given to turn on the element 15, allowing to turn off the gate voltage of the FET10 forcedly and to quicken the off-operation of the FET10.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a high-speed switch circuit that requires direct current insulation and is used to switch the voltage of a load at high speed.

Conventionally, there have been circuits of this type as shown in FIGS. 1 and 2. In Figure 1, (1) is a power supply, (2) is a protection resistor, (3) is a bipolar transistor, (4) is a load, (5) is a base current limiting resistor, 6) is a negative current circuit, and (7) is a load. ) is a transformer, (8) is a control circuit, and (9) is a signal input terminal.

In Fig. 2, the same symbols as in Fig. gJ1 indicate the same parts, Ill is MO8+FET, (111 is a pulse transformer), and the control circuit (8) in Fig. 1.2.
, the bipolar transistor (3), the control circuit (8), and the switch circuit portion of the MOS-FET III are a transformer (7) and a pulse transformer (111), respectively.
DC insulation is provided.

Next, the operation of the conventional circuit shown in FIG. 2, which has many similarities with the present invention, will be explained.

When transistor (3) and MO8-FET (13) are off, the output voltage of power supply (1) is almost equal to the load (4
b applied to the signal input terminal (
When entering the control circuit (8) from 9), a gate voltage (sub) with a constant pulse width is applied to the pulse transformer +Ill, which makes MO8-FETQQ conductive. At the same time, the transistor (3) is also connected to the transformer (7) and the rectifier circuit (6).
) and the drive base current (c) flows through it. Then,
The load (4) is first MO5-F with short switching time.
Short-circuited to A6 speed by ETIII. And this M
By the time the O8-FETtlG becomes non-conductive, the transistor (3) is in the conductive state, so the short-circuited state of the load 141 is maintained. Thereafter, in the same manner as the DC/l)C converter, the control circuit (8) activates the transformer (7) so that current alternately flows through it. At this time, transformer (
7), there is a □ voltage (
2) appears. Next, when the input signal 1211 is turned off, the oscillation of the control a circuit (8) is stopped and the transistor (3) is turned off.
The base current no longer flows and the transistor (3) becomes non-conducting again.

Since the conventional single-speed switch circuit is configured as described above, the on-time of the switch can be set at one speed depending on the switching speed of MOIFET Taω, but the off-time is limited by the switching speed of the transistor (3). was there. For example, withstand voltage 8o.

When ■, the general switching speed of the conventional circuit is 1
The limit was μg.

This invention was developed in order to eliminate the above-mentioned drawbacks of the conventional devices, and is designed to maintain the MO5-FET switch circuit in order to increase the switching speed when the load is off, especially when the load is capacitive. - It is an object of the present invention to provide a high-speed switching circuit that can switch not only the on-time but also the off-time at a high speed of 1000 seconds or less by adding a resistor in parallel.

An embodiment of the present invention will be described below with reference to FIG. 1ζ.

Figure 's5 shows a high speed switch circuit according to one embodiment of the present invention. According to the diagram, (1) is the power supply, (2) is the power supply (1)
A protective resistor connected in series with the load (4) across the +
111 is a first MO that short-circuits both ends of the load 14) at high speed.
8-NET, +13 is the second MOIFET connected in parallel to the protection resistor (2) to apply a voltage of 1Ml1Illittl to the load (4), and 181 is the second MOIFET that short-circuits the load to the signal input terminal (9). When the control signal to the effect that it should be input is inputted, it generates the first ON signal to turn on the first MO8-FET, and when the above control signal is not inputted, it turns off the first MO8-FETtll. A control circuit that generates a second on signal to turn on rj13 and a second on signal to turn on MO5-pi: (7) is a control circuit that generates a second on signal to turn on rj13. MO8-FETQ
DC+ as a transformer of 17J1 added to the gate of I
The transformer for DC converter, II is the above control circuit (8
) is a pulse transformer as an off transformer that applies an off signal to the gate of the first MO8-FETJI, and in this embodiment, an off signal is input to the gate of switch element 4 consisting of MO5-FET, (15
1, the off signal is transmitted by short-circuiting the gate and source of the first MO8-FKTIII. Further, (141 is a second ON signal of the control circuit (8)).
This is a pulse transformer serving as a second transformer for inputting Mol to the gate of FET d3. #tel
A rectifier circuit that rectifies the output of the 41 transformer (7),
ul) compensates for the rise time of the signal to increase the switching speed of the first MO8-FETLIOI/4) A pulse transformer that transmits the non-res signal, (2) passes the signal from this pulse transformer +111 to the 1st current circuit ( 6) is a diode to prevent the output voltage from flowing to the /(/resistance (111).

FIG. 6 shows the operating waveforms of each part of this circuit.

The figure (a) shows the human power level H71) as a control signal input to the signal input terminal 191, and the figure (b) shows the gate voltage sent from the pulse transformer tin to the first MU S-FET (11). (Support) waveform, the same figure (C) is the secondary side output voltage (to) of the transformer (7), the same figure (dark is the rectifier circuit +61 to '11! 1 e MOS -1' ET
(ll E sent rectification current ratio ('a), the figure (e) is the gate voltage (to) applied to the switch element t151, the figure (phantom is the gate voltage plane of the second MO8-FETll3,
In the same figure (morning is the gate voltage (to) of the first MU8-FET (11j), (h) is the output voltage (to) output from both ends of the load (4). Note that the waveform ( The time difference '1'1 between (to) and A) is the delay time from the gate off of @l(7) MU8-NET (II until the drain and source are turned off).

Next, the operation will be explained.

In the initial state a+ where there is no input signal 121), the first and is 2 MO8-FE-f [1, 113 and the switch element (151) are all in the off state,
A voltage #tIl+ is applied to the load (4) via the protective resistor (2).

Next, when the input signal 3υ is input to the signal input terminal (9), the gate voltage (2) that compensates for the rise is applied to the first MU8-F via the pulse transformer tLD and the diode (1).
Applied to the gate of ETQl. Almost simultaneously, the rectified voltage (
c) is applied to the gate of the first MU8-FETQI,
The first MU S + FE-r (IG turns on... and short-circuits both ends of the load (4). Then, while the input signal tall is present, the rectified voltage (c) causes the first MU8- FETQI remains on and current from the power supply (1) flows through the first hlOs-FET tlQl and the protection resistor (2).

Then, when the input signal (21) is turned off, the rectified voltage will be
is turned off, but the back emf of the transformer (7) and the first
Due to the valley between the gate and source of the MU8-FET dl, the first MU8-FET (1G gate voltage is difficult to turn off. Therefore, input signal 2!) is turned off at the same time, via the pulse transformer +161. By sending the gate voltage @ that activates the switch element (415) and turning on the switch element (l!
-FET (In) gate voltage is forcibly turned off to accelerate the off operation of the first MU8-NET (11).

In this way, after the first λ40b-FE'r (1α) is sufficiently turned off, the second NI
A gate voltage plane is applied to the US-FET (131).Then, the load (4) has a voltage from #fi+ to the load (4), and the second
Current flows through the MU5-)ET (13) and the load (4
) is quickly switched and returns to the initial voltage state even if there is a floating valley across the voltage.

In this way, the output I @ rise of the juice at both ends of the load (4),
The stand-up time can be reduced to 10gn5ec or less.

In addition, in this embodiment, in order to prevent malfunction due to gate charging of the non-operating side MO8-FET that occurs due to high-speed switching, the second MU8-FET is
-FET113) gate voltage level (Fig. 6(f)
) (see part A) to cancel out the gate charging voltage generated by switching, and during off-operation, the on-time T! of switch element α9 is reduced. the second MU5-
It is made long enough to cover the ON time of FET 13 (this prevents the gate of the first MOIFEitlu from being filled by switching. Also, since this device uses a transformer, the input/output It is possible to provide direct current insulation between the two, so it can be used without interruption even when the output circuit is exposed to high pressure.

FIG. 7 shows another embodiment of the invention. In the figure, (7
a) (7b) are rectifier circuits (6a) (6b) respectively
via the first and second MU8 + F ET tt
(1 (transformer that supplies gate 11fi pressure to 131,
(15λ) (15b) are the first and second M
U8 + FET (10) (This is a switch element that forcibly turns off the gate voltage of 131, and here both MO
8+NET is used. Further, (16 (16b)) is a pulse transformer that applies a gate voltage to the switching elements (15m) (15b), respectively.

This circuit basically operates in the same way as the embodiment shown in FIG.
sO8-FET13 is turned off quickly, and since the protective resistor (2) is omitted, the current from the load (4) or the first MU S -F ETuQI always flows into the second M
This differs from the embodiment shown in FIG. 5 in that the current flows through the US-FET (131) and the pulse transformer (111) is omitted, so that the rise speed of the gate voltage is slightly slower.

Note that in the above embodiment, a pulse transformer uIl and a diode 02) are used for compensation of rising power, but it is necessary for the OI function to obtain sufficient voltage and rise with the transformer (7) and rectifier circuit (6). The pulse transformer 111 and the diode (121) may be omitted.

In addition, in the other embodiments described above, the first klU S -)'
Although switching elements (15a) and (15b) are used to speed up the off operation of the ET (10), a negative voltage may be applied to the gate of the first MOS-FET tl (l) instead. It has the same effect as.

As described above, since the present invention provides MOS-FETs for on and off switching operations, it is possible to perform switching with low impedance when 7<4 is applied to the load, and when the load is high-speed. Even in the case of a capacitive load such as a floating container that interferes with the switching operation, it is possible to sufficiently exhibit its performance.

[Brief explanation of the drawing]

Figure 1 right and Figure 2 are circuit diagrams showing conventional high-speed switch circuits, Figure 3 $ and w14 are operating waveform diagrams of the conventional circuit,
! /65 Diagram A circuit diagram showing a high-speed switch circuit according to an embodiment of this invention, s6 is an operation waveform diagram of the circuit in FIG.
FIG. 9J7 is a circuit diagram showing another embodiment of the present invention. fi+...Power supply, (4)...Load, (2)-...Protection resistor, ilG...1st (7) MOS + NET
, (131,,,jl 2 (7) MOS-FE
T, (81...control circuit, (7)...transformer (
! IFSI transformer), (1!...Pulse transformer (off transformer), I...Hulse transformer (42 transformer). The same reference numerals in the drawings indicate the same or equivalent parts. Agent Shin Kuzuno - Figure 1 Figure 3 (a) 21 ]--1-]-1 = (b) 22 ``1-11'': Figure 4 (c) 23 ''-1-8-11 ] - Figure 5 Figure 6

Claims (1)

[Claims] (1) A power supply, a protection resistor connected in series with the load across the power supply, a first MOS-FET connected in parallel to the load for shorting the load at high speed, and the protection A second MOS-FET connected in parallel with the resistor for applying the power supply voltage to the load at high speed, and the first MO8+FET waiting for input of a control signal indicating that the load should be short-circuited.
an off signal No. 0 for generating a first on signal to turn on the MOS-FET, and turning off the first MOS-FET when the input of the control signal is stopped; and 12 for turning on the second MOS-FET. a control circuit that generates an on signal of the control circuit; and a control circuit that generates an on signal of the control circuit;
a first transformer that applies the off signal of the control circuit to the first MOS-FET; and an off transformer that applies the off signal of the control circuit to the first MOS-FET;
A same-speed switch circuit characterized by comprising a second transformer in addition to an 8+FET.