JPH0678526A - Gate driver circuit - Google Patents

Abstract

PURPOSE:To increase the speed of the switching operation of a switching element further. CONSTITUTION:An ON-OFF signal source 1 outputs an ON-OFF signal V1 driving a power MOSFET 13. A high-frequency signal source 2 outputs a high- frequency signal V2 having frequency sufficiently higher than the ON-OFF signal V1. An exclusive OR gate 3 overlaps the high-frequency signal V2 to the ON-OFF signal V1, and outputs an output signal V3 to the primary side of a pulse transformer 5. A resistor 8 and a capacitor 9 eliminate a high-frequency signal component from output signals Va, Vb on the secondary side of the pulse transformer 5. An inverter 10 outputs the inverting signals of outputs from the resistor 8 and the capacitor 9 to the gate of the power MOSFET 13. An inverter 11 outputs the non-inverting signals of outputs from the resistor 8 and the capacitor 9 to the source of the power MOSFET 13. Diodes 61, 62 and capacitors 71, 72 rectify the output signals Va, Vb of the pulse transformer 5, and supply the inverters 10, 11 with the output signals as power supplies.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power MOSFET or an IGBT (Insulated G) used for an all-digital AC servo drive, a PWM inverter or the like.
The present invention relates to a gate drive circuit that drives a switching element such as an ATE Bipolar Transistor).

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a conventional example of a gate drive circuit. The pulse transformer 43 is a power MOS
The pulse voltage of the on / off signal on the primary side that drives the FET 41 generates a positive pulse voltage and a negative pulse voltage on the secondary side according to the rising and falling of the ON / OFF signal. The diodes 46 and 49 conduct only when a positive pulse voltage is generated on the secondary side of the pulse transformer 43, and the gate of the power MOSFET 41 that is the switching element to be driven is driven.
A positive voltage is applied between the sources to turn it on. The enhancement type MOSFET 42 is a pulse transformer 43.
When a negative voltage is generated on the secondary side of the
The gate of the power MOSFET 41 is connected to the source.
The diode 48 holds the conduction state of the MOSFET 42. The NPN transistor 44, which is a current type switching element, and its base resistance 45 are pulse transformers 43.
When a positive pulse voltage is generated on the secondary side of the MOSFET,
The conducting state of 42 is changed to the non-conducting state.

When a positive pulse voltage is generated on the secondary side of the pulse transformer 43 in response to turning on / off of the on / off signal, the transistor 4 is positively biased through the resistor 45.
4 turns on, the gate of MOSFET 42 is grounded, and MO
The gate charge of the SFET42 is discharged, and the MOSFET42
Turn off. Next, the diode 46 is turned on, and the charging current of the equivalent gate input capacitance of the power MOSFET 41 flows in the order of diode 46 → gate / source of the power MOSFET 41 → diode 49. As the equivalent gate input capacitance is charged, the gate-source voltage of the power MOSFET 41 rises, and when it exceeds the gate-source threshold voltage, the power MOSFET 41 turns on.
Next, when a negative pulse voltage is generated on the secondary side of the pulse transformer 43 in response to turning on / off of the on / off signal, the diodes 47 and 48 become conductive and the equivalent gate input capacitance of the MOSFET 42 is charged. When the gate voltage of the MOSFET 42 exceeds the gate-source threshold voltage, the MOSFET
T42 is turned on, the gate of the power MOSFET 41 is grounded, and the charge of the equivalent gate input capacitance of the power MOSFET 41 is discharged. When the gate voltage of the power MOSFET 41 becomes lower than the threshold voltage, the power MOSFET 41
Turn off. A gate drive circuit using such a pulse transformer has two circuits compared to one using a photo coupler.
Since the power supply circuit on the secondary side is unnecessary, the area occupied by parts is small and the degree of freedom in pattern design is high (Japanese Patent Laid-Open No. 61-242).
416, and JP-A-62-21322).

[0004]

In the conventional gate drive circuit described above, when the power MOSFET is turned off, the gate of the power MOSFET is grounded by another MOSFET so that the gate-source voltage becomes zero. .
However, since the gate of a switching element such as a power MOSFET or IGBT usually has a capacitance of several thousand pF,
If you just ground this gate with a MOSFET,
The source-to-source voltage cannot be made negative (-), and the fall of the switching element cannot be made too fast. That is, it is difficult to speed up the switching operation. An object of the present invention is to provide a gate drive circuit that can speed up the switching operation of a switching element.

[0005]

A gate drive circuit of the present invention has a pulse transformer using an ON / OFF signal as an input signal on the primary side, and outputs an output signal on the secondary side of the pulse transformer to a switching element. A gate drive circuit for driving the switching element by a second SEPP circuit for inputting an output signal on the secondary side of the pulse transformer and outputting it as an inverted signal or a non-inverted signal to the source of the switching element; A second SEPP circuit for inputting the output signal of the secondary side of the transformer and outputting it to the gate of the switching element as a non-inverted signal or an inverted signal. The gate drive circuit of the present invention may include a rectifier circuit connected to the secondary side of the pulse transformer and supplying power to the first and second SEPP circuits. In this gate drive circuit, a signal in which a high frequency signal having a frequency sufficiently higher than the on / off signal is superimposed on the on / off signal is used as an input signal of the pulse transformer, and the high frequency signal component is removed on the secondary side of the pulse transformer. It is preferable that a filter that does this be provided.

[0006]

Operation: Two SEPPs that output signals in opposite phases
In the case where a load is connected between the output terminals of the (Single Ended Push-Pull) circuit, the BTL (Bal
It is called an ancested Transformer Less) circuit and both positive and negative voltages can be applied to this load. The present invention applies positive and negative voltages to the gate and source of the switching element, which is a load, to turn the switching element on and off by the BTL circuit, and particularly when the gate-source voltage falls from positive to negative. The charge stored in the capacitance of the gate of the switching element can be discharged at high speed. With a rectifier circuit that supplies power to the BTL circuit,
It is not necessary to prepare a power source for the BTL circuit. When the high frequency signal is superimposed on the on / off signal, the output signal on the secondary side of the pulse transformer is stably output even if the low level state or the high level state of the on / off signal continues for a long time.

[0007]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 shows a first gate drive circuit of the present invention.
2 (a) to 2 (d) are waveform diagrams in the main part of this embodiment. On-off signal source 1
Is about 20k for driving the power MOSFET 13.
A well-known signal can be used for outputting the on / off signal V _{1 of} Hz. The output terminal of the on / off signal source 1 is connected to one input terminal of the exclusive OR gate 3.
The high frequency signal source 2 outputs a high frequency signal V ₂ having a frequency sufficiently higher than the ON / OFF signal. Here, the “sufficiently high frequency” means a frequency at which a signal component of the frequency is removed by a filter described later to such an extent that a portion after the filter does not malfunction, and is usually 100 to 5
About 00 kHz is preferable, and about 200 kHz in this embodiment.
z. The output terminal of the high frequency signal source 2 is connected to the other input terminal of the exclusive OR gate 3. The exclusive OR gate 3 operates as a superposition circuit that outputs an output signal V ₃ that superimposes two signals. The output terminal of the exclusive OR gate 3 is connected to the input terminal of the line driver 4. The output ends of the inverted and non-inverted signals of the line driver 4 are respectively 1 of the pulse transformer 5.
It is connected to the secondary side. One end of the secondary side of the pulse transformer 5 is an anode of a diode 6 ₁ that half-wave rectifies the output of the pulse transformer 5 and outputs a positive half-wave rectified output,
The output of the pulse transformer 5 by half-wave rectification are connected to the cathode of the diode 6 ₂ which outputs the negative half-wave rectified output. The other end on the secondary side of the pulse transformer is connected to each end of the capacitors 7 ₁ and 7 ₂ and the resistor 8.
The pulse transformer 5 is configured such that when the inverted output of the line driver 4 rises, one output voltage V _a on the secondary side rises and the other output voltage V _b rises. The other end of the capacitor 7 ₁ is connected to the cathode of the diode 6 ₁ and the power supply terminal of a CMOS IC (not shown) incorporating the inverters 10 and 11. The other end of the capacitor 7 ₂ is connected to the anode of the diode 6 ₂ and the inverters 10 and 1
A ground terminal of a CMOS IC (not shown) which incorporates 1;
It is connected to one end of the capacitor 9. The other end of the resistor 8 is connected to the other end of the capacitor 9 and the input end of the inverter 10. The resistor 8 and the capacitor 9 operate as a filter that removes high frequency signal components from the output signal on the secondary side of the pulse transformer 5. The output end of the inverter 10 is connected to the input end of the inverter 11 and the source of the power MOSFET 13 (which may be an IGBT) which is a switching element. The output terminal of the inverter 11 is connected to the gate of the power MOSFET 13 and also connected to the source of the power MOSFET 13 via the resistor 12. The resistor 12 is for preventing the power MOSFET 13 from turning on when the gate drive circuit is not operating at all, that is, when the on / off signal V ₁ is no signal. Inverters 10, 11
Has a Schmitt trigger circuit at the input and SEPP at the output.
Circuit, and these two SEPP circuits make B
A TL (full bridge) circuit is configured. As the inverters 10 and 11, CMOSICs that consume less power are preferable, but any one can be used as long as the output stage is a SEPP circuit, that is, a BTL circuit can be configured.

Next, the operation of this embodiment will be described.
ON / OFF signal V from ON / OFF signal source 1 to 20 kHz₁ But
The high frequency signal output from the high frequency signal source 2 is 200 kHz.
Issue V ₂ Is output, the exclusive OR gate 3
These two signals V₁, V₂ Exclusive
OR is taken and the output signal V shown in FIG.₃ Ex
Output from the Crucial OR gate 3. Here, FIG.
As shown in (b), the on / off signal V₁ Has a high level
When output signal V₃ Has a duty ratio of 90%.
Turn-off signal V₁ Is low level, output signal V₃ De
The duty ratio is 10%. Output signal V₃ Is the line dora
It is input to the pulse transformer 5 via the inverter 4. Palust
Of the output signal of lance 5, capacitor 7₁ , 7₂ Contact
Voltage V on the continuation side_a Is integrated with resistor 8 and capacitor 9
And is input to the input terminal of the inverter 10. Palust
The other output signal of the lance 5 is the diode 6₁ And half
Wave rectified, capacitor 7₁ Charged to the voltage V_P age
Input to the power supply terminals of the inverters 10 and 11
The diode 6₂ Half-wave rectified with capacitor 7 ₂ To
Charged and voltage V_N As inverters 10 and 11
Input to the input terminal. Exclusive OR Gate 3
Output signal V₃ When the duty ratio is 90%, the voltage V
_a Is the voltage V_b Since the higher time is longer, it is shown in Fig. 2 (c).
As you can see, capacitor 7₁ , 7₂ Voltage V_P , V_N Is below
Give up. That is, the voltage V_P Is the voltage V _a Approaching the voltage
V_N Is the voltage V_a Stay away from. At this time, the potential difference V_P −
V_N Is constant (+ 15V in this embodiment). I
High level threshold voltage of inverters 10 and 11 + V_TH
Voltage V_P , V_N Voltage V between_P , V_N Changes like
It Threshold voltage + V_THIs the voltage V_a When it gets lower
Then the output of the inverter 10 becomes low level and the power M
It joins the source of OSFET13 and the output of inverter 11
The power becomes high level and the power MOSFET 13
Join Therefore, as shown in FIG.
Gate-source voltage V of the power MOSFET 13_GSIs +
It becomes 15V, and the power MOSFET 13 is turned on.
Output signal V of exclusive OR gate 3₃ The Dew
When the tee ratio is 10%, the voltage V_a Is the voltage V_b Lower
Since the time is long, as shown in Fig. 2 (c),
7₁ , 7₂ Voltage V_P , V_N Rises. That is,
Pressure V_P Is the voltage V_a Away from the voltage V_N Is the voltage V_a To
Get closer. Potential difference V_P -V_N Is also constant (+ 15V)
Becomes Low-level threshold of inverters 10 and 11
Voltage-V_THVoltage V_P , V_N Voltage V between_P , V_N same as
Changes to. Threshold voltage -V_THIs the voltage V_a Higher
The output of the inverter 10 becomes high level when
Inverter added to the source of power MOSFET 13
The output of 11 becomes low level and power MOSFET 1
Join Gate 3 Therefore, as shown in FIG.
, The gate-source voltage of the power MOSFET 13
V_GSBecomes -15V and the power MOSFET 13 is off
become. Output signal of Exclusive OR Gate 3 again
V₃When the duty ratio of the inverter becomes 90%, the inverter 1
The outputs of 0 and 11 are inverted, and the power MOSFET 13 is turned off.
Become The above operation is repeated. Power MOSFE
The gate of T13 has a capacity of several thousand pF, but ± 15V
Gate-source voltage V_GSApplied between gate and source
Therefore, the gate capacity is charged at both the rising and falling edges.
The generated charge is discharged very quickly. Because of this, power
MOSFET 13 enables high-speed switching operation
It Also, the gate is stopped without servo lock.
In the so-called base block state, the on / off signal V
₁ Keeps low level for a long time. In such a case,
Turn-off signal V₁ From the secondary side of the pulse transformer 5
Not output, but high frequency signal V₂ Is the pulse tran component
Since it is output from the secondary side of the inverter 5,
The power of 1 is supplied stably. This example is
Since the lure or gate 3 is used, the on / off signal
V₁ Supports when the high level (on) state continues for a long time
it can. Inverter for servo drive and motor drive
Is an on-off signal V₁ The high level (on) state of the
Since it does not continue, it is exclusive as a superposition circuit.
An OR gate may be used instead of the OR gate 3.

FIG. 3 shows a second gate drive circuit of the present invention.
4 (a) to 4 (d) are waveform diagrams in the main part of this embodiment. On-off signal source 2
1 is about 20 for driving the power MOSFET 33.
It outputs an on / off signal of kHz. On-off signal source 21
The output terminal of is connected to one input terminal of the OR gate 23. The high frequency signal source 22 outputs a high frequency signal having a frequency sufficiently higher than the on / off signal. The output terminal of the high frequency signal source 22 is connected to the other input terminal of the OR gate 23.
The OR gate 23 operates as a superposition circuit that outputs an output signal V ₂₃ that superimposes two signals. The output end of the OR gate 23 is connected to the input end of the line driver 24.
The output ends of the line driver 24 for inverted and non-inverted signals are connected to the primary side of the pulse transformer 25, respectively. One end on the secondary side of the pulse transformer 25 is a diode bridge 2 including four diodes for full-wave rectifying the output of the pulse transformer 25 and outputting a full-wave rectified output.
6 and also to one end of the resistor 27. Two direct current (pulsating current) output lines 26a and 26b of the diode bridge 26 are provided with a smoothing capacitor 29 between the lines. These output lines 26a, 26
b is a DC output of 15 V,
0 and 31 are respectively connected to a power supply terminal and a ground terminal of a CMOS IC (not shown). Resistance 2
The other end of 7 is connected to one end of a capacitor 28 and the input end of an inverter 30, and the other end of the capacitor 28 is connected to one output line 26 of a diode bridge 26. The resistor 27 and the capacitor 28 operate as a filter that removes a high frequency signal component from the output signal on the secondary side of the pulse transformer 25. The output end of the inverter 30 is connected to the input end of the inverter 31 and the source of the power MOSFET 33 that is a switching element.
The output terminal of the inverter 31 is connected to the gate of the power MOSFET 33 and also connected to the source of the power MOSFET 33 via the resistor 32. The input parts of the inverters 30 and 31 are Schmitt trigger circuits,
The output section is a SEPP circuit, and these two SE
A BTL circuit is configured by the PP circuit.

Next, the operation of this embodiment will be described.
When the on-off signal source 21 outputs an on-off signal and the high-frequency signal source 22 outputs a high-frequency signal, the OR gate 23 takes the OR of these two signals.
The output signal V ₂₃ shown in (a) is output from the OR gate 23. The output signal V ₂₃ is input to the pulse transformer 25 via the line driver 24. The output signals at both ends of the pulse transformer 25 are full-wave rectified by the diode bridge 26, smoothed by the capacitor 29, and supplied to the inverters 30 and 31 as a power source. Further, of the output signals of the pulse transformer 25, the output signal on the side to which the resistor 27 is connected is integrated by a filter including the resistor 27 and the capacitor 28 to remove the high frequency signal component, and the inverter 30 causes the output signal shown in FIG. As shown in b), the waveform-shaped on / off signal V ₃₀ is output. The on / off signal V ₃₀ is input to the source of the power MOSFET 33 and is inverted by the inverter 31, as shown in FIG.
As shown in, is output as the on-off signal V _31. The on / off signal V ₃₁ is input to the gate of the power MOSFET 33. As described above, since signals having phases opposite to each other are always input to the gate and the source of the power MOSFET 33, the gate-source voltage V _GS is the high level of the on / off signal V _{31 as} shown in FIG. 4D. When +15
When the V and the on / off signal V ₃₁ are low level, the voltage is -15V.

[0011]

As explained above, according to the present invention, the gate and source of the switching element are added to the BTL circuit,
By turning on and off the switching element by applying a negative voltage, the rising and falling of the switching element can be made extremely fast, and high-speed switching operation can be performed. Therefore, the operation of the device such as the motor driven by the switching element follows the command of the on / off signal well. Further, by rectifying the output signal on the secondary side of the pulse transformer and supplying it to the BTL circuit as a power source, the power source for the circuit on the secondary side of the pulse transformer becomes unnecessary, so that the number of parts can be reduced. Further, by superimposing a high frequency signal having a frequency sufficiently higher than the on / off signal on the on / off signal, the power supply voltage of the BTL circuit is not affected even if the low level state or the high level state of the on / off signal continues for a long time, and a stable supply is provided. To be done.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a gate drive circuit of the present invention.

2 (a) to (d) are waveform diagrams of main parts of the present embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of the gate drive circuit of the present invention.

4 (a) to (d) are waveform diagrams of main parts of the present embodiment.

FIG. 5 is a circuit diagram showing a conventional example of a gate drive circuit.

[Explanation of symbols]

1, 21 ON / OFF signal source 2, 22 High frequency signal source 3 Exclusive OR gate 4, 24 Line driver 5, 25 Pulse transformer 6 ₁ , 6 ₂ Diode 7 ₁ , 7 ₂ , 9, 28, 29 Capacitor 9, 12, 27, 32 resistance 10, 11, 30, 31 inverter 13, 33 power MOSFET 23 OR gate 26 diode bridge

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location // H02M 7/537 E 9181-5H

Claims (3)

[Claims] 1. A pulse transformer using an on / off signal as an input signal on the primary side, and a pulse transformer
In a gate drive circuit for driving a switching element by outputting an output signal on the secondary side to a switching element, an output signal on the secondary side of the pulse transformer is input to the source of the switching element as an inverted signal or a non-inverted signal. It has a first SEPP circuit for outputting and a second SEPP circuit for inputting an output signal on the secondary side of the pulse transformer and outputting it as a non-inverted signal or an inverted signal to the gate of the switching element. Gate drive circuit to do. 2. The gate drive circuit according to claim 1, further comprising a rectifier circuit connected to the secondary side of the pulse transformer and supplying power to the first and second SEPP circuits. 3. A signal in which a high frequency signal having a frequency sufficiently higher than the on / off signal is superimposed on the on / off signal is used as an input signal of the pulse transformer, and the high frequency signal component is removed on a secondary side of the pulse transformer. The gate drive circuit according to claim 2, further comprising a filter.