JPS58108732A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS58108732A
JPS58108732A JP20856381A JP20856381A JPS58108732A JP S58108732 A JPS58108732 A JP S58108732A JP 20856381 A JP20856381 A JP 20856381A JP 20856381 A JP20856381 A JP 20856381A JP S58108732 A JPS58108732 A JP S58108732A
Authority
JP
Japan
Prior art keywords
polysilicon layer
pattern
annealing
protrusion part
width
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP20856381A
Other languages
Japanese (ja)
Other versions
JPH0237085B2 (en
Inventor
Koichi Kugimiya
釘宮 交公一
Shigenobu Akiyama
秋山 重信
Haruhide Fuse
玄秀 布施
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP20856381A priority Critical patent/JPS58108732A/en
Publication of JPS58108732A publication Critical patent/JPS58108732A/en
Priority to US06/660,255 priority patent/US4563227A/en
Publication of JPH0237085B2 publication Critical patent/JPH0237085B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H01L21/76232Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers

Abstract

PURPOSE:To enable to perform an annealing without having a scattering polysilicon layer by a method wherein, after the pattern width of an overhang protrusion part of the polysilicon layer has been formed on an insulating film in such a manner that said pattern width will be more than one half of the pattern width of the polysilicon layer which constitutes the main body of this device, an annealing is performed using an energy beam. CONSTITUTION:The pattern 20 of the polysilicon layer is formed on the insulating film (not shown in the diagram). On this pattern 20, the polysilicon layer 21, which will constitute the main body of the device, and the overhang protrusion part 22 are formed, and they have pattern widths a and b respectively. Then, an annealing is performed on the polysilicon layer from the direction indicated by the arrow A using a laser beam. An Ar continuous oscillation is used for the laser beam with a scanning speed of 100mm./sec, a crossfeed width of 10mum, a laser spot diameter of 20mum, and a substrate temperature of 350 deg.C. Both the polysilicon layer 21 and the overhang protrusion part 22 are annealed at bTHETA1/ 2a, without generation of scattering on the protrusion part 22.

Description

【発明の詳細な説明】 本発明は、近年急速に発展してきているレーザアニール
やエレクトロンビームアニールナトのエネルギービーム
アニールを用いた半導体装置の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device using energy beam annealing such as laser annealing or electron beam annealing, which has been rapidly developed in recent years.

近年、ポリシリコン層にエネルギービームアニールを施
して簡単な半導体装置を作るといった報告例が散見され
る。これらの例で製造されている半導体装置は全て単純
な矩形や正方形に近いものであり、実際にSO8などで
実用にされている複雑な形状の半導体装置は報告されて
いない0本発明者らは、実際用いられている様な複雑な
形状を有した島状のポリシリコン層に対するエネルギー
ビームアニール実験を各種のポリシリコンパターン、種
々のアニール条件(ビーム出力、走査速度、温度など)
で行なった結果、次のような結論を得た。即ち、エネル
ギービームアニール法特ニ島状ポリシリコン層のアニー
ルにおいては、ポリシリコン層を溶融させる最適条件が
あり、との条件を越えると、ポリシリコン層の一部が飛
散してしまう。
In recent years, there have been several reports on the fabrication of simple semiconductor devices by applying energy beam annealing to polysilicon layers. The semiconductor devices manufactured in these examples are all close to simple rectangles or squares, and there have been no reports of semiconductor devices with complex shapes that are actually used in SO8 etc.0The present inventors We performed energy beam annealing experiments on island-shaped polysilicon layers with complex shapes, such as those used in practice, using various polysilicon patterns and various annealing conditions (beam output, scanning speed, temperature, etc.)
As a result, the following conclusions were obtained. That is, in the energy beam annealing method, particularly in annealing an island-like polysilicon layer, there are optimum conditions for melting the polysilicon layer, and if these conditions are exceeded, part of the polysilicon layer will scatter.

第1図はポリシリコン層に対するレーザアニールの前後
の状態を示すものである。まず、同図(&)に示す様に
、Si02等の絶縁膜(図示せず)上にポリシリコン層
11を形成する。このポリシリコン層11は片持ち突起
部12、両持ち突起部13及び本体部とガる直長部14
が形成されている。次にレーザ光を方向15の様にポリ
シリコン層士上を順次走査させる。レーザ走査後のポリ
シリコン層11の形状を第1図(b)に示す。同(b)
図より明らかな様に、片持ち突起部12は飛散して原形
がはとんとなくなっているが、両持ち突起部13はほと
んどそのまま残っている。これはポリシリコン層11を
溶融するレーザ光をこのような微小々突起12にあてる
と、その部分で入力過剰となり飛散してしまうためと考
えられる。
FIG. 1 shows the state before and after laser annealing the polysilicon layer. First, as shown in the figure (&), a polysilicon layer 11 is formed on an insulating film (not shown) such as Si02. This polysilicon layer 11 has a cantilever protrusion 12, a double-end protrusion 13, and a straight part 14 that connects with the main body.
is formed. Next, the laser beam is sequentially scanned over the polysilicon layer in a direction 15. The shape of the polysilicon layer 11 after laser scanning is shown in FIG. 1(b). Same (b)
As is clear from the figure, the cantilever protrusion 12 is scattered and loses its original shape, but the double-end protrusion 13 remains almost intact. This is thought to be because when the laser beam that melts the polysilicon layer 11 is applied to such minute protrusions 12, the input becomes excessive at that portion and the laser beam scatters.

以下、本発明に係る詳細な実施例を述べる。Detailed embodiments of the present invention will be described below.

(実施例1) 第2図(2L)に示す様に、絶縁膜(図示せず)上にポ
リシリコン層のパターン20を形成する。このパターン
20には主体となるポリシリコン層21及び片持ち突起
部22が形成されており、それぞれのパターン巾は12
 a、bとなっている。次に、レーザ光によりポリシリ
コン層をアニールした。レーザにはAr連続発振を用い
、走査速度10 o−1横送りIll 10 pm 、
レーザスポット径206m、基板温度360℃とした。
(Example 1) As shown in FIG. 2 (2L), a pattern 20 of a polysilicon layer is formed on an insulating film (not shown). This pattern 20 is formed with a main polysilicon layer 21 and a cantilever protrusion 22, each of which has a pattern width of 12
They are a and b. Next, the polysilicon layer was annealed using laser light. Ar continuous oscillation was used for the laser, and the scanning speed was 10 o-1, the horizontal feed was 10 pm,
The laser spot diameter was 206 m, and the substrate temperature was 360°C.

尚、ポリシリコン層2゜はhpcvn法により厚さ50
00人の酸化膜上に厚さ460o入に形成されている。
Note that the polysilicon layer 2° was made to a thickness of 50° by the HPCVN method.
It is formed to a thickness of 460° on a 0.0000000000000000000 oxide film.

この結果を表1に示した。同表中で○印は主体となるポ
リシリコン層21と片持ち突起部22共にアニールされ
ていることを示し、X印は突起部22が飛散しているこ
とを、△印は主体となるポリシリコン層21のアニール
が不十分であることを示している。
The results are shown in Table 1. In the same table, the ○ mark indicates that both the main polysilicon layer 21 and the cantilever protrusion 22 have been annealed, the This indicates that the annealing of the silicon layer 21 is insufficient.

同表から、a = 2 bを境界にして飛散状態が変化
することが分る。ここで、本実施例ではレーザアニール
を用いた例を示したが、エレクトロンビームを用いても
同様のことが云える。
From the same table, it can be seen that the scattering state changes with a = 2 b as the boundary. Here, although an example using laser annealing is shown in this embodiment, the same can be said even if an electron beam is used.

(実施例2) 実施例1における島状に残したポリシリコン層に81イ
オンを1o16/2注入し、アモルファス化m し、同様の実験を行ったが、全く同じ結果が得られた。
(Example 2) 81 ions were implanted into the polysilicon layer left in the island shape in Example 1 at a rate of 1016/2 to make it amorphous, and a similar experiment was conducted, but exactly the same results were obtained.

(実施例3) 第2図(b)に示す様に、パターン巾亀のポリシリコン
層23とパターン巾b+、b2を有する片持ち突起部2
4,2δを有するポリシリコン層20Iを形成し、実施
例1と同様の実験を行った。この結果を表2に示す。同
表から明らか々様に、b、ffaの時、C\シ、の時に
都合よくアニールされている。
(Example 3) As shown in FIG. 2(b), a polysilicon layer 23 with a pattern width and a cantilever protrusion 2 having pattern widths b+ and b2
A polysilicon layer 20I having a diameter of 4.2δ was formed, and an experiment similar to that in Example 1 was conducted. The results are shown in Table 2. It is clear from the same table that annealing is conveniently performed when b, ffa, and C\shi.

尚、○△×の意味については表1と同じである。Note that the meanings of ○△× are the same as in Table 1.

表2 (実施例4) 第2図(0)に示すような梯子状のポリシリコン層2o
”パターンを形成して実施例1と同様の実験を行なった
。ここで、ポリシリコン層2σの主たるポリシリコン層
26の巾はaであり、それに橋渡:たすように形成され
た両持ち突起部26の上側がiJaで長さ21L−(i
、下側が巾lで長さdである。この結果を表3に示す。
Table 2 (Example 4) Ladder-shaped polysilicon layer 2o as shown in FIG. 2 (0)
``A pattern was formed and an experiment similar to that in Example 1 was conducted.Here, the width of the main polysilicon layer 26 of the polysilicon layer 2σ is a, and a double-sided protrusion formed to bridge it. The upper side of the portion 26 is iJa and has a length of 21L-(i
, the lower side has a width l and a length d. The results are shown in Table 3.

同表から明らかな様にd4aでう捷〈アニールされた。As is clear from the same table, it was deformed and annealed in d4a.

尚、○×の意味についCは表1と同じである。Note that the meaning of ○× is the same as in Table 1 for C.

表3 以上説明した様に、本発明に係る半導体装置の製造方法
ではポリシリコン層の片持ち突起部のパターン巾を主体
となるポリシリコン層パターン巾の種以上になる様に絶
縁膜上に形成した後、エネルギービームによりアニール
するので、ポリシリコン層の飛散とほとんどなくすこと
が可能となり、製造歩留上極めて有用なものである。
Table 3 As explained above, in the method for manufacturing a semiconductor device according to the present invention, the pattern width of the cantilever protrusion of the polysilicon layer is formed on the insulating film so that it is larger than the pattern width of the main polysilicon layer. After that, annealing is performed using an energy beam, which makes it possible to almost eliminate scattering of the polysilicon layer, which is extremely useful in terms of manufacturing yield.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)、 (b)はポリシリコン層をレーザ7=
−ルする工程を示した上面図、第2図(a)〜(C)は
本発明に係る実施例を説明する為に用いたポリンリコン
のパターン図を示すものである。 2o、2σ、2σ・・・・ポリシリコン層、22゜24
.25・・・・・・片持ち突起部、21.23,25・
・・・・主体となるポリシリコン層、26・・・・・・
両持ち突起部。 代理人の氏名 弁理士 中 尾 敏 男 ほか1名城 11 わ□□っと一□、
Figures 1 (a) and (b) show the polysilicon layer 7=
2(a) to 2(C) are top views showing the process of rolling, and FIGS. 2(a) to 2(C) show pattern diagrams of polyconductors used to explain the embodiments of the present invention. 2o, 2σ, 2σ...polysilicon layer, 22°24
.. 25...Cantilever protrusion, 21.23,25.
...Main polysilicon layer, 26...
Double-sided protrusion. Name of agent: Patent attorney Toshio Nakao and 1 other person 11 Wa□□ttoichi□,

Claims (1)

【特許請求の範囲】[Claims] 絶縁膜上に本体部のパターン巾より約彊以上のパターン
巾を持つ突起部を有するポリシリコン層を形成する工程
と、前記ポリシリコン層をエネルギービームによりアニ
ールする工程とを備えたことを特徴とする半導体装置の
製造方法。
The present invention is characterized by comprising the steps of: forming a polysilicon layer having a protrusion having a pattern width of about an inch or more than the pattern width of the main body portion on the insulating film; and annealing the polysilicon layer with an energy beam. A method for manufacturing a semiconductor device.
JP20856381A 1981-12-08 1981-12-22 Manufacture of semiconductor device Granted JPS58108732A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP20856381A JPS58108732A (en) 1981-12-22 1981-12-22 Manufacture of semiconductor device
US06/660,255 US4563227A (en) 1981-12-08 1984-10-12 Method for manufacturing a semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20856381A JPS58108732A (en) 1981-12-22 1981-12-22 Manufacture of semiconductor device

Publications (2)

Publication Number Publication Date
JPS58108732A true JPS58108732A (en) 1983-06-28
JPH0237085B2 JPH0237085B2 (en) 1990-08-22

Family

ID=16558251

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20856381A Granted JPS58108732A (en) 1981-12-08 1981-12-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS58108732A (en)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
J.APPL PHYS *

Also Published As

Publication number Publication date
JPH0237085B2 (en) 1990-08-22

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