JPS58107967A - Test system - Google Patents

Test system

Info

Publication number
JPS58107967A
JPS58107967A JP56206615A JP20661581A JPS58107967A JP S58107967 A JPS58107967 A JP S58107967A JP 56206615 A JP56206615 A JP 56206615A JP 20661581 A JP20661581 A JP 20661581A JP S58107967 A JPS58107967 A JP S58107967A
Authority
JP
Japan
Prior art keywords
time
memories
converter
test
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56206615A
Other languages
Japanese (ja)
Inventor
Masao Yamamoto
山本　雅男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ando Electric Co Ltd
Original Assignee
Ando Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ando Electric Co Ltd filed Critical Ando Electric Co Ltd
Priority to JP56206615A priority Critical patent/JPS58107967A/en
Publication of JPS58107967A publication Critical patent/JPS58107967A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To eliminate data transfer executed each time and to reduce the test time, by transferring a measuring data in advance to plural memories provided between a sequence processor and a DA converter, and controlling the address of a memory. CONSTITUTION:A measuring data from a sequence processor 1 is converted into a measuring signal at a DA converter 3 and this measuring signal is applied to an object to be measured 4. In such a test system, a plurality of memories 5A-5C are provided between the processor 1 and the converter 3. The measuring data of the processor 1 is transferred to the memories 5A-5C in advance via an interface 6. Thus, only the address of the memories 5A-5C is controlled from an address control circuit 7 in the execution and the time for data transfer done each time in conventional systems is eliminated, allowing to reduce the test time.

Description

【発明の詳細な説明】 この発明は、シーケンスプロセッサからの測定用データ
をメモリを介して被測定物に供給するテストシステムに
ついてのものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a test system that supplies measurement data from a sequence processor to a device under test via a memory.

従来システムの一例を第１図に示す。図で、１はシーケ
ンスプロセッサ、２はレジスタ、３ハｌ）Ａ変換器、４
は被測定物である。シーケンスプロセッサ１には、プロ
グラムメモリ、コンピュータ。An example of a conventional system is shown in FIG. In the figure, 1 is a sequence processor, 2 is a register, 3 is a converter, and 4 is a converter.
is the object to be measured. The sequence processor 1 includes a program memory and a computer.

ディジタル回路などを使用することができる。そして、
レジスタ２にはシーケンスプロセッサ１から測定用デー
タが転送さ扛る。ＤＡ変換器６はレジスタ２の測定用デ
ータを測定信号に変換し、その測定信号を被測定物４に
供給する。Digital circuits etc. can be used. and,
Measurement data is transferred to the register 2 from the sequence processor 1. The DA converter 6 converts the measurement data in the register 2 into a measurement signal, and supplies the measurement signal to the object to be measured 4.

次に、第１図によるフローチャートの一例を第２図に示
す。図で、１１はシーケンスプロセッサ１からレジスタ
２へのデータ転送時間、１２はレジスタ２の出力による
回路切換え時間、１６はリレーなどの動作による待ち時
間、１４は被測定物４の測定時間である。Next, an example of the flowchart shown in FIG. 1 is shown in FIG. In the figure, 11 is the data transfer time from the sequence processor 1 to the register 2, 12 is the circuit switching time due to the output of the register 2, 16 is the waiting time due to the operation of a relay, etc., and 14 is the measurement time of the object to be measured 4.

１１〜１４で構成さ扛るステップ１０で１つの測定が行
われ、２１〜２４で構成さ扛るステップ２０で次の測定
が行わｎ、る。ステップ２０はステップ１０の繰シ返し
であり、以下同じようにして但（ｌ定が進行する。One measurement is performed in step 10 consisting of steps 11 to 14, and the next measurement is performed in step 20 consisting of steps 21 to 24. Step 20 is a repetition of step 10, and the determination proceeds in the same manner.

このように従来システムでは、測定のたびにデータをシ
リアル転送していくので、時間的なロスが大きいという
問題がある。In this way, in the conventional system, data is serially transferred every time a measurement is performed, which causes a problem of large time loss.

この発明は、シーケンスプロセッサ１．．！：ＤＡ変換
器６の間に複数のメモリを設け、この複数のメモリに測
定用データをあらかじめ転送しておき、テストの実行に
際してはこれらのメモリのアドレスを制御することによ
り、毎回行わ扛ていたデータ転送をなくし、テスト時間
を短くすることを目的とする。以下、図面によシこの発
明の詳細な説明する。This invention provides a sequence processor 1. ．． ! : Multiple memories were provided between the DA converters 6, measurement data was transferred to these multiple memories in advance, and each test was performed by controlling the addresses of these memories when executing the test. The purpose is to eliminate data transfer and shorten test time. The present invention will be described in detail below with reference to the drawings.

この発明による実施例の構成図を第６図に示す。A block diagram of an embodiment according to the present invention is shown in FIG.

図で、５Ａ〜５Ｃはメモリ、６はインターフェ−ス、７
はアドレスコントロール回路である。In the figure, 5A to 5C are memories, 6 is an interface, and 7
is an address control circuit.

第６図では３つのメモリ５Ａ〜５Ｃを例示しているが、
メモリ５の数は必要に応じて増減する。Although FIG. 6 illustrates three memories 5A to 5C,
The number of memories 5 can be increased or decreased as necessary.

そして、シーケンスプロセッサ１の測定用データをイン
ターフェース６を介してメモリ５Ａ〜５Ｃにあらかじめ
転送しておく。The measurement data of the sequence processor 1 is transferred in advance to the memories 5A to 5C via the interface 6.

こうしておけば、テストの実行にはアドレスコントロー
ル回路７からメモリ５Ａ〜５Ｃのアドレスだけを制御す
ｎば工く、第２図に示したステップ１０のデータ転送時
間１１とステップ２０のデータ転送時間２１をなくすこ
とができる。すなわち、第２図のような従来システムで
毎回行わｌｊしていたデータ転送のための時間をなくし
、テスト時間を短くすることができる。In this way, in order to execute the test, only the addresses of the memories 5A to 5C need to be controlled from the address control circuit 7. can be eliminated. That is, it is possible to eliminate the time required for data transfer, which is performed every time in the conventional system as shown in FIG. 2, and to shorten the test time.

以上のように、この発明によｎば測定データを各メモリ
にあらかじめ転送しておくので、データ転送時間だけ実
行時間を短くすることができ、テストを高速化すること
ができる。As described above, according to the present invention, since measurement data is transferred to each memory in advance, the execution time can be shortened by the data transfer time, and the test can be performed at high speed.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来システムの一例、 第２図は第１図によるフローチャートの一例、第６図は
この発明による実施例の構成図。 １・・・・・シーケンスプロセッサ、２・・・・レジス
タ、６　・・・ＤＡ変換器、４・・・・・被測定物、５
Ａ〜５Ｃ・・・・・・メモリ、６・・・・・インターフ
ェース、７・・・・・アドレスコントロール回Ｍ、１０
・・・・ステップ、１１・・・・・データ転送時間、１
２・・・回路切換え時間、１６・・・・・待ち時間、１
４・・・・・測定時間、２０・・ステップ、２１・・・
・・データ転送時間、２２・・・・・・回路切換え時間
、２３・・・・待ち時間、２４・・・・・・測定時間。 　５− 第１図 第２図 テ′°−タ奄６更　　１１ 回路Ｍ撥太　１２ ０ ４舟　　ち　　　　１３ シ則大　　　１４ デ°−タ車云蓬　　２１ 回路坊換え　２２ ０ 余午　　ち　　　　２３ ミ則−ｉ　　　２４FIG. 1 is an example of a conventional system, FIG. 2 is an example of a flowchart according to FIG. 1, and FIG. 6 is a configuration diagram of an embodiment according to the present invention. 1...Sequence processor, 2...Register, 6...DA converter, 4...Device under test, 5
A~5C...Memory, 6...Interface, 7...Address control times M, 10
...Step, 11 ...Data transfer time, 1
2...Circuit switching time, 16...Waiting time, 1
4...Measurement time, 20...Step, 21...
...Data transfer time, 22...Circuit switching time, 23...Waiting time, 24...Measurement time. 5- Figure 1 Figure 2 Data 6 change 11 Circuit M plug 12 0 4 boats 13 Shi rule 14 Data wheel 21 Circuit replacement 22 0 Yogo 23 Mi rule -i 24

Claims (1)

【特許請求の範囲】 １、　シーケンスプロセッサ（１）からの測定用データ
をＤＡ変換器（６）で測定信号に変換し、この測定信号
を被測定物＋４１に供給するテストシステムにおいて、 シーケンスプロセッサｌｊＩとＤＡ変換器（６１の間に
複数のメモ１月５）を設け、 シーケンスプロセッサ由から各メモリ６１に測定用デー
タをあらかじめ転送しておき、 テストの実行に際しては各メモ１月５１のアドレスを制
御することを特徴とするテストシステム。[Claims] 1. In a test system in which measurement data from a sequence processor (1) is converted into a measurement signal by a DA converter (6) and this measurement signal is supplied to an object under test +41, a sequence processor ljI and a DA converter (multiple memos 61 between them), transfer the measurement data from the sequence processor to each memory 61 in advance, and when executing the test, use the address of each memo 51. A test system characterized by controlling.
JP56206615A 1981-12-21 1981-12-21 Test system Pending JPS58107967A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56206615A JPS58107967A (en) 1981-12-21 1981-12-21 Test system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56206615A JPS58107967A (en) 1981-12-21 1981-12-21 Test system

Publications (1)

Publication Number Publication Date
JPS58107967A true JPS58107967A (en) 1983-06-27

Family

ID=16526302

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56206615A Pending JPS58107967A (en) 1981-12-21 1981-12-21 Test system

Country Status (1)

Country Link
JP (1) JPS58107967A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4947573A (en) * 1972-05-24 1974-05-08
JPS5058988A (en) * 1973-09-25 1975-05-22
JPS5384437A (en) * 1976-12-29 1978-07-25 Fujitsu Ltd Control system for test pattern generation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4947573A (en) * 1972-05-24 1974-05-08
JPS5058988A (en) * 1973-09-25 1975-05-22
JPS5384437A (en) * 1976-12-29 1978-07-25 Fujitsu Ltd Control system for test pattern generation

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