JPS58101575U - Video signal processing circuit - Google Patents
Video signal processing circuitInfo
- Publication number
- JPS58101575U JPS58101575U JP19340181U JP19340181U JPS58101575U JP S58101575 U JPS58101575 U JP S58101575U JP 19340181 U JP19340181 U JP 19340181U JP 19340181 U JP19340181 U JP 19340181U JP S58101575 U JPS58101575 U JP S58101575U
- Authority
- JP
- Japan
- Prior art keywords
- video signal
- circuit
- switch circuit
- signal processing
- input video
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Television Signal Processing For Recording (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来回路の一例を示す系統図、第２図はこの考
案の一実施例を示す系統図である。
１は逓倍器、３は振幅変調器、５． １７． ２０゜２
１はスイッチ回路、６は遅延回路、８．２２は復調器、
１０は検出回路、１６は比較器、−２３は □分周器
である。FIG. 1 is a system diagram showing an example of a conventional circuit, and FIG. 2 is a system diagram showing an embodiment of this invention. 1 is a multiplier, 3 is an amplitude modulator, 5. 17. 20°2
1 is a switch circuit, 6 is a delay circuit, 8.22 is a demodulator,
10 is a detection circuit, 16 is a comparator, and -23 is a □ frequency divider.
Claims (1)
回路の出力と上記入力映像信号とを選択する第１のスイ
ッチ回路とを設け、上記第１のスイッチ回路を選択信号
に応じて切換えるようにらすと共に、上記遅延回路の出
力と上記入力映像信号とを選択する第２のスイッチ回路
と、この第２のスイッチ回路からの出力に応じて上記入
力映像信号の利得を制御する利得制御回路とを設け、上
記第２のスイッチ回路を上記選択信号より充分周波数が
高い周期的信号により切換えるようにしたことを特徴と
する映像信号の処理回路。 ゛A delay circuit that delays an input video signal by a predetermined amount, and a first switch circuit that selects between the output of the delay circuit and the input video signal are provided, and the first switch circuit is switched in accordance with the selection signal. a second switch circuit that selects the output of the delay circuit and the input video signal, and a gain control circuit that controls the gain of the input video signal according to the output from the second switch circuit. A video signal processing circuit characterized in that the second switch circuit is switched by a periodic signal having a sufficiently higher frequency than the selection signal.゛
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19340181U JPS58101575U (en) | 1981-12-28 | 1981-12-28 | Video signal processing circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19340181U JPS58101575U (en) | 1981-12-28 | 1981-12-28 | Video signal processing circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58101575U true JPS58101575U (en) | 1983-07-11 |
Family
ID=30106756
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19340181U Pending JPS58101575U (en) | 1981-12-28 | 1981-12-28 | Video signal processing circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58101575U (en) |
-
1981
- 1981-12-28 JP JP19340181U patent/JPS58101575U/en active Pending
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