JPS58101516A - Comparator - Google Patents

Abstract

PURPOSE:To attain a remarkable mitigation of conditions reading an input signal stably, by controlling a threshold level in response to the level of the input signal. CONSTITUTION:When an input signal I is inputted and a positive level exceeds a threshold level TH, an output O becomes a low level, a positive peak hold circuit section 6 starts the peak hold and an analog switch 10 is conductive. When the signal I is lower than a threshold level TL, the output O goes to a high level, an analog switch 9 is conductive and the switch 10 is interrupted. As a result the positive peak value is added to TH in a constant rate and TH is shifted to a high level. When the input signal I is increased negative, the correction is done to decrease TL through the similar operation, allowing to widen noise margin 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the transmission of signals from peripheral devices to a computer;
This invention relates to a comparator that Δ-shapes an input signal and is used as an interface when transmitting signals between computers or from analog equipment to digital equipment.

Many comparators have two threshold levels.

In a comparator that shapes an analog signal into a digital signal, as shown in FIG. The average m of is set as a fixed bias signal Io and is passed through the resistor R1 to adder circuit section 2.
At the same time, the output signal 0 of the differential amplifier circuit section l (that is, the output of this comparator) is looped back and added to the adder circuit section 2 through the resistor R2't-, and the output signal of the adder circuit section 2 is A configuration is known in which the output is input to the non-inverting input terminal of the differential amplifier circuit section l.

In the comparator shown in FIG.
When first reaches the high-level side threshold level THtM, the output 0 of the comparator becomes a low level, and this low-level output 0 is fed back to lower the threshold level and push it down to the bell side threshold level TL. Next, in order for the output 0 of the comparator to become a high level, the input signal must fall below the low level side threshold level TL. -to result, threshold level fiTH-T
L becomes a noise margin of 8, and noise within this range, for example the noise indicated by symbol 4, is removed and the analog input signal signal is encoded into a digital output signal of 0.

However, in the comparator shown in Figure 1, the threshold level is set by the fixed resistor R2 and is always constant, so there is a problem that it can only be correctly encoded when the noise level of the input signal ■ is within a limited range. There is. That is, as shown in FIG. 2, if noise 5 exceeding the fixed noise margin 8 is included, this comparator will malfunction. For example, signals input from a tape recorder or the like to a personal computer, etc. have different amplitudes and S/N ratios depending on the volume, tone, or model of the tape recorder, as shown in Figure 1. Even if such a comparator with two threshold levels is used, it is difficult to stably read all tape recorders.

In view of the above problems, the present invention greatly eases the conditions for stably reading input signals by controlling the threshold level according to the level of the input signal. The purpose of this invention is to obtain similar effects in shaping input signals from , photocouplers, and other transmission systems.

Hereinafter, the present invention will be explained in detail using one example.

FIG. 8 is a circuit diagram showing one embodiment of the present invention.

1 is the same differential amplifier circuit as shown in FIG. 1, and its inverting input amplifier HK is connected to the input coupling capacitor C1.
The input signal I is input through -. 6 is Puwo7111+
(+ side) Peak hold circuit section, 7 is Minanu 111 (
− side) The peak hold circuit section is connected to the input signal path, and the + side and − side of the input signal The peak value of is maintained. Reference numeral 8 denotes a four-man power adder circuit section, which is connected to the non-inverting input terminal of the differential amplifier circuit section l, and this four-man power adder circuit section 8 receives a fixed bias signal ■. is input through the entire resistor R1, and the output signal 0 of the differential amplifier circuit section 1 is input at an appropriate ratio through the resistor R2f, and the + side peak value held in the + side peak hold circuit section 6 is input. is connected to the resistor R2 through the analog switch 9 when the high-level side threshold level becomes effective.
A3. When the one side peak value inputted at an appropriate rate through the peak hold circuit section 7 and held in the peak hold circuit section 7 becomes effective, the low level side threshold is activated. It is input at an appropriate rate through a resistor R4 via a dilog switch IO. This four-man power addition circuit section 8 adds these four man-power forces and outputs it as the threshold level of the input signal I to the non-inverting input terminal of the differential amplifier circuit section l.

The + side peak hold circuit section 6 refreshes the + side beat value at the timing when the output 0 of the differential amplifier circuit section l switches from high level to low level, and the - side peak hold circuit section 7 One side peak tit occurs at the timing when the output 0 of circuit section l switches from low level to high level.
Refresh.

The analog switch 9 is in a conductive state when the output 0 of the differential amplifier circuit section l is at a high level, and is in a cutoff state when the output O is at a low level. Conversely, the analog switch 10 assists conduction when the output 0 of the differential amplifier circuit section l is at a low level, and enters a cutoff state when the output 0 is high and at a pel level.

The operation of this embodiment will be explained with reference to FIGS. 8 and 4.

When the input signal ■ is not applied, the output values of both the + side peak hold circuit section 6 and the - side peak hold circuit section 7 are zero, so the threshold level TH9
TL is the same as the comparator in FIG. The input signal I is now input, and the + side level is the threshold level TH.
(at the time of symbol 11), the output 0 becomes a low level, and at this timing the + side peak hold circuit section 6 becomes +
The side peak value is started to be held, and the analog switch IO becomes conductive. Next, when the input signal I falls to the threshold level TLxv (at the time of symbol 12), the output 0 becomes high level, and at this timing, the one-side peak hold circuit section 7 starts holding the one-side peak value, and the analog switch 9 becomes conductive, and analog switch IO becomes cut off.

Sono result, high level side threshold level TH is +
The side peak values are added at a rate of one foot and shifted to a high level (All).Next, when the input signal (■) is shifted to this high level side and reaches the threshold level TH11 (at the time of symbol 18), the output 0 becomes low. level, and at this timing +
The side peak hold circuit section 6 refreshes the holding of the + side peak value, and the analog switch 10 becomes conductive.
Analog switch 9 is turned off. As a result, the one-side peak value is added to the low-level threshold level TL at a constant rate and shifted to the low-level side.

Similarly, when the input signal ■ increases to the + side, this comparator changes to the high level side threshold level THt-.
If the input signal I increases to one side, it is corrected to push it down to the low level side 7 threshold level TL1, thereby widening the noise margin 8.

Here, the threshold level TH1TL once returns to its initial value at the time of refreshing to maintain the peak operation, but since this timing is not the timing at which the threshold level is effectively operated, there is no opening at all in terms of operation.

Further, in the above embodiment, the threshold level is not corrected when the input signal I is not input.
A dummy bit may be provided before inputting the input signal I to initialize the threshold level to an appropriate level.

As described above, the comparator of the present invention has an input m number t-
Since the threshold level for distinguishing from noise is corrected according to the amplitude of the input signal, it is possible to remove even noise 5 that would cause a malfunction in a conventional comparator, as shown in FIG. in this way,
According to the present invention, it is possible to obtain a computer with increased resistance to noise, reduced error rate when encoding an analog signal, and improved transmission reliability.

Furthermore, for example, if the comparator of the present invention is used for data transfer between a personal computer and a tape recorder,
The reliability of data transfer is improved, the selection range of tape recorder models is expanded, and the volume setting range of each tape recorder is also expanded.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a conventional comparator, FIG. 2 is an input/output signal waveform diagram explaining the operation of the comparator shown in FIG. 1, and FIG. 8 is a circuit diagram showing a ninth embodiment of the present invention. FIG. 4 is an input/output signal waveform diagram illustrating the operation of the same embodiment. ■...Input signal, 0...Fixed signal, T
H...High level side threshold level, TL...
Low level side threshold level, 0...Output signal, 1...Differential amplifier circuit section, 6...+ side peak hold circuit section, 7...-side peak hold circuit section, 8...4 Manual addition circuit section, 9.10...Analog switch. Patent applicant: Sharp Co., Ltd. Representative: Patent attorney: 8 people from Aohaku, 2nd figure, 3rd figure, 4th figure

Claims (1)

[Claims] (11) In a comparator having two threshold levels, a high level and a low level, and shaping an input signal according to these two threshold levels, the threshold levels are set independently of each other in immediate response to the amplitude of the input signal. (2) When the input signal exceeds the high-level side threshold level, the output signal becomes low level, and when the input signal falls below the low-level side threshold level, the output signal changes. The comparator includes a positive peak hold circuit section that holds a positive peak value of the input signal when the output signal switches from a high level to a low level; a negative side peak hold circuit section that holds the negative side peak value of the input signal when the output signal is switched to the high level side, and a value corresponding to the held value of the positive side peak hold circuit section when the output signal is high level. Claim 1, further comprising: means for adding to a threshold level; and means for adding a value corresponding to a value held by the negative peak hold circuit section to the low-level threshold level when the output signal is at a low level. The comparator described in section.