JPS63194441A - Clock reproduction circuit - Google Patents

Abstract

PURPOSE:To remove the unstable factors of a tank circuit completely and to make a circuit into an integrated circuit, by generating a waveform equivalent to noise generated at the tank circuit, and removing the noise by using a differential amplifier, in the circuit where a timing component is extracted from an equalization signal with a digital transmission system and a clock signal is generated. CONSTITUTION:The equalization signal inputted to an input terminal A is binary- encoded at a binary encoding circuit 1, and after a sine wave being obtained by extracting a timing wave at the tank circuit 3, is inputted to the first input terminal of the differential amplifier 5. Also, the binary encoded signal, after the same waveform as the noise generated at the output of the tank circuit 3 via a capacitor 15 and a resistor 13 being obtained, is inputted to the second input terminal of the differential amplifier 5. In such a way, a noise component that is a problem in a conventional circuit is removed the in-phase noise eliminating function of the differential amplifier 5, and it is possible to obtain a pulse clock waveform without turbulence stably. As a result, it is possible to design the tank circuit with an arbitrary delay quantity since a delay phase is operated stably in any phase state, and to make a clock reproduction circuit including the tank circuit into an LSI.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention extracts a timing component from an equalized signal to identify an equalized signal obtained by equalizing and amplifying a transmission line signal using a digital transmission method. This invention relates to a clock regeneration circuit that generates a clock.

(Prior Art) In general, in digital transmission systems, a self-timing system is widely used in which a timing component is extracted from a transmission line equalized signal to generate a clock signal for identifying and reproducing an equalized waveform. As shown in FIG. 2, the timing extraction circuit in the conventional self-timing method is composed of a binary encoding circuit 1, an integrator 2, a tank circuit 3, and a pulse shaping circuit 4. and 12
are the matching resistances at the input and output of the tank circuit, respectively. An equalized signal is input to the input terminal A, is binary encoded by the binary encoding circuit 1, and after the timing component is extracted by the tank circuit 3 to obtain a sine wave output, it is sent to the pulse shaping circuit 4. A pulse clock signal is obtained by applying amplitude limitation and waveform shaping.

(Problems to be Solved by the Invention) The input and output waveforms of the tank circuit when the integrator is removed from the clock recovery circuit of FIG. 2 will be described.

In an ideal tank circuit, the sine wave shown in Figure 3 (B) is output in response to the input signal in Figure 3 (A), and the waveform of the pulse shaping circuit is a pulse as shown in Figure 3 (C). Can be used as a clock signal.

However, in the tank circuit commonly used in the past, as shown in Figure 3 (d), the rise of the input pulse of the tank circuit,
The high frequency component of the falling portion is superimposed on the output as noise by a certain amount proportional to the input pulse amplitude. Since this noise exceeds the threshold level, the pulse clock signal becomes as shown in FIG. 3 (E) and cannot be used as a clock signal. In particular, when the mark rate of the transmission line code is small, the timing component included in this signal becomes small, so the tank circuit output level becomes small, and the problem arises that the pulse clock signal may be disturbed if it is affected by noise first.

In order to solve this problem, in the past, the rising and falling parts of the tank circuit input pulse were smoothed as shown in the circuit shown in Figure 2, and the noise component superimposed on the tank circuit output was created as shown in Figure 3 (G). is suppressed. Furthermore, a sine wave and noise proportional to the input pulse amplitude are superimposed on the output level of the tank circuit.

FIG. 4 shows the waveform of the tank circuit output depending on the input amplitude of the tank circuit. Here, FIG. 4(a) shows the case of large input, and FIG. 4(b) shows the case of manpower factor. When the input level becomes smaller for input pulses with the same mark rate, the signal with superimposed noise approaches the threshold level as shown in Figure 4, so the fluctuation of the discrimination uncertainty width of the threshold level causes disturbances in the pulse crotter waveform. may occur. For this reason, large amplitude levels, such as general logic I
I had to enter C level.

Furthermore, in order to avoid the influence of the aforementioned noise, the delay phase of the tank circuit must be limited and used, which is a major constraint on the realization of the tank circuit, and it is difficult to design the tank circuit. leading to higher prices.

In addition, although the noise component is suppressed in the conventional usage method, noise is still superimposed, and there is an unstable factor where the pulse clock signal suddenly becomes distorted due to temperature fluctuations in the pulse shaping circuit or variations in elements due to manufacturing. It was left as it was.

Furthermore, in order to convert the tank circuit into an IC, the input level of the tank circuit must be changed to conventional CMOS or TTL.

Since it has to be used at a much lower level than the current level, it has been impossible to integrate the tank circuit into an IC.

For this reason, it had to be realized with high power consumption, high price, and large implementation scale.

The object of the present invention is to eliminate these problems and provide a lock regeneration circuit which can be integrated into an integrated circuit after completely eliminating the unstable elements of the tank circuit.

(Means for Solving the Problems) The clock regeneration circuit of the present invention inputs a transmission path equalization signal in the form of a binary encoded signal to one end of a first resistor, and connects the other end of the first resistor to a tank. The output of the tank circuit is connected to the input of the circuit and one end of the capacitor, the output of the tank circuit is grounded through a second resistor, and the first input of the differential amplifier is connected, and the other of the capacitor is connected to one end of the third resistor. and the other of the third resistors is grounded through a fourth resistor and connected to the second human power of the differential amplifier, so that the output of the differential amplifier is output as a pulse clock signal. It is something.

(Example) Next, the present invention will be explained by way of example with reference to the drawings.

FIG. 1 is a block diagram of a clock recovery circuit according to an embodiment of the present invention. In addition, Figures 3 (A) to (E) are diagrams showing waveforms in the tank circuit, especially Figures 3 (A) and (E).
(f) shows the input pulse waveform of the tank circuit, and FIGS. 3(b), (d), and (g) show the output waveform of the tank circuit. Furthermore, FIGS. 3(c) and 3(e) are diagrams showing output waveforms of the clock recirculating circuit.

Referring to FIG. 1, the glue regeneration circuit of the present invention inputs a transmission path equalization signal converted into a binary encoded signal by a binary encoding circuit 1 to one end of a first resistor 11, and resistance 1
1 is connected to the input end of the tank circuit 3 and one end of the capacitor 15, and the output end of the tank circuit 3 is grounded via the second resistor 12 and connected to the first input end of the differential amplifier 5. The other end of the capacitor 15 is connected to one end of the third resistor 13, the other end of the third resistor 13 is grounded via the fourth resistor 14, and the second The differential amplifier 5 is connected to the input terminal of the differential amplifier 5, and outputted from the output terminal B of the differential amplifier 5 as a pulse clock signal.

To explain the operation in this configuration in more detail, first, the equalized signal input to the input terminal A is binary encoded in the binary encoding circuit 1, and the timing wave is extracted in the tank circuit 3 to generate a sine wave. After obtaining, the signal is input to the first input terminal of the differential amplifier 5. Further, the binary encoded signal is inputted to the second input terminal of the differential amplifier 5 after obtaining a waveform equivalent to the noise generated at the output of the tank circuit 3 via the capacitor 15 and the third resistor 13. be done. As a result, the noise component, which has been a problem in the prior art, is removed by the common mode noise removal action of the differential amplifier 5, and a pulse clock waveform without disturbance as shown in FIG. 3(b) can be stably obtained. As a result, since the delay phase operates stably in any phase state, a tank circuit can be designed with a free amount of delay, and a tank circuit with high characteristics and low cost can be employed. Furthermore, the tank circuit input pulse level enables reliable operation not only at large amplitude levels such as the conventional CMO9 or TTL level, but also at small amplitude levels used in various LSIs. It becomes possible to convert it into an LSI.

(Effects of the Invention) As explained above, according to the present invention, unstable elements such as noise can be completely removed from conventional circuits that are expensive, have a large implementation scale, have high power consumption, and cannot be integrated into LSI. L on top
Since it becomes possible to implement SI, it has the effect of significantly reducing the implementation scale, lowering power consumption, and lowering costs.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a clock regeneration circuit according to an embodiment of the present invention, Fig. 2 is a block diagram of a conventional clock regeneration circuit, and Figs. 3 (A) to (E) are diagrams showing waveforms in a tank circuit. , Figure 4 (a). (b) is a diagram showing the output waveform of the tank circuit depending on the tank circuit input level. 1... Binary encoding circuit, 2... Integrator, 3... Tank circuit, 4... Clock shaping circuit, 5... Differential amplifier, 11.12, 13.14... Resistor, 15... Capacitor, A... Equalization signal input terminal, B
...Pulse clock signal output terminal. Agent Patent Attorney Toshikichi Somekawa Figure 3 Section 4 Procedures (Fu Zhengqin F (method) 1. Indication of the case 1988 Patent Application No. 27740 2. Name of the invention Clock regeneration circuit 3. Person making the amendment Relationship to the incident Patent applicant address 5-33-1 Shiba, Minato-ku, Tokyo Name (
423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent ■101 Address 11-11 Uchikanda-chome, Chiyoda-ku, Tokyo
No. Fujii No.-Building March 31, 1988 (Shipping date: April 28 of the same year) 6.
Target of correction +--^ Between "Diagram shown" and "Figure 4" on page 9, line 2 of the specification, Figure 3 (f) shows the human pulse waveform of the tank circuit. Figure 3(g) is a diagram showing the output waveform of the tank circuit, and 1 is added thereto.

Claims (1)

[Claims] A binary encoded transmission line equalization signal is input to one end of a first resistor, the other end of the first resistor is connected to the input end of a tank circuit and one end of a capacitor, and the output end of the tank circuit is connected to the input end of the first resistor. ground through the second resistor and the first resistor of the differential amplifier.
The other end of the capacitor is connected to one end of a third resistor, the other end of the third resistor is grounded via a fourth resistor, and the second end of the differential amplifier is connected to the input terminal of the differential amplifier. A clock regeneration circuit connected to an input terminal and outputting the output of the differential amplifier as a pulse clock signal.