JPH04212537A - Clock reproducing circuit - Google Patents

Abstract

PURPOSE:To prevent the instability of a clock reproducing operation caused by the noise component of the clock reproducing circuit to extract a timing component for identifying and reproducing a digital transmission line signal. CONSTITUTION:Two threshold values VH and VL are set corresponding to the direct current component of a signal binary coding a digital transmission line signal A, and the levels of these threshold values are compared with that of a sine wave output (a) from a tank circuit 3 by comparator circuits 6 and 7. These compared outputs (b) and (c) are defined as the set/reset inputs of an RS flip-flop 8, and an output (d) of this flip-flop 8 is defined as a regenerative clock.

Description

[Detailed description of the invention]

0001

TECHNICAL FIELD The present invention relates to a clock regeneration circuit, and more particularly, to a clock regeneration circuit that extracts a clock signal, which is a timing component, from an equalized amplified signal obtained by equalizing and amplifying a digital transmission signal in order to identify and reproduce the same. The present invention relates to a clock recovery circuit for

0002

[Prior Art] Generally, in digital transmission systems,
A self-timing method is widely used in which a clock signal, which is a timing component, is extracted from a transmission line equalized amplified signal and the clock signal is generated in order to identify and reproduce an equalized waveform.

FIG. 2 schematically shows a conventional clock recovery circuit using the self-timing method. A binary encoding circuit 1 binary encodes a digital transmission line equalized amplified signal A.

The noise component of this output is suppressed in an integrating circuit 2, and a sine wave, which is the fundamental frequency component of the timing component included in the binary encoded signal, is extracted in a tank circuit 3. This sine wave signal is amplitude limited and waveform shaped in the pulse shaping circuit 4 to obtain a clock pulse.

When a binary encoded signal is input to the tank circuit 3, the ideal tank circuit output waveform is a sine wave as shown in FIG. Can be used as

However, in the tank circuit, the high frequency portions of the rising and falling edges of the input pulse are superimposed on the tank circuit output as noise proportional to the input pulse amplitude, as shown in FIG. 3(b). Due to this noise, when the output of the tank circuit exceeds the threshold level for shaping, the output of the pulse shaping circuit becomes as shown in FIG. 3(c) and cannot be used as a clock pulse.

In particular, when the mark rate of the transmission line code is small, the timing component included in the input signal becomes small, so the output level of the tank circuit also becomes small, and the clock pulse becomes disturbed due to the influence of the previous noise. Become. Therefore, an integrating circuit 2 is inserted before the tank circuit 3 to smooth the rise and fall of the input pulse of the tank circuit as shown in Fig. 3(d), and the noise component superimposed on the tank circuit output is reduced as shown in Fig. 3(d).
This is suppressed as shown in e).

However, even when the mark rate of the transmission line code is the same, when the amplitude level of the tank circuit input becomes smaller, the signal with superimposed noise approaches the threshold level of the shaping circuit as shown in Figure (f), and the threshold level The fluctuation of the identification uncertainty width causes disturbances in the clock pulse. For that purpose, CMOS
It is necessary to input an amplitude level signal such as level or TTL level to the tank circuit.

[0009]

OBJECTS OF THE INVENTION An object of the present invention is to provide a clock regeneration circuit capable of removing unstable elements in a tank circuit and extracting and reproducing stable clock pulses.

0010

[Structure of the Invention] A clock recovery circuit according to the present invention includes a binary encoding means for binary encoding an equalized amplified signal obtained by equalizing and amplifying a digital transmission signal, and an input of the binary encoded signal. a sine wave signal generating means for extracting a fundamental frequency component of a clock signal component included in this signal to generate a sine wave signal; level signal generating means for generating a pair of level signals symmetrical with respect to the center level of the wave signal; a pair of comparing means for comparing the levels of each of the pair of level signals and the sine wave signal; It is characterized in that it includes an RS flip-flop whose comparison output is used as a set and reset input, and the output of this flip-flop is used as a reproduced clock signal.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Examples of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, and parts equivalent to those in FIG. 2 are designated by the same reference numerals. The transmission line equalized signal A is binary encoded by a binary encoding circuit 1 and then passed to an integrating circuit 2.
Its rise and fall are smoothed and input to the tank circuit 3. In this tank circuit 3, a timing component is extracted to obtain a sine wave a having the frequency of this timing component, and inputted to two voltage comparison circuits 6 and 7.

On the other hand, the binary encoded signal is converted into a DC signal according to the amplitude and mark rate by the rectifier circuit 9, level-converted by the voltage level conversion circuit 5, and inputted to the two voltage comparison circuits 6 and 7. be done. It is assumed that the output levels VL and VH of the level conversion circuit 5 are vertically symmetrical levels with respect to the center level (ground level) of the sine wave signal, as shown in FIG. 4(a).

In this case, the output level of the rectifier circuit 9 is proportional to the amplitude level of the input signal and the mark rate, and the higher the mark rate, the higher the rectified output level. Here, since the output amplitude level of the tank circuit 3 is proportional to the input amplitude of the tank circuit and the mark rate of the input signal, the levels VL and VH proportional to the output amplitude level of the tank circuit are the thresholds of the comparison circuits 6 and 7. It will be set as .

The tank circuit sinusoidal signal a has a threshold value VL.
and VH in comparison circuits 6 and 7, respectively,
Comparison outputs b and c are obtained as shown in FIGS. 4(b) and 4(c). Comparison outputs b and c are used as set and reset inputs for an RS flip-flop (FF) 8.

In this FF8, the set signal (S) is “1”.
”, the output d becomes “1”, and when the reset signal (R) is “1”, the output d becomes “1”. Also, when both S and R are “0”, the output d returns to the previous state. .In addition,
Since it is impossible for both S and R to be "1" due to the setting, the output d will not become unstable. Therefore, this FF
The output d of 8 is as shown in FIG. 4(d).

[0017] By configuring the pulse shaping function section to use two threshold values in this manner, relative noise tolerance is improved and noise generated at the tank circuit output can be eliminated.

[0018]

As described above, according to the present invention, no matter what the delay phase of the tank circuit is, an accurate clock can be obtained by stably operating against noise superimposed on the output of the tank circuit. Therefore, it is possible to freely select a tank circuit with an arbitrary amount of delay, and there is an effect that an inexpensive tank circuit can be used.

Furthermore, the input level of the tank circuit is
Not only large amplitude levels such as MOS and TTL, but also various L
Another advantage is that it can operate reliably even at the amplitude level used in SI.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional clock recovery circuit.

FIG. 3 is a signal waveform diagram showing the operation of a conventional clock recovery circuit.

FIG. 4 is a signal waveform diagram showing the operation of the embodiment of the present invention.

[Explanation of symbols]

1 Binary encoding circuit 2 Integral circuit 3 Tank circuit 5 Level conversion circuit 6,7 Voltage comparison circuit 8 RS flip-flop 9 Rectifier circuit

Claims (1)

[Claims] 1. Binary encoding means for binary encoding an equalized amplified signal obtained by equalizing and amplifying a digital transmission signal, and a clock signal included in this signal using the binary encoded signal as input. a sine wave signal generating means for extracting a fundamental frequency component of the component to generate a sine wave signal; and a sine wave signal generation means each having a level corresponding to the DC component of the binary encoded signal, and having a level corresponding to the center level of the sine wave signal. Level signal generation means for generating a pair of symmetrical level signals; a pair of comparison means for comparing the levels of each of the pair of level signals and the sine wave signal; and the pair of comparison outputs as set and reset inputs. What is claimed is: 1. A clock regeneration circuit comprising: an RS flip-flop; the output of the flip-flop is used as a regeneration clock signal.