CA2058387C - Method and circuit for regenerating the binary bit stream from a ternary signal - Google Patents

Abstract

Method and circuit for regenerating the binary bit stream from a ternary signal In the application P 40 41 717, an improvement in the signal-to-noise ratio with a bit stream regenerator was achieved using a circuit simplified in comparison with the Viterbi detection. The object of the present invention is to make it possible to employ this circuit for a PR4 signal and to increase the transmission reliability.
Two value sequences can be formed by demultiplexing the scanning values of the ternary PR4 signal and these correspond to signals whose impulses are directed alternately positive and negative with respect to a center line. The two scanning value sequences are processed in the time-division multiplex in a circuit corresponding to the older application (Figs. 9 and 10).
In particular for the bit regeneration in a digital video recorde.

Description

.20583x1 Method and circuit for regenerating the binary bit stream from a ternary signal The invention relates to a method and a circuit for regenerating a binary bit stream from a ternary signal.
Such a method is, for example, employed with the "Viterbi Detection" and is more closely described in "IEEE
Transactions on Communications", Vol. Com-34, No. 5, May 1986, pp. 454 through 461. With this known bit regeneration, a reduction in the error rate or, respectively, an improvement in the signal-to-noise ratio in an order of magnitude of 1 - 3 db is achieved compared to circuits having a pure threshold value detector.
It is the object of the invention to specify a method for the regeneration of the binary signal which, like the named, known regeneration, exhibits an increased signal-to-noise ratio as against a threshold value detector, but can be realized using simpler circuitry.
The invention may be summarized as a method of regenerating the binary bit stream from a ternary signal which has been obtained by sampling a binary recording track and consists of pulses which are alternately positively and negatively directed relative to a central line, where sample values are obtained from the pulses with the aid of an A/D
converter clocked with the regenerated bit clock signal, where a threshold value in each case exists for the sample values of the positive and negative pulses, characterised in that each threshold value overshooting whose sign has changed compared to the previous threshold value overshooting is initially ~.205838~
- la -evaluated as a level transition of the binary bit stream, and that in the case of a plurality of consecutive overshootings with the same sign, the sample value with the greatest threshold value overshooting defines the final position of the level transition.
The invention may be summarized as a circuit for the implementation of a process according to any one of claims 1 to 5 for the regeneration of the binary bit stream from a ternary signal, which has been obtained by sampling a binary recording track and consists of pulses which are alternately positively and negatively directed relative to a central line, where sample values are obtained from the pulses with the aid of an A/D converter clocked with the regenerated bit clock signal, where the threshold value fed to a second comparator for detecting the threshold value overshootings is adapted with the aid of a logic circuit to the signal to be processed, characterised in that for the detection of the greatest threshold value overshooting, which defines the position of the level transition, in a first comparator the amount of the current sample value is compared with the amount stored in the register and in the case of every threshold value overshooting with a change of sign and in the case of every determination of an increase in amount the register is loaded with the amount of the current sample value.
The method according to the invention therefore renders possible circuits which have, regarding the error rate or signal-to-noise ratio respectively, the advantages of the known Viterbi detection but function with a lower expenditure .2058387 - lb -on circuitry.
The known Viterbi detection and the invention are explained in the following by means of the drawing. Therein is shown:
Fig. 1 a block circuit diagram of the complete arrangement, D 91/041*

2~?~338'~
Fig. 2 curves for illustrating the signals which appear upon scanning the tape and bit regeneration, , Fig. 3 a block circuit diagram of a circuit according to the invention, Fig. 4 an extract from Fig. 3, Fig. 5 curve profiles for illustrating the operation of the circuit according to Figs. 3, 4, and Tab. 1 a code table for the analog-to-digital converter employed in Fig. 3, Figs. 6, 7, 8 illustrations concerning the origin of the so-called PR4 signal, -Fig. 9 an example of a circuit for the further development of the invention for a PR4 signal, Fig. 10 an extract from the circuit according to Fig. 9.
Fig. 1 shows the block circuit diagram of a circuit for retrieving the bit stream recorded on a magnetic medium, and Fig. 2 shows the associated courses of the signal. The magnetic track M contains the bit pattern in binary form, i.e. in the form of oppositely magnetized areas, a~ is indicated by the symbols N (north pole) and S (south pole).
In the playback head the playback voltage is induced by the flux changes between the areas N and S or S and N. This voltage represents roughly the differentiated bit pattern.
The impulses generated by the magnetizaton transitions are narrowed down or, respectively, freed from the influences of neighboring bits in the equalizing circuit P. The original bit stream can be obtained from the equalized signal E in circuit section G in various ways, for example, by integration, zero crossing detection and scanning using the bit timing (clock) regenerated with a PLL circuit. The advantage of this method is that by way of integration from the ternary signal E, a signal is generated whose evaluation using the zero crossing detector is essentially independent of the level. Insofar as the binary signal contains very D 91/041* - 3 -low frequency spectrum components and large runlength values, it is more favorable to evaluate the ternary signal E directly using a level determiner. A Schmitt trigger can, for example, serve as the level determiner which alternately registers the positive and negative impulses. However, in order to maintain the optimum trigger points, an automatic amplification regulation is required for the ternary signal E. The binary output signal from the Schmitt trigger is scanned using the regenerated bit clock to determine the final position of the level transitions. An improvement in the interference immunity can be achieved upon signal evaluation using the aforementioned known Viterbi detection of the ternary signal E. With this known circuit the signal , is preferably processed in two circuit branches. Herefor, the signal is scanned alternately by two analog-to-digital converters. Apart from the analog-to-digital converter, each branch contains various registers, comparators, adders and a RAM with an addressing facility.
In the following, a circuit for regenerating the bit stream from the ternary signal is described which also has an increased interference immunity compared to the simple level determiner but, however, requires a considerably lower expenditure on circuitry-. Apart from an analog-to-digital converter, only some registers and two comparators are required.
Fig. 3 shows the block circuit diagram of such a bit stream generator, and Fig. 5 illustrates some associated signal curves. The equalized ternary signal E is scanned by the analog-to-digital converter 1 with the help of the regenerated bit clock. The scanning times are set by the phase-shift control of the clock regeneration circuit (PLL) roughly to the impulse peaks of the signal E.

D 91/041* - 4 -Table 1 shows, in excerpt form, the table for the digital output code of the analog-to-digital converter used here. In this case, the MSB stands for the algebraic sign while the remaining n-1 bits specify the amount A of the scanning values. It is practical to utilize the MSB (most significant bit) for the bias voltage regulation at the input of the analog-to-digital converter. Herefor, a voltage generated from the average value of the MSBs and amplified is fed back to the input of the analog-to-digital converter via the low pass 2. Here the setting is arranged so that the "0" and the "1" appear as MSBs with roughly equal frequency.
The comparators 3 and 4 always examine only the amount A of the scanning values. In doing this, the comparator 3 establishes whether the scanning value A exceeds a predetermined threshold value S. The comparator 4 serves for determining the maximum scanning value up until the next time the threshold value is exceeded with an opposite algebraic sign. The respective maximum value determined is stored in the register 5.
Each time the threshold value is exceeded, the outputs of the gates 6 and 7 supply, depending on the algebraic sign (MSB), a negative impulse to one of the inputs of the RS
flipflop formed by the gates 8 and 9. The output signal D
from flipflop 8, 9 corresponds to the signal regenerated with a simple threshold value detector. The level transitons of signal D then appear, when the threshold value is exceeded with an altered algebraic sign for the first time. With the interference-free signal E, successive exceedings of the threshold value have alternating algebraic signs, i.e. each scanning value A which exceeds the threshold value S belongs to a level transition of the original bit stream. Upon successive exceedings of the threshold value with the same algebraic sign, the scanning D 91/041* - 5 -value with the largest amplitude will, with high probability, correspond to the actual level transition. The remaining values that exceed the threshold value are to be considered as interference. The circuit according to Fig. 3 now serves for determining the probably correct level transitions upon appearance of signal faults. The correction register 10 enables a later correction of the bit stream D.
The bit stream D is read into the correction register via the D-flipflop 15. One arrangement for the correction register 10 is shown in Fig. 4. The length of the two shift registers 11 and 14 corresponds to the maximum runlength of the signal because displacements in the level transition which may be necessary do not exceed the distance between the actual level transitions. The movement of the bits in the shift register 11, which always contains the final m bits of the scanned bit stream, is carried out via EXOR gate 12 which renders possible the inverting of a section of the bit stream, if required. The register 14 is reset, in a clock synchronous way, at every primarily determined level transition and set step-by-step,~lalth the bit clock, between the level transitions. The inverting of the bits in the shift register 11 can be triggered according to the steps set in the shift register 14 via the AND gates 13.
r Every level transition of the signal D generates a one-bit long, positive impulse T at the output of the EXOR gate.
The OR gate 17 operates so that the register 5 is not only loaded with the current scaning value not only upon establishment of a scanning value increase but also at every level transition of the signal D.
The gate 18 operates so that, upon establishment of a scanning value increase which is not connected with a level D _"91/041; - 6 -transition, the inverting of a series of bits is carried out in the shift register 10. The signal C which is necessary for this is delayed by one bit for the temporal matching by means of the D-flipflop 19.
The gate 20 operates so that the register 14 in the correction circuit 10 is reset at every level transition T
or at every level transition displacement which is carried out for the purpose of signal correction.
There is the possibilty that the threshold S can be automatically matched to the signal level and the signal quality. An increase in the frequency of occurence of the impulses Co means that the threshold S is set too low. A
threshold S which is set too high has the effect that some level transitions are no longer registered. Thereby, an alteration to the runlength statistic of the signal ensues in favor of the higher runlength values, or, respectively, the maximum runlength of signals with restricted runlength is exceeded, This information can be utilized for the automatic optimization of the threshold value S with the help of a logic circuit 21. The reference voltage V Ref of the analog-to-digital converter can also be adjusted via this logic circuit. Therewith, an automatic gain stabilization for the input signal E can be omitted, if applicable.
With the circuit described here, bit errors only occur when a value A caused by a fault is greater than the value of the neighboring level transition, or if, following overstepping of the threshold value as a result of a fault, the threshold value is again exceeded as a result of a fault but with an opposite algebraic sign. An optimization of the threshold value renders this event relatively improbable.
Consequently, the circuit causes an improvement in the D 91/041* - 7 -interference immunity with respect to the simple threshold value detector.
In Fig. 3, the circuit section consisting of the analog-to-digital converter 1, the two comparators 3 and 4, and the register 5, can also be built as an analog circuit.
The analog-to-digital converter and the register 5 are then replaced by scanning and holding circuits, and the two comparators replaced by analog comparators with binary outputs. An additional comparator can serve here for determining the algebraic sign of the scanning values, while the ternary signal E is sent via a full-wave rectifier for forming the value. The rest of the circuit can remain unchanged.
In the Figs. 3 through 5, a circuit was described which effects an improvement in the interference immunit~~ with the bit stream regeneration. In the above-mentioned publication, the improvement in the interference immunity is achieved using a Viterbi detector and in fact, concerns a partial response class IV signal (PR4).
While for the signal E used in Fig. 3 the high frequencies are particularly strongly boosted, with a PR4 signal it is, above all, the middle frequencies which are raised, thereby achieving an especially good interference immunity. The generation of the PR4 signal is shown schematically in Fig. 6 and 7. The signal E in Fig. 3 corresponds to a signal which has been created from the bit stream Din through the transmission function 1 - D, whereby D is the signal delay of 1 bit. Multiplication using the transmission function 1 + D then results in the PR4 signal (see Figs. 6 and 7). It can be seen that the PR4 signal possesses a smaller band width than the signal E.

D 91/041* - 8 -The PR4 signal can also be generated directly using the circuit with the transmission function 1 - DZ specified on the right in Fig. 6. The.PR4 signal is a ternary signal with the level values 1, 0, -1. A binary signal P can be obtained from this signal through the formation of values.
The signal P corresponds to a signal which was generated from the signal Din using the circuit specified on the right of Fig. 8. In this circuit, the input signal Din is combined in an EXOR gate with the signal delayed by two bit cycles. This signal modification can be cancelled through a precoding by means of the circuit specified on the left of Fig. 8 (Dout in Fig. 7). .
In the circuit according to Fig. 3, it Haas the special feature that in the signal E positive and negative impulses always appear alternatingly that was utilized for the error correction. As is shown in Fig. 7, that is no longer the case with the PR4 signal. Deviations from this rule occur when the number of directly successive half-waves for the length of one-bit is an even figure in the binary input signal Din. However, Fig. 7 also illustrates that,the PR4 signal consists of two impulse sequences which correspond to the above-mentioned rule and are combined in a time-division multiplex. In Fig. 7, not only in the sequence of all bits designated with "1" but also in the sequence of all bits designated with "2", negative and positive impulses appear always alternatingly. With this there exists the possibilty of also processing a PR4 signal by means of a correction circuit according to Fig. 3. For this, the PR4 signal is demultiplexed before or after the analog-to-digital converter and processed in two parallel branches according to Figs. 3 through 5 like with Viterbi detection.
Afterwards, the signal is reassembled using a multiplexer.
Using a circuit according to Figs. 9 and 10, the PR4 signal can also be processed directly in the time-division D 91/041* -multiplex. The extra expense with regard to the processing circuit for the signal E then merely consists of the following: the RS flipfl.op 6 through 9 is present twice.
The delay in register 5 as well as at points 15 and 19 is two bit cycles each, i.e. for each signal path there are two D-flipflops operated at the bit clock connected in series.
The flipflop 22 generates the change-over voltage U which ensures that the inputs of the RS flipflop 8, 9 and 8', 9' are bit-wise alternatingly activated and that the output voltages of the RS flipflop 8, 9 and 8', 9' are fed bit-wise alternatingly via the change-over switch 23 to the further processing circuit.
With the correction register 10 the expenditure is even reduced because only every second step of the shift register 11 is coupled to the following step via an EXOR gate.
Likewise, with the register 14 only every second step is synchronously reset.
The correction register 10' illustrated in Fig. 10 possesses three correction stages. Therefore, it can correct signal half-~Javes up to a runlength of 4 double bits, i.e. 8 bits. The signal example in Fig. 7 shows that increases in runlength can occur in the partial signals formed from even-numbered or, respectively, odd-numbered scanning values of the PR4 signal. However, it not absolutely necessary to increase the length of the correction register correspondingly. As the majority of the level transition displacements which are to be corrected only have a few bits, a good corrective effect can already be achieved using a relatively short correction register.
The interpulse period in the two partial signals 1 and 2 of the PR4 signal (Fig. 7? determines the duration of an error propagation as a result of a faulty decision. In D 91/041* - 10 -~Q'~~~~~
every case, an error propagation ends with the next correctly recognized level transition.
The circuit according to Fig. 9 and 10 triggers a regeneration of the bit pattern Din which is, for example, the bit pattern on a recording medium. If this bit pattern was generated by a precoding, for example, according to Fig. 8 left, then the original bit pattern must be regenerated through an additional code conversion (according to Fig. 8 right). As Fig. 10 shows, this code conversion circuit can be combined with the correction register.
The code conversion according to Fig. 8 right generates merely one double bit error from a,faulty bit, thereby causing practically no error propagation. The circuit according to Figs. 9 and 10 is, therefore, suitable for both signals with precoding and signals without precoding.
Compared with that, the known detector circuits for the PR4 signals generate the signal P from the signal Din. In order to obtain the signal Din, the code conversion circuit shown on the left of Fig. 8 would have to be connected downstream from the detector circuit. However, this circuit'already causes unlimited error propagation with just one single bit error. It is, therefore, customary to integrate this code conversion as a precoding prior to the signal transmission.
The known signal transmission facilities caith PR4 detection require this precoding. Compared with this, the PR4 detection method according to Figs. 9 and 10 is independent of the precoding.

Claims (14)

1. A method of regenerating the binary bit stream from a ternary signal which has been obtained by sampling a binary recording track and consists of pulses which are alternately positively and negatively directed relative to a central line, where sample values are obtained from the pulses with the aid of an A/D converter clocked with the regenerated bit clock signal, where a threshold value in each case exists for the sample values of the positive and negative pulses, characterised in that each threshold value overshooting whose sign has changed compared to the previous threshold value overshooting is initially evaluated as a level transition of the binary bit stream, and that in the case of a plurality of consecutive overshootings with the same sign, the sample value with the greatest threshold value overshooting defines the final position of the level transition.

2. A method according to claim 1, wherein in the output code of the A/D converter, the first bit indicates the sign of the sample values and the remaining bits indicate the amount of the sample values.

3. A method according to claim 1 or 2, wherein the bias voltage at the analogue input of the A/D converter is regulated with the aid of the first bit in such manner that positive and negative sample values occur approximately with the same frequency.

4. A method according to any one of claims 1 to 3, wherein for the regeneration of the binary bit stream from a ternary signal, which corresponds to a signal which has been formed by the addition of two identical signals offset from one another by the duration of one bit and consisting of pulses which are alternately positively and negatively directed relative to a central line, by demultiplexing of the sample values of the ternary signal two value sequences are formed which correspond to signals whose pulses are alternately positively and negatively directed relative to a central line, that each sample sequence is processed in a process according to any one of claims 1 to 3, and that then the individual signals are recombined in a multiplexer.

5. A method according to any one of claims 1 to 3, wherein for the regeneration of the binary bit stream from a ternary signal which corresponds to a signal which has been formed by the addition of two identical signals offset relative to one another by the duration of one bit and consisting of pulses which are alternately positively and negatively directed relative to a central line, the processing of the sample values of two value sequences takes place in accordance with time division multiplex in a process corresponding to any one of claims 1 to 3.

6. A circuit for the implementation of a process according to any one of claims 1 to 5 for the regeneration of the binary bit stream from a ternary signal, which has been obtained by sampling a binary recording track and consists of pulses which are alternately positively and negatively directed relative to a central line, where sample values are obtained from the pulses with the aid of an A/D converter clocked with the regenerated bit clock signal, where the threshold value fed to a second comparator for detecting the threshold value overshootings is adapted with the aid of a logic circuit to the signal to be processed, characterised in that for the detection of the greatest threshold value overshooting, which defines the position of the level transition, in a first comparator the amount of the current sample value is compared with the amount stored in the register and in the case of every threshold value overshooting with a change of sign and in the case of every determination of an increase in amount the register is loaded with the amount of the current sample value.

7. A circuit according to claim 6, wherein a flip-flop is provided for the generation of the preliminary binary bit stream and where in the case of threshold value overshootings the output of said flip-flop is set at the value corresponding to the sign.

8. A circuit according to claim 7, wherein the preliminary bit stream is input into a correction register clocked with the bit clock signal and where the length of said correction register corresponds approximately to the maximum run length of the bit stream to be regenerated.

9. A circuit according to claim 8, wherein in the correction register, the bit transportation takes place in a first register via EXCLUSIVE-OR gates, that a second shift register is provided which is set in stepped manner with the bit clock signal and is reset in the case of every threshold value overshooting with a changed sign, and that in the case of sample value increases with no change of sign the bits in the first register are inverted via the EXCLUSIVE-OR gates in accordance with the stages set in the second register, and the second register is likewise reset.

10. A circuit according to claim 6, wherein the logic circuit processes the correction frequency and/or the run length values of the uncorrected bit stream.

11. A circuit according to claim 10, wherein the logic circuit adjusts the reference voltage of the A/D converter.

12. A circuit according to any one of claims 6 to 11, wherein the A/D converter and the register are replaced by sample and hold circuits and that the comparators for detecting the threshold value overshootings and for detecting the maximum threshold value overshooting have analogue inputs and binary outputs.

13. A circuit according to claim 6 for regenerating the binary bit stream from a ternary signal, which corresponds to a signal which has been formed by the addition of two identical signals offset relative to one another by the duration of one bit and consisting of pulses which are alternately positively and negatively directed relative to a central line, where for the generation of the preliminary binary bit stream two RS flip-flops are provided for the processing of the even-numbered and odd-numbered sample values in accordance with time division multiplex and where in the event of threshold value overshootings the outputs of said RS
flip-flops are set at the value corresponding to the sign.

14. A circuit according to claim 13, wherein the preliminary bit stream is input into a correction register which is clocked with the bit clock signal and whose length corresponds approximately to the maximum run length of the bit stream to be regenerated, where in a first shift register the bit transportation takes place via an EXCLUSIVE-OR gate in the case of every second stage, and that a second shift register is provided which is set in stepped manner with each bit clock signal, that an inversion of the bits in the first register can be effected via the EXCLUSIVE-OR gates in accordance with the set stages of the second register, and that the resetting of the second register takes place in a synchronous manner for every second stage.