DE19549400B4 - PRML regenerating device - Google Patents

Abstract

A maximum likelihood decoder in a PRML regeneration apparatus for regenerating a signal read from a storage medium by a head which is digitally conditioned to obtain a sequence of signal values (Y _n ) indicative of ternary regenerative signals having upper and lower threshold levels be compared, wherein the upper and lower threshold levels are adjustable,
with a ternary determination circuit (1, 14 . 15A ) for deriving the ternary regenerative signals by comparing the read signal with upper and lower threshold levels, wherein the upper and lower threshold levels are changed depending on the comparison result,
which ternary determining circuit has a memory (11, 15A ) containing a correspondence table for upper and lower threshold levels corresponding to the result of the comparison,
an input circuit (55, 502, 18 ) for converting the ternary regenerative signals into binary data,
a data buffer (2, 14 ) for holding the binary data from the input circuit, and
a correction circuit (3, 14 ) for detecting a consecutivity of each bit signal (DDt 0, DDt 1) of the ternary regenerative signals and for ...

Description

BACKGROUND OF THE INVENTION

Field of the invention

The The present invention relates to a PRML regeneration device, in the case of partial reaction or partial response signal transmission with a Seqenzdetektion the greatest probability or maximum likelihood sequence detection is used.

Description of the Related Art

From the EP 0 369 962 A2 a device is known in which an analog read signal is first processed and then fed to a decoder, in which it is compared with fixed predetermined upper and lower threshold levels. The threshold levels are constant quantities, as already apparent from the abstract of this document.

The DE 4041717 A1 shows a maximum likelihood (Viterbi) decoder in which binary signals are derived from a read signal, but not a ternary determination. How to get in 5 a read signal E is compared to a single binary data threshold (MSB) S. These MSB are integrated (A) and the peak value (B) of the integrated result is held. Further, the integration result (A) is compared with the held peak value (B) to detect the continuity of the same polarity peak. An erase pulse (C) is generated by the detection result and corrects MSB in the data buffer (10). This document thus shows a maximum likelihood decoder for the binary determination of read signals and for detecting and correcting the binary data from the binary signals.

The PRML (partial response signal transmission with maximum likelihood sequence detection) has been in recent years for reinforcement the recording density of magnetic disk and magneto-optical disk devices used. In such a PRML system is a PRML regeneration device provided for regenerating a read signal.

In a disk storage device in which the partial response signal transmission is used, the regeneration device is a waveform equalizer circuit and a maximum likelihood decoder. A receive filter the waveform equalizer circuit of this regeneration circuit equalizes / shapes an output of a recording channel to a Partial response signal. Then take the maximum likelihood sequence detector (Maximum-likelihood decoder) after the execution a ternary determination of Equalization signal before the maximum likelihood detection, and reconstructed so a recorded data chain.

This type of PRML regeneration device is described in the descriptions of U.S. Patent 5,060,088 . U.S. Patent 4,644,564 . U.S. Patent 4,707,681 . U.S. Patent 4,786,890 and U.S. Patent 4,888,775 disclosed.

at the conventional one PRML regeneration devices become parameters of the waveform equalizer circuit and the maximum likelihood decoder are set to fixed values when they are derived from the factor of the device. Therefore, too set the characteristics of the waveform equalizer circuit and the maximum likelihood decoder. For example, in a ternary determination circuit of the maximum likelihood decoder, a distance between two slice levels set to divide the input signal.

Actually however, the scanning signal quality deteriorates due to a defect on a magnetic medium. Further there is also a deterioration in one case the scanning signal quality, where a signal-to-signal interference described by a polynomial (1-D) can not be controlled quantitatively due to an equalization error can. Furthermore There is a deterioration in signal quality, which is a result of a scatter derived from the characteristics of an MR (magnetoresistive) head is. When the equalization error due to the characteristics of the the above head, the magnetic medium and the waveform equalizer circuit occurs, there is a problem insofar as according to the state the technique in which the distance between the above cutting levels is fixed, no effective maximum likelihood decoding is performed can.

If the characteristics of the head and the waveform equalizer circuit are not correct, also arises the problem that often one Equalization error is generated, and no optimal regeneration carried out can be.

Further shows the conventional PRML regeneration device insofar a problem, as a configuration of it is complicated.

SUMMARY OF THE INVENTION

It is the object of the present invention to provide a maximum likelihood decoder in a PRML regeneration device, the size of the decoding process with a comparatively simple circuit design Security can perform.

These The object is solved by the features of the claim.

In Such a PRML regeneration device may have an equalization error be minimized.

at execution A correct maximum likelihood decoding can be a distance between Cutting levels are set optimally.

In a PRML regeneration device for minimizing an equalization error a head characteristic can be optimally set.

Also can optimel a characteristic of a waveform equalizer circuit be set.

The Control circuit of a PRML regeneration device may be a distance set variably between the slice levels of the maximum likelihood decoder, whereby an optimal ternary determination, which corresponds to an equalization error quantity can.

The Ternärbestimmungsschaltung may be the use of memory to store the conversion table to involve. If at the ternary determination the sample (equalization output) and one of the current slice levels can be determined, a result of ternary determination and the next Schnittpe gel to be obtained. Then the conversion table can be provided, which the ternary determination result and the next Slice level, the sample and the current slice level match, stores. Then, where is the sample and the current slice level serve as inputs, the corresponding one Ternärbestimmungsergebnis and the next one Cut levels are obtained by searching the conversion table becomes.

at With such a construction, the ternary determination can be easily achieved by the Provision of memory performed be, and this leads to a simpler configuration. Furthermore, the ternary determination simply be done by accessing the store, and therefore it is possible the ternary determination at high speed. In addition, the ternary determination characteristic changed as in the case of change the distance between the cutting levels by only the content of the Memory is varied. Therefore, the determination characteristic slightly changed become.

If the error size of a Pulling operation of a multiplexer for selecting high-quality m-bits low-order m-bits can be large in a PRML regeneration device that practice low-order bits have a small influence on the control variable, whereas the high quality bits exert a large influence on the control quantity. If in contrast, in the station arooperation a low fluctuation occurs, practice the high-quality bits exert little influence on the control variable, wherein the low-order bits exert the great influence on the control variable. Out For this reason, in the drag operation, the control is based on the high quality bits performed. If the fluctuation is low, after the data in the station aroperation are essentially converged, the control is based on the low order bits performed. Accordingly, the chooses Multiplexer the high and low bits in dependence from the drawing operation and the station operation. Consequently, it is with respect to n-bit inputs a smaller number, i. m-pieces of charge pump circuits, capable of converting the digital error signal to the analog control quantity. Therefore, the number of charge pump circuits can be reduced.

Also can in the drag operation control based on the high quality Bits performed become. If the fluctuation is small after the data in the stationary operation are essentially converged, the control is based on the least significant bits are made. For this reason, the chooses Multiplexer the high and low bits in dependence from the drawing operation and the station operation. Consequently, it is with respect to the n-bit inputs lower number, i. m-pieces of charge pump circuits, capable of converting the digital error signal to the analog control quantity. Therefore, the number of charge pump circuits can be reduced.

One Voltage control filter can be the use of a passive filter of integration type. According to the prior art the reason why the voltage control filter is the use of a gm amplifier involved that the gm amplifier filter the frequency characteristic per zone on the disk changes. It However, it is known that the Variation of the frequency characteristic due to the track density per Zone to some extent by the eigenoperation of the voltage frequency oscillator can be absorbed. consequently involved in this embodiment the voltage control filter the use of the passive filter of Integration type. With this arrangement, the passive filter of Integration type can be formed in a simple configuration. Furthermore The voltage control filter can be constructed at a low cost become.

An offset error can be detected in the slit pattern and from the amplitude value in the data pattern be subtracted. Therefore, the amplitude value input to the phase comparator can be corrected to a value containing no offset error. With this processing, it is possible to prevent an influence of a positive / negative asymmetrical waveform of the MR head from being exerted on the phase error. Further, the offset error has an influence when the determination value is zero. For this reason, a level at which the determination value is zero is detected in the gap pattern as a displacement error. Thereby, the displacement error can be accurately detected.

Other Features and advantages of the present invention will be apparent from the following Description in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are included in the description and form part of it, illustrate preferred herein embodiments of the invention, and serve, together with the above, general Description and the detailed description given below the preferred embodiments, the explanation of the principle of the invention, wherein:

1 Fig. 10 is a block diagram illustrating a PRML regeneration device;

2 is a block diagram showing a maximum likelihood decoder in the construction in 1 shows;

3 is a circuit diagram (part 1) showing the maximum likelihood decoder of the construction in FIG 2 illustrated;

4 is a circuit diagram (part 2) showing the maximum likelihood decoder of the construction in FIG 2 illustrated;

5 Fig. 12 is an illustration for assistance in explaining a maximum likelihood decoding operation;

6 a flow chart of the maximum likelihood decoding in the construction in 2 is;

7A and 7B Flowcharts of the slice level setting processing are;

8th Fig. 16 is a block diagram showing a setting circuit;

9 an explanatory view of a memory in the construction in 8th is;

10A and 10B Are flowcharts, each showing how an offset voltage is set;

11A and 11B Are flowcharts each showing how to set a characteristic of an MR head in an embodiment of the present invention;

12A and 12B Are flowcharts each showing how to set a characteristic of an electric filter;

13A and 13B Are flowcharts each showing how to set a characteristic of a cosine equalizer;

14 is a block diagram of a maximum likelihood decoder;

15A and 15B Representations are each one configuration of a ternary determination circuit in FIG 14 demonstrate;

16 an explanatory diagram showing a conversion table of the memory in 15A shows;

17 an illustration to assist the explanation of a conversion operation in the construction in 15A is;

18 is a representation showing a configuration of a data buffer in the construction in 14 illustrated in accordance with the present invention;

19 FIG. 12 is a diagram showing a configuration of an error detection circuit constructed in FIG 14 shows;

20 FIG. 10 is a diagram showing a configuration of an address mark detecting circuit constructed in FIG 14 shows;

21 a timing diagram of an error detection operation in the construction in 19 is;

22 a timing diagram of an error correction operation in the construction in 19 is;

23 an explanatory diagram showing an address mark in 20 shows;

24 Fig. 12 is a block diagram illustrating another PRML regeneration device;

25 is a block diagram showing a charge pump type D / A converter in FIG 24 shows;

26 an explanatory representation of the operation in 25 is;

27 FIG. 12 is a block diagram showing a modified example of the charge pump type D / A converter in FIG 24 shows;

28 a circuit diagram of a charge pumping circuit in 27 is;

29 Fig. 12 is a block diagram illustrating a phase synchronization circuit;

30 is a block diagram showing a voltage difference arithmetic unit in FIG 29 illustrated;

31 a timing diagram in a non-read state in the construction in 29 is;

32 a timing chart in a reading state in the construction in 29 is;

33 Fig. 11 is an explanatory view showing a phase synchronization operation;

34 Fig. 11 is an explanatory view showing a displacement error;

35 Fig. 12 is a block diagram showing a modified example of the phase synchronization circuit;

36 a circuit diagram of an error detection circuit in the construction in 35 is; and

37 a timing diagram in the construction in 35 is.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

1 Figure 13 is a block diagram illustrating a PRML regeneration device. This regeneration device is defined as a magnetic recording / regeneration device having a partial response class 4 and a maximum likelihood decoder can be used.

As in 1 illustrates an MR (magnetoresistance) head is used 10 for reading data on a magnetic disk. A head IC circuit 11 serves to drive the MR head 10 , A gain control amplifier 12 gives a read signal a predetermined gain and then outputs the signal. An equalizer filter (electric filter) 13 shows a (1 + D) characteristic and equalizes an output of the gain control amplifier 12 firmly. An analog-to-digital converter circuit 14 effects sampling of a binary data string at a signal transfer rate 1 / T at time nT + τ, and then outputs a digital sample Yn.

A cosine equalizer 15 is provided for correcting a partial response characteristic in a radial direction of the disc. In this cosine equalizer 15 For example, a tap coefficient is optimally set by a practice pattern. Further, this type is a cosine equalizer 15 constructed from a known transversal filter, such as in the description of U.S. Patent 5,060,088 revealed. The cosine equalizer can be replaced by a multi-tap digital filter, such as a ten-tap FIR filter.

A maximum likelihood decoder 16 processes the output sample Yn of the cosine equalizer 15 and reconstructs the record data string. When a recorded data sequence is regenerated to obtain a data-data correlation, the maximum likelihood decoder detects 16 a maximum likelihood sequence. The operation of this maximum likelihood decoder 16 is described in "Optimal Reception for Binary Partial Response Channels", The Bell System Technical Journal, Vol. 51, No. 2, February 1992 (ATT). A construction of this maximum likelihood decoder 16 becomes with reference to 3 and subsequent figures.

A 9-bit data value from the maximum likelihood decoder 16 decoded data sequence is from an 8/9 decoder 17 converted to 8-bit data. This decoder 17 is also known, as in the descriptions of the U.S. Patent 4,707,681 and U.S. Patent 4,786,890 revealed. An ECC circuit 18 detects and corrects an error in the decoder 17 decoded data sequence.

A control circuit 19 is constructed from a microprocessor. The control circuit 19 observes the output sample Yn of the sample detection circuit 21 which will be described below, and automatically controls a head drive current of the head IC circuit 11 to minimize an equalization error. The control circuit 19 Also automatically controls a frequency characteristic of the electric filter 13 , an offset voltage of the A / D converter circuit 14 and an equalization coefficient of the cosine equalizer 15 , Further, the control circuit controls 19 automatically a distance of a cutting level of the maximum likelihood decoder 16 in accordance with the result of detection by the ECC circuit 18 ,

A store 20 stores a value of the controlled offset voltage of the A / D converter circuit 14 , The memory 20 Also stores a head drive current value of the head IC circuit 11 per capita, a frequency characteristic value of the electric filter 13 , the equalization coefficient of the cosine equalizer 15 and the distance of the cutting level of the maximum likelihood decoder 16 ,

The scan detection circuit 21 as described below with reference to 8th described, determines a level of the sample Yn of the cosine equalizer 15 and also outputs the classified sample. The scan detection circuit 21 is used when the control circuit 19 performs the automatic control to minimize the equalization error.

2 is a block diagram showing the maximum likelihood decoder in 1 illustrated. 3 and 4 are schematics of the maximum likelihood decoder. 5 Fig. 13 is a diagram for assistance in explaining the operation of the maximum likelihood decoder. 6 FIG. 10 is a flowchart of the maximum likelihood signal processing. FIG.

As in 2 Fig. 11 illustrates the input data strings by an interleaving circuit 16-3 into an odd-numbered data string and an even-numbered data string. The data of the odd-numbered data string becomes a maximum likelihood decoder aligned to an odd-numbered data string 16-1 entered. Further, the data of the even-numbered data string becomes an maximum-likelihood decoder aligned to an even-numbered data string 16-2 entered.

Every maximum likelihood decoder 16-1 . 16-2 contains level cutters (ternary discriminators) 30-1 . 30-2 , Slice level update circuits 31-1 . 31-2 , Data buffer 32-1 . 32-2 , Pointer 33-1 . 33-2 and error detection circuits 34-1 . 34-2 ,

The level cutter 30-1 . 30-2 perform a level cut using an upper (+1 side) cutting level Δn + 1 and a lower (-1 side) cutting level Δn-1, whereby a ternary determination value Xn is obtained. The slice level update circuits 31-1 . 31-2 give to the level cutter 30-1 . 30-2 the upper slice level Δn + 1 and the lower slice level Δn-1 included in one of the control circuit 19 in agreement with the ternary determination value.

The data buffers 32-1 . 32-2 are constructed from serial registers and store a plurality of consecutive determination values. The pointers 33-1 . 33-2 indicate the determination values to be checked. The error detection circuits 34-1 . 34-2 detect an error of the determination value and correct the determination values of the data buffers 32-1 . 32-2 ,

3 illustrates details of the slice level update circuits 31-1 . 31-2 , Here is just the slice level update circuit 31-1 Fig. 11 illustrates the slice level update circuit 31-2 however, it has the same configuration.

As in 3 shown, set time registers 310 . 311 the time of the sample Yn. A section amplitude setting register 312 sets an amplitude A as the distance from that of the control circuit 19 fixed cutting level.

The one with this control circuit 19 connected storage 20 For example, with respect to these cylinder positions 0 to m, 1000 cylinders are set in one group, and the amplitude of one cylinder position represents the amplitude of this group.

Accordingly, the control circuit reads 19 upon receipt of a head number to be selected and the cylinder position, the group amplitude in this cylinder position of the head number from the memory 20 and sets this amplitude in the register 312 ,

An adder 313 subtracts the sample Yn from that in the register 312 set amplitude A. An adder 314 subtract those in the register 312 set amplitude A from the sample Yn. An initial value of the cutting level from the control circuit 19 is in a cut start value set register 315 set. A polarity bit inverter circuit 316 inverts a polarity bit of the register 315 and generates an initial value of the lower (-1 side) cutting level.

A selector 317 generates select signals of a pair of multiplexers 318 . 319 in accordance with a determination value 1PJOD. The selector 317 enters a # 3 input selection at a read start time. If the determination value is [1], the selector gives 317 Further, a No. 1 input selection is output, and if the determination value is [-1], outputs No. 2 input selection.

The first (+ side) multiplexer 318 has three pieces of input terminals, and outputs one input of the terminals selected by the selection signal as the upper slice level. The sample Yn is input to the first input terminal. An output of the adder 313 is input to the second input terminal. An initial level of the register 315 is input to the third input terminal. Therefore, the first multiplexer gives 318 , as in 5 illustrates the initial level in the form of the upper determination intercept level Δn + 1 at startup. Then there's the first multiplexer 318 if the determination value [1] is the sample Yn off. Furthermore, there is the first multiplexer 318 if the determination value is [-1], (set amplitude sample).

The second (- side) multiplexer 319 has three pieces of input terminals, and outputs as an inferior slice level one input of the terminal selected by the selection signal. An output of the adder 314 is input to the first input terminal. The sample Yn is input to the second input terminal. An inverted initial level of the inverter circuit 316 is input to the third input terminal. Accordingly, the second multiplexer outputs 319 , as in 5 illustrates the initial level in the form of the -1 determination level Δn-1 at startup. Then there is the second multiplexer 319 when the determination value is [1] (set amplitude sample), and also when the determination value is [-1], outputs the sample value Yn.

4 illustrates details of the level cutter 30-1 , the data buffer 32-1 , the pointer 33-1 and the error detection circuit 34-1 , It should be noted that the level cutter 30-2 , the data buffer 32-2 , the pointer 33-2 and the error detection circuit 34-2 also have the same configurations.

As in 4 illustrates, the level cutter contains 30-1 a comparator 300 for comparing the sample Yn with the upper determination slice level and a comparator 301 for comparing the sample Yn with the lower determination cut level. The level cutter 30-1 also includes an EODER circuit 302 for taking the exclusive OR of the outputs of the two comparators 300 . 301 ,

The comparator 300 [1] outputs when the sample Yn is the upper determination cut level or above. The comparator 301 [1] outputs when the sample value Yn is the lower determination cut level or less. Accordingly, there is the EODER circuit 302 [1] when the sample Yn is the upper determination slice level or above and the lower determination slice level or less. The EODER circuit 302 However, it outputs [0] when the sample Yn is between the upper determination cut level and the lower determination cut level.

The data buffer 32-1 contains a receive register 320 , 5-stage buffer registers 321 to 325 and four pieces of AND gates 326 to 329 , The reception register 320 holds the output of the EODER circuit 302 , The 5-stage buffer registers 321 to 325 restrict a sequence of the determination values [0] to 5, and are therefore constructed in five stages.

The AND gates 326 to 329 take the AND of a data clear signal DTCLR with the pointer signals CNTFF20D to CNTFF50D. Then, the data clear signal ADTCLR becomes an erase terminal of the register 321 entered. Outputs of the corresponding AND gates 326 to 329 are entered to the ports of the other registers 322 to 325 to delete.

The pointer 33-1 is a 5-bit shift register. The pointer 33-1 Sequentially outputs pointer signals CNTFF20D to CNTFF50D in accordance with clock clocks. Then the pointer will 33-1 reset by a counter reset signal CNTRST.

The error detection circuit 34-1 has an AND gate 340 , a register 341 , a pair of EODER circuits 342 . 343 and an OR circuit 344 , The AND gate 340 sets the clock when an output of the EODER circuit 302 [1], whereby an error detection operation is performed. The registry 341 holds an output of the comparator 300 ,

The EODER circuit 342 takes the exclusive-OR of the output of the register 341 with the output of the comparator 300 on. The EODER circuit 343 takes the exclusive OR of an inverted Q output of the register 341 with the output of the comparator 301 on. The OR circuit 344 takes an OR with respect to the two EODER circuits 341 . 342 and outputs of the data clear signal DTCLR.

If X (nj), defined as the output of the EODER circuit 302 , is not [0], accordingly determine the EODER circuits 342 . 343 Whether the determination value X (nj) coincides with a determination value X (n) or not. When the determination value X (nj) coincides with the determination value X (n), the OR circuit outputs 344 the data clear signal DTCLR off. With this processing, the in the buffer registers 321 to 325 However, the contents indicated by the pointer signals are set to [0], which corrects the error.

Therefore, in the circuit fluctuates in 3 , as in 5 Fig. 11 illustrates the slice level in accordance with the determination value, and the amplitude (distance between the slice levels) A is variably controlled by each head and each cylinder position.

Further illustrated 6 a maximum likelihood decoding flow to obtain a maximum likelihood decoding sequence when the sample Yn is input. As in 6 shown, the determination section gel by the dashed line in the 6 changed specified processing. If X (nj), defined as the output of the EOR circuit 302 , not [0], then determine the EODER circuits 342 . 343 Whether the determination value X (nj) coincides with the determination value X (n) or not. When the determination value X (nj) coincides with the determination value X (n), the OR circuit outputs 344 the data clear signal DTCLR off. With this processing, the in the buffer registers 321 to 325 However, the contents indicated by the pointer signals are set to [0], which corrects the error.

It should be noted that with reference to 6 to limit the circuit scale of the decoder, as in 4 1, a modulation / demodulation code is used to limit the number of consecutive 0 in the binary signal string to be recorded.

With reference to 4 and 6 the sequence [0] is restricted to [5]. A condition thereof is reflected in j ≦ 5. With renewed reference to 6 Yn takes a ternary value [0, +2, -2]. In fact, however, as in 4 explains the binary data replaced by [0, 1]. This corresponds to dn in 6 ,

7A and 7B Fig. 10 are flowcharts of the slice level setting processing.

(S1) The control circuit (hereinafter referred to as a processor) 19 drives an unillustrated actuator and searches the head for a target cylinder.

(S2) The processor 19 causes the amplitude setting register 312 of the maximum likelihood decoder 16 to set the distance (amplitude) A of the cutting level to the maximum value. Next, the processor writes 19 the recording data on this cylinder with the head given above. Further, the processor selects 19 a head 0 off.

(S3) The processor 19 reads the recording data using the selected head. This read data field is provided via an in 1 transmitted route, and in the ECC circuit 18 error-checked. The processor 19 examines whether the data error in a specified number of bits from a determination output of the ECC circuit 18 occurs or not.

(S4) When it is determined that the data error occurs in the specified number of bits, the processor reduces 19 the distance A of the cutting level by ΔV. Then this will be in the register 312 is written, and the processing returns to step S3.

(S5) When it is determined that no data error is generated in the specified number of bits, the processor stores 19 the distance A of this cutting level as the upper limit. Next, the processor causes 19 the amplitude setting register 312 of the maximum likelihood decoder 16 to set the distance (amplitude) A of the cutting level to the minimum value.

(S6) The processor 19 reads the recording data using the selected head. This data field is over the in 1 transmitted route, and in the ECC circuit 18 error-checked. The processor 19 examines whether the data error in a specified number of bits from the determination output of the ECC circuit 18 occurs or not.

(S7) When it is determined that the data error occurs in the specified number of bits, the processor increases 19 the distance A of the cutting level by ΔV. Then this will be in the register 312 is written, and the processing returns to step S6.

(S8) When it is determined that no data error is generated in the specified number of bits, the processor stores 19 the distance A of this cutting level as the lower limit. Next comes the processor 19 a calculation (upper limit + lower limit) / 2 by. Then the processor causes 19 the memory 20 (please refer 3 ) to store the result of this calculation as the distance A of the cutting level of the current head and current cylinder.

(S9) Next, the processor checks 19 whether a designated head is a maximum (MAX) head or not. If the designated head is not the maximum head, a designated head address is incremented by 1, and the processing returns to step S3. In contrast, if the designated head is the maximum head, the processor examines 19 whether the settings of all setting cylinders are finished or not. The setting cylinder is set at an interval of 100 cylinders, for example. If it is determined that the settings of all the setting cylinders are not completed, the processor causes 19 a search to the next cylinder, and the processing returns to step S2. On the other hand, if it is determined that the settings of all the setting cylinders have been completed, the processor stops 19 the settings.

In this way, as in 3 illustrates, stores the memory 20 the distance (amplitude) of the optimum cutting level in the cylinder positions where all the heads are set. This operation is performed at the time of delivery from the factory. Then the processor receives 19 at a normal access time, a selected head address and a cylinder address, and reads the distance of the Cylinder, which corresponds to the selected head address and is set for this cylinder address, from the memory 20 , The distance thus read is in the amplitude setting register 312 of the maximum likelihood decoder 16 set.

Therefore Is it possible, set the distance with a maximum tolerance that matches the characteristics of a Waveform-equalizing circuit and the head corresponds. This can be a maximum likelihood decoding be performed at the optimum cutting level. Further differentiates the characteristic is dependent from the head, and therefore, the setting will be at the optimal cut level per Head performed. A variation of the recording density, from the cylinder position dependent also practices Influence on a regenerative signal, and therefore the maximum likelihood decoding at the optimum cutting level in accordance with the cylinder position carried out.

8th Fig. 16 is a block diagram illustrating a setting circuit. 9 Fig. 13 is a diagram for assistance in explaining the memory.

In the magnetic recording / regeneration circuit, the signal-to-noise ratio of the signal is degraded due to various factors, and there is a high probability that a regenerative signal error will occur. The factors causing this error may be an offset voltage of the A / D converter circuit for sampling, forward-backward asymmetry of the regenerative signal due to a bias magnetic field deviation of the MR head 10 , an equalization error due to a deviation in the setting of the electric filter 13 , an equalization error caused by an adjustment variation of the cosine equalizer 15 is caused to be a dispersion in the characteristic of the reproduction head and the variation of the recording density depending on the cylinder position. According to this embodiment, these characteristics are to be set.

With reference to 8th are the same elements as the ones in 1 explained with the same reference numerals. The processor 19 writes a bias current value of the MR head 10 in a write register 40 , A D / A converter 41 converts it to the write register 40 written Vorstromwert to an analog variable, and this leads a Vorstromtreibschaltung the head IC circuit 11 to.

The processor 19 writes a frequency characteristic value (cutoff frequency, etc.) of the electric filter 13 in a write register 42 , A D / A converter 43 converts the frequency characteristic value of the electric filter that enters the write register 42 is written to an analog variable, and controls the frequency characteristic of the electric filter 13 ,

The processor 19 writes a displacement value of the A / D converter circuit 14 in a write register 44 , A D / A converter 45 converts the offset value of the A / D converter 14 which is in the write register 44 is written to an analog size and outputs this analog magnitude to an adder amplifier 140 off, in front of the A / D converter 141 is provided. It should be noted that the adder amplifier 140 a displacement amount of the D / A converter 45 from an output of the electric filter 13 subtracted, and the result of it in the A / D converter 141 enters.

The processor 19 writes an equalization coefficient of the cosine equalizer 15 in a write register 46 , and this coefficient is applied to a coefficient set register of the cosine equalizer 15 output.

In the 1 shown scan detection circuit 21 contains a level determination unit 210 for determining the sample (equalization output) Yn at a ternary level, three write registers 211 to 213 and three reading registers 214 to 216 ,

The level determination unit 210 compares a level of the sample Yn with the upper and lower determination levels, and therefore performs a classification into the determination values Xn [+1], [0], [-1]. If the determination value is Xn [0], the sample Yn becomes the write register 212 written. If the determination value is Xn [-1], the sample Yn becomes the write register 213 written.

Compliant to the display of the processor 19 keeps the reading register 214 a content of the write register 211 , and informs the processor 19 about that. Compliant to the display of the processor 19 keeps the reading register 215 a content of the write register 212 , and informs the processor 19 about that. Compliant to the display of the processor 19 keeps the reading register 216 a content of the write register 213 , and informs the processor 19 about that.

The memory 20 , as in 9 4 illustrates stored set current values (bias values) in the adjustment cylinder positions 0 to m of the respective heads 0 to n, a filter constant value (frequency characteristic value) and a filter (equalization) coefficient.

In normal access, the processor receives 19 the selected head address and the cylinder address, and reads the drive current corresponding to the cylinder corresponding to the selected head address and for that cylinder address is set, the filter constant value and the filter coefficients from the memory 20 , These values are stored in the corresponding write registers 40 . 42 . 46 set. With this processing, a regenerative signal is obtained in which the up-down asymmetry due to the characteristic of the MR head 10 is compensated. Further, the deviation in the setting of the electric filter 13 be compensated. In addition, the setting deviation of the cosine equalizer can also 15 be compensated.

10A and 10B FIG. 10 are flowcharts for adjusting the offset voltage of the A / D converter.

at the adjustment of the offset voltage of the A / D converter becomes the offset voltage of the A / D converter itself without performing the read operation.

(S11) The processor 19 initializes five parameters A, B, C, D, N to [0]. Next, the processor continues 19 a default value as an initial operation value of a correction D / A converter 45 in a write register 44 , Furthermore, the processor stops 19 the read operation, reducing the input of the A / D converter 14 in the adder amplifier 140 is stopped.

(S12) In this state, the processor reads 19 the sample Yn, if Xn = 0, a predetermined number of times from the read register 215 , Then the processor calculates 19 an average value A of the samples Yn obtained a predetermined number of times.

(S13) The processor 19 calculates an error C from an absolute value (B - A). Here, B is the ideal sample if Xn = 0. In this example, the ideal sample is set to [0].

(S14) Next, the processor checks 19 Whether a number of times parameter N [0] is set or not.

(S15) When the parameter N for the first processing is [0], the processor updates 19 a reading D of the last time on error C. Next, the processor stores 19 the parameter N and an operation amount of the correction converter in a working area of the memory 20 while making them match each other. Furthermore, the processor adds 19 Δp to the operation amount of the correction D / A converter. This value becomes the operation size of the correction D / A converter 45 in the write register 44 written. In addition, the processor updates 19 the parameter N to (N + 1). Then, the processing returns to step S12.

(S16) If the parameter N is not [0], the processor compares 19 the measured value D of the last time with the measured value C of this time. If D> C, the measurement value of the last time is not the minimum value, and therefore the processing returns to step S15. On the other hand, if D> C is not detected, the last time reading is the minimum value. Because of this, the memory stops 20 the operation amount, as a result of adjustment, of the correction D / A converter in the case of (N-1) of the last time.

Therefore, such an operation amount is measured that the offset voltage of the A / D converter 141 is minimized, and this measurand is in memory 20 held. When operated, this optimal operation size is read out, and the result of adding this magnitude to the default value is in the register 44 set. The offset voltage of the A / D converter 141 this can be minimized.

11A and 11B FIG. 10 are flowcharts for adjusting the characteristics of the MR head. FIG.

(S21) The processor 19 drives the actuator, not shown, and thus performs the search of the head to a target cylinder.

(S22) The processor 19 initializes the five parameters A, B, C, D, N to [0]. Next, the processor writes 19 the recording data on this cylinder using the head. Further, the processor selects 19 head 0 off.

(S23) The processor 19 sets the setting value of the correction D / A converter 14 to the default value. That is, the processor 19 writes the default value in the write register 40 , Next, the processor reads 19 the recording data through the selected head.

(S24) In this state, the processor reads 19 the sample Yn, if Xn = 0, a predetermined number of times from the read register 215 , Then the processor calculates 19 the average A of samples Yn obtained a predetermined number of times. Furthermore, the processor calculates 19 the error C from an absolute value (B - A). Here, B is the ideal sample if Xn = 0. In this example, the ideal sample is set to [0].

(S25) Next, the processor checks 19 whether the parameter is N [0] or not.

(S26) If the parameter N for the first processing is [0], the processor updates 19 the measured value D of the last time on the measured value C of this time. Next, the processor saves 19 the parameter N and the operation size of the cor in a working area of the memory 20 while making them match each other. Furthermore, the processor adds 19 Δp to the operation amount of the correction D / A converter. This value becomes the operation size of the correction D / A converter 45 in the write register 40 written. In addition, the processor updates 19 the parameter N to (N + 1). Then, the processing returns to step S24.

(S27) If the parameter N is not [0], the processor compares 19 the measured value D of the last time with the measured value C of this time. If D> C, the measurement value of the last time is not the minimum value, and therefore the processing returns to step S26. On the other hand, if D ≦ C, the last time measurement is the minimum value. Therefore, the in 9 shown memory 20 the operation amount as a result of setting the relevant cylinder position of the relevant head of the correction D / A converter in the case of (N-1) of the last time.

(S28) Next, the processor checks 19 whether the designated head is the maximum (MAX) head or not. If the designated head is not the maximum head, the designated head address is incremented by 1, and the processing returns to step S23.

(S29) On the other hand, if the designated head is the maximum head, the processor examines 19 whether the settings of all setting cylinders are finished or not. The setting cylinder is set, for example, in the interval of 100 cylinders. If it is determined that the settings of all the setting cylinders are not completed, the processor causes 19 a search to the next cylinder, and the processing returns to step S22. In contrast, if it is determined that the setting of all the setting cylinders has been completed, the processor terminates 19 the settings.

In this way, as in 9 illustrates, stores the memory 20 the optimum bias value in the cylinder positions where all the heads are set. This operation is performed at the time of delivery from the factory. Then the processor receives 19 at a normal access time, the selected header address and the cylinder address, and reads the bias current value corresponding to the selected header address and set for that cylinder address from the memory 20 , This bias current value is in the write register 40 set.

In this way, the bias current of the MR head 10 is set to minimize the level of the sample Yn when the determination value Xn = 0. Therefore, it is possible the forward-backward or up-down asymmetry of the read waveform due to the characteristic of the MR head 10 to minimize. Further, the variation of the recording density, which depends on the cylinder position, also exerts an influence on the regenerative signal, and therefore the setting to the optimum bias current value is performed in accordance with the cylinder position.

12A and 12B FIG. 10 are flowcharts for adjusting the characteristic of the electric filter. FIG.

(S31) The processor 19 drives the unillustrated actuator, thus performing the seek of the head to a target cylinder.

(S32) The processor 19 initializes the two parameters A, B to [0]. Next, the processor writes 19 the recording data on this cylinder using all the heads. Further, the processor selects 19 head 0 off.

(S33) The processor 19 sets the setting value of the correction D / A converter 43 to the default value. That is, the processor 19 writes the default value in the write register 42 , Next, the processor reads 19 the recording data through the selected head.

(S34) In this state, the processor reads 19 the sample Yn, if Xn = X, a predetermined number of times from the read registers 214 to 216 , This value X is one of [+1], [0], [-1]. Then the processor calculates 19 (Maximum value minimum value) of the samples Yn obtained a predetermined number of times. This is set as parameter A. A standard deviation is determined instead of this calculation of (maximum value minimum value), and the result thereof can be set as parameter A.

(S35) Next, the processor checks 19 whether the parameter is N [0] or not.

(S36) If the parameter N for the first processing is [0], the processor updates 19 the measured value B of the last time to the measured value A of this time. Next, the processor saves 19 the parameter N and the operation size of the correction converter in a working area of the memory 20 while making them match each other. Furthermore, the processor adds 19 Δp to the operation amount of the correction D / A converter. This value becomes the operation size of the correction D / A converter 41 in the write register 42 written. In addition, the processor updates 19 the parameter N to (N + 1). Then, the processing returns to step S34.

(S37) If the parameter N is not [0], the processor compares 19 the measured value B of the last times with the measured value A of this time. If B> A, the reading of the last time is not the minimum value, and therefore the processing returns to step S36. If, on the other hand, B ≤ A, the last maize reading is the minimum value. Therefore, the in 9 shown memory 20 the operation amount as a result of setting the relevant cylinder position of the relevant head of the correction D / A converter in the case of (N-1) of the last time.

(S38) Next, the processor checks 19 whether the designated head is the maximum (MAX) head or not. If the designated head is not the maximum head, the designated head address is incremented by 1, and the processing proceeds to step S33 in FIG 12A back.

(S39) On the other hand, if the designated head is the maximum head, the processor examines 19 whether the settings of all setting cylinders are finished or not. The setting cylinder is set, for example, in the interval of 100 cylinders. If it is determined that the settings of all the setting cylinders are not completed, the processor causes 19 a search to the next cylinder, and the processing returns to step S32. In contrast, if it is determined that the settings of all the setting cylinders have been completed, the processor terminates 19 the settings.

In this way, as in 9 illustrates, stores the memory 20 the optimum frequency characteristic value in the cylinder positions where all the heads are set. This operation is performed at the time of delivery from the factory. Then the processor receives 19 at normal access time, the selected head address and the cylinder address, and reads out the frequency characteristic value corresponding to the selected head address and set for that cylinder address from the memory 20 , This frequency characteristic value is in the write register 42 set.

In this way, the frequency characteristic value of the electric filter becomes 13 is set to minimize the standard deviation or a difference between the maximum value and the minimum value of the samples Yn when the determination value Xn = X. Therefore, it is possible to minimize the setting error of the electric filter. Further, the characteristic per head differs, and therefore the frequency characteristic value per head is set. In addition, since the regenerative signal is influenced by the variation of the recording density depending on the cylinder position, the frequency characteristic value is set to the optimum value in accordance with the cylinder position.

13A and 13B Fig. 10 are flowcharts for adjusting the characteristics of the cosine equalizer.

(S41) The processor 19 drives the unillustrated actuator, thus performing the seek of the head to a target cylinder.

(S42) The processor 19 initializes the two parameters A, B to [0]. Next, the processor writes 19 the recording data on this cylinder using all the heads. Further, the processor selects 19 head 0 off.

(S43) The processor 19 sets the set value of the coefficient setting register of the cosine equalizer to the default value. That is, the processor 19 writes the default value in the write register 46 , Next, the processor reads 19 the recording data through the selected head.

(S44) In this state, the processor reads 19 the sample Yn, if Xn = 0, a predetermined number of times from one of the read registers 214 . 215 . 216 , This value X is one of [+1], [0], [-1]. Then the processor calculates 19 (Maximum value minimum value) of the samples Yn obtained a predetermined number of times. This is set as parameter A. A standard deviation is determined instead of this calculation of (maximum value minimum value), and the result thereof can be set as parameter A.

(S45) Next, the processor checks 19 whether the parameter is N [0] or not.

(S46) When the parameter N for the first processing is [0], the processor updates 19 the measured value B of the last time to the measured value A of this time. Next, the processor saves 19 the parameter N and the operation size of the correction converter in a working area of the memory 20 while making them match each other. Furthermore, the processor adds 19 Δp to the operation amount of the correction D / A converter. This value becomes the operation size of the coefficient setting register in the write register 46 written. In addition, the processor updates 19 the parameter N to (N + 1). Then, the processing returns to step S44.

(S47) If the parameter N is not [0], the processor compares 19 the measured value B of the last time with the measured value A of this time. If B> A, the measurement value of the last time is not the minimum value, and therefore the processing returns to step S46. On the other hand, if B> A is not detected, the last time measurement is the minimum value. Therefore, the in 9 shown memory 20 the operation amount, as a result of setting the relevant cylinder position of the relevant head, of the correction D / A converter in case of (N-1) of the last one Times.

(S48) Next, the processor checks 19 whether the designated head is the maximum (MAX) head or not. If the designated head is not the maximum head, the designated head address is incremented by 1, and the processing proceeds to step S43 in FIG 13A back.

(S49) On the other hand, if the designated head is the maximum head, the processor examines 19 whether the settings of all setting cylinders are finished or not. The setting cylinder is set, for example, in the interval of 100 cylinders. If it is determined that the settings of all the setting cylinders are not completed, the processor causes 19 a search to the next cylinder, and the processing returns to step S42. In contrast, if it is determined that the settings of all the setting cylinders have been completed, the processor terminates 19 the settings.

In this way, as in 9 illustrates, stores the memory 20 the optimal filter coefficient in the cylinder positions where all the heads are set. This operation is performed at the time of delivery from the factory. Then the processor receives 19 at normal access time, the selected head address and the cylinder address, and reads the filter coefficient corresponding to the selected head address and set for that cylinder address from the memory 20 , This filter coefficient is in the write register 46 set.

In this way, the frequency characteristic value of the cosine equalizer becomes 15 is set to minimize the standard deviation or the difference between the maximum value and the minimum value of the samples Yn when the determination value Xn = X. Therefore, it is possible to make the adjustment error of the cosine equalizer 15 to minimize. Further, the characteristic per head differs, and therefore the frequency characteristic value per head is set. In addition, since the regenerative signal is affected by the variation of the recording density depending on the cylinder position, the filter coefficient is set to the optimum value in accordance with the cylinder position.

As discussed above, the control circuit controls 19 the distance between the slice levels of the maximum likelihood decoder 16 variable, and therefore, the optimal ternary determination corresponding to the equalization error quantity can be performed. Further, the maximum decoding operation may also be performed according to the characteristics of the equalizer circuit and the head.

When next an explanation is given a modified example of the ternary determining unit. A the PRML system inherent problem is the enlargement of the scale the circuit. For this reason, it is desirable that the decoder is constructed easily and also under a condition where the Is not good, has a high decoding capability.

positive and negative maxima occur alternately in a scan chain even or odd number of regenerative signals of the recording device based on a partial response class IV system. Under consideration the fact stated above that the positive and negative Maxima occur alternately therein, a method of performing the Ternärbestimmung proposed. Becomes more specific after the detection of the positive Signal an upper slice level S0 (n + 1) to a detected Slice level Y (n) is set, and a lower slice level S1 (n + 1) will be on the next Cut level set at a fixed distance A from upper cutting level is maintained.

in the In contrast, after the detection of the negative signal, the lower slice level S1 (n + 1) to a detected slice level Y (n) is set, and the upper slice level S0 (n + 1) becomes the next slice level set at a fixed distance from the lower slice level is held. If [0] is detected, both the upper and lower cutting level unchanged.

The is called, the two slice levels S0 (n) and S1 (n) become detections for [+1] and [-1] detections generated. A difference between the two cutting levels S0 (n) and S1 (n) is set to a suitable value A (S0 (n) - S1 (n) = A> 0).

It it is assumed that the Sample Y (n), and if Y (n) ≥ S0 (n), becomes a ternary regenerative signal A (n) is set, such as [+1], S0 (n + 1) = Y (n), and S1 (n + 1) = Y (n) - A. If S1 (n) <Y (n) <S0 (n), becomes ternary Regenerative signal A (n) also set, such as [0], S0 (n + 1) = S0 (n), and S1 (n + 1) = S1 (n). If Y (n) ≤ S1 (n), also becomes the ternary Regenerative signal A (n) is set, such as [-1], S0 (n + 1) = Y (n) + A, and S1 (n + 1) = Y (n).

If such a ternary determination is carried out is the negative or positive signal after detection of the positive or negative signal easily detected, with the result that due voltage drop [1] is not mistaken for [0].

When each such ternary determination circuit is constructed in a discrete manner, the configuration becomes complicated. Furthermore, a Bestim mung speed reduced, and the maximum likelihood decoding speed is in turn reduced. In addition, it is desirable that the difference between the two cutting levels be changed according to the characteristics of each head and each cylinder. However, adding such a function involves a difficulty in configuration.

Under such circumstances is the maximum likelihood decoder in this modified example to carry out the ternary determination provided with a simpler construction.

14 Fig. 13 is a diagram illustrating a construction of the maximum likelihood decoder.

As in 14 shows a ternary determination circuit 51 Ternary determinations of the samples Y (n) passing through a partial equalizer 15 be rectified (see 1 ), and outputs ternary determination results A (n). A data buffer 52 holds a predetermined number of ternary determination results A (n), and outputs a demodulation data field X (n). An error detection correction circuit 53 detects an error from the ternary determination results S (n), and thus corrects the corresponding data in the data buffer 52 , It should be noted that the reference number 54 an address mark detection circuit.

15A and 15B are representations showing the ternary determination circuit in 14 illustrate. 16 FIG. 4 is an explanatory diagram showing a conversion table of the memory in FIG 15A shows. 17 FIG. 13 is a diagram for assistance in explaining a conversion operation in FIG 15A ,

As in 15A shows the ternary determination circuit 51 an input buffer 100 , a store 110 and an output buffer 120 , The input buffer 100 holds high quality 6 bits of 8-bit sample Y (n) to be input.

The memory 110 is constructed from a RAM. In the store 110 become the sample Y (n) of the input buffer 100 and input the current upper 6-bit slice level S0 (n). Then there is the memory 110 2-bit ternary determination results DT0, DT1, as in 15B and the next upper 6-bit slice level S0 (n + 1). The output buffer 120 holds the next upper 6-bit slice level S0 (n + 1) and feeds it to a slice level input of the memory 110 back.

As in 16 that is in memory 110 stored conversion table, a correspondence table of the ternary determination results DT0, DT1 and the next upper slice level S0 (n + 1) corresponding to the sample Y (n) and the upper slice level S0 (n). This correspondence relationship is consistent with the relationship between the above-stated ternary determinations.

More specifically, when Y (n) ≥ S0 (n), the ternary regenerative signal A (n) (DT0, DT1) [+1] (10), and therefore S0 (n + 1) = Y (n). Further, if S1 (n) <Y (n) <S0 (n), the ternary regenerative signal A (n) (DT0, DT1) is [0] (00), and therefore S0 (n + 1) = S0 (n) , In addition, when Y (n) ≦ S1 (n) = S0 (n) -A, the ternary regenerative signal A (n) (DT0, DT1) is [-1] (01), and therefore S0 (n + 1) = Y (n) + A. For example, as in 16 when Y (n) = 00 (HEX), and S0 (n) = 00 (HEX), Y (n) ≥ S0 (n), and therefore, the ternary regenerative signal DT0, DT1 includes +1 (10), S0 (n + 1) = Y (n) = 00 (HEX). Similarly, if Y (n) = 3F (HEX), and S0 (n) = 00 (HEX), Y (n) ≥ S0 (n), and therefore the ternary regenerative signal DT0, DT1 contains +1 (10), S0 (n + 1) = Y (n) = 3F (HEX).

Accordingly, as in 17 is shown when Y (n) = 10 (HEX), and S0 (n) = 18 (HEX), S1 (n) <Y (n) <S0 (n), and therefore, the ternary regenerative signal DT0, DT1 becomes 0 (00), S0 (n + 1) = S0 (n) = 18 (HEX) is output.

Such a conversion table is in memory 110 stored, whereby the configuration of the ternary determination circuit is simplified. Furthermore, a universal memory can be used, and therefore the circuit can be constructed at a low cost. In addition, the ternary determination result can be easily obtained by accessing the memory 110 can be obtained, whereby the ternary determination can be carried out at high speed. In addition, the difference between the two slice levels can be made simply by varying the contents of the memory 110 are changed, and thereby the Ternärbestimmungscharakteristik is changeable.

These Conversion table is created per capita or cylinder, with the Result that the Conversion table used in correspondence to each head or cylinder can be.

When next For example, a path memory and an error correction circuit will be explained.

18 is a representation showing a configuration of the data buffer in 14 illustrated. 19 is an illustration showing a configuration of the error correction circuit in FIG 14 shows. 20 Fig. 12 is a diagram illustrating a configuration of the address mark detection circuit.

As in 18 is the data buffer 52 from a ternary data input circuit 55 a path memory circuit 56 and an address mark detection path storage circuit 57 constructed. The ternary data input circuit 55 contains registers 500 . 501 for holding the ternary determination values DT0, DT1 and an EODER circuit, respectively 502 for receiving the exclusive-OR of the outputs DDT0, DDT1 of the two registers 500 . 501 ,

Accordingly, there is the EODER circuit 502 [1] when the ternary determination values DT0, DT1 are [+1] (10) and [-1] (01). Then there is the EODER circuit 502 [0] if both ternary determination values DT0, DT1 are [0].

The path memory circuit 56 includes 5-stage serial buffer registers 510 . 512 . 514 . 516 . 518 as well as AND gate 511 . 513 . 515 . 517 . 519 , The buffer register 510 keeps an output of the EODER circuit 502 and give this to the AND gate 511 out. The AND gate 511 takes the AND of a data clear signal * DTCLR with an output of the buffer register 510 on, and outputs path data P-DATA.

The buffer register 512 holds an output of the AND gate 511 and give this to the AND gate 513 out. The AND gate 513 takes the AND of a clear signal * CLR1 with an output of the buffer register 512 on, and outputs path data P-DATA1.

The buffer register 514 holds an output of the AND gate 513 , and gives this to the AND gate 515 out. The AND gate 515 takes the AND of a clear signal * CLR2 with an output of the buffer register 514 on, and outputs path data P-DATA2.

The buffer register 516 holds an output of the AND gate 515 , and gives this to the AND gate 517 out. The AND gate 517 takes the AND of a clear signal * CLR3 with an output of the buffer register 516 on, and outputs path data P-DATA3.

The buffer register 518 holds an output of the AND gate 517 , and gives this to the AND gate 519 out. The AND gate 519 takes the AND of a clear signal * CLR4 with an output of the buffer register 518 on, and outputs path data P-DATA4. This path data field P-DATA4 generates demodulation data.

The buffer registers 510 to 518 the path memory circuit 56 Since the number of consecutive data [0] is restricted to 5, they are constructed in five stages.

The address mark detection path storage circuit 57 is for detecting an address tag with a buffer register 520 and an AND gate 521 Mistake. The buffer register 520 holds an output of the AND gate 519 , and gives this to the buffer register 521 out. The AND gate 521 takes the AND of the clear signal * CLR5 with an output of the buffer register 520 on, and outputs path data P-DATA5. The error detection correction circuit 53 has an error detection circuit 60 , a pointer circuit 61 and an error correction signal generation circuit 62 , The error detection circuit 60 contains an AND gate 600 , a time delay delay buffer circuit 601 , a register 602 , a pair of EODER circuits 603 and 604 , an OR circuit 605 and an inverter circuit 606 ,

The AND gate 600 sets the clock when the output of the EODER circuit 502 [1], whereby the error detection operation is performed. The registry 602 where the output of the AND gate 600 serves as a clock, holds the output of the buffer circuit 601 ,

The EODER circuit 603 takes the exclusive OR of an output Q of the register 602 with the output of the buffer circuit 601 on. The EODER circuit 604 takes the exclusive-OR of the inverted output Q of the register 602 with an output DDT1 of the input register 601 on.

The OR circuit 605 takes the OR with respect to the two EODER circuits 603 . 604 on, and outputs the data clear signal * DTCLR. The inverter circuit 606 inverts the data clear signal * DTCLR. The operation of this error detection circuit will be described with reference to FIG 21 described.

As in 19 illustrates the pointer circuit 61 a register 610 for holding the data DATA0, a NAND gate 611 and a counter, which consists of 5-stage flip-flops 612 to 616 is constructed. The registry 610 outputs the data DATA0 in synchronism with the clock * CLK. The NAND gate 611 outputs data * REGCLR with a width of the CLK clock.

The flip-flop 612 is turned ON when a single data value [0] is input. The flip-flop 612 is cleared when the data * REGCLR is turned ON after entering [1]. The flip-flop 613 is turned ON when two data values [0] are consecutively input, but cleared when the data * REGCLR is turned ON after inputting [1].

The flip-flop 614 is switched ON if three data values [0] are entered consecutively, and is cleared when the data * REGCLR is turned ON after entering [1]. The flip-flop 615 is turned ON when four data values [0] are consecutively input, but cleared when the data * REGCLR is turned ON after inputting [1].

The flip-flop 616 is a zero counter for detecting the address mark. The flip-flop 616 is turned ON when five data values [0] are consecutively input, but cleared when the data * REGCLR is turned ON after inputting [1].

The error correction signal generation circuit 62 takes the AND of the corresponding data clear signals DTCLR with the count signals CNTFF2 to CNTFF6 of the flip-flops 612 to 626 on. The error correction signal generation circuit 62 has five AND gates 620 to 624 for issuing clear signals * CLR1 to * CLR5.

As in 20 shown contains the address mark detection circuit 54 an AND gate 640 , a 4-bit counter 641 and an AND gate 642 , The AND gate 640 takes the AND of the data values of the path data P-DATA0 to P-DATA 5 , and detects a sequence of six data values [0]. The counter 641 is cleared by an address mark search signal AM-SEARCH, and counts outputs of the AND gate 640 , If a value of the counter 641 [2] gives the AND gate 642 an address mark detection signal AM-FOUND.

21 Fig. 16 is a timing chart showing the error detection operation. 22 Fig. 10 is a timing chart showing the error correction operation. 23 Fig. 13 is a diagram for assistance in explaining the address mark.

First, the error detection operation will be described with reference to FIG 21 explained. The AND gate 600 picks up the AND of the data DATA0 with the clock * CLK, whereby a signal A is obtained. The flip-flop 602 , where signal A is the clock, holds the data DDT0, and thereupon the output Q provides a signal B. An inverted output Q thereof becomes a signal C.

The EODER circuit 603 takes the exclusive-OR of the signal B with the data DDT0, whereby a signal D is obtained. Further, the EODER circuit picks up 604 the exclusive-OR of the signal C with the data DDT1, whereby a signal E is obtained. Accordingly, the data clear signal * DTCLR of the OR circuit 605 as shown in the figure. That is, when two data items having the same digit are consecutively input, the data clear signal * DTCLR for correcting the previous data is outputted to [0], and the AND gate 511 corrects the data DATA1.

As in 21 As can be seen, the data to be corrected are underlined. When data items marked with the same numeral are consecutively input (eg, +1 and +1), the data erase signal * DTCLR is input to erase the underlined data. Then, the AND relating to DDATA0 is taken with a delay of one clock from the data DATA0, thereby obtaining the corrected data P-DATA0 (DATA1).

If the data remains unchanged, for example, [0] occurs between [+1] and [+1], the data can not be corrected. This corresponds to double underlined data [1] in 21 , Then, as in 18 veran illustrates the path memory circuit 56 further provided with a tuple of a register and an AND gate. In addition, the pointer circuit 61 and the error correction signal generating circuit 62 provided in 19 are shown.

As in 22 illustrates, the flip-flop 612 Turned ON when a single data value [0] is input is cleared, however, when the data * REGCLR is turned ON after the input of [1], thereby outputting a counter signal CNTFF2. The flip-flop 613 is turned ON when two data values [0] are consecutively input, but is cleared when the data * REGCLR is turned ON after the input of [1], thereby outputting a counter signal CNTFF3.

The flip-flop 614 is turned ON when three data values [0] are consecutively input, but is cleared when the data * REGCLR is turned ON after the input of [1], thereby outputting a counter signal CNTFF4. The flip-flop 615 is turned ON when four data values [0] are consecutively input, but is cleared when the data * REGCLR is turned ON after the input of [1], thereby outputting a counter signal CNTFF5.

The flip-flop 616 is turned ON when five data values [0] are consecutively input, but is cleared when the data * REGCLR is turned ON after the input of [1], thereby outputting a counter signal CNTFF6.

If there is a data value [0] between data of the same digit, the counter operates accordingly 612 and the AND gate 620 to generate a clear signal * CLR1, whereby the data from the AND gate 513 Getting corrected. If there are two data values [0] between the data with the same digit, the counter will work 613 and the AND gate 621 together to clear a signal * Generate CLR2, removing the data from the AND gate 515 Getting corrected.

If there are three data values [0] between the data with the same digit, the counter will work 614 and the AND gate 622 to generate a clear signal * CLR3, whereby the data from the AND gate 517 Getting corrected. If there are four data values [0] between the data with the same digit, the counter will work 615 and the AND gate 623 to generate a clear signal * CLR4, whereby the data from the AND gate 519 Getting corrected.

If there are five data values [0] between the data with the same digit, the counter will work 616 and the AND gate 624 together to generate a clear signal * CLR5, whereby the data from the AND gate 521 Getting corrected.

On in this way, the maximum likelihood decoding operation is performed.

Next, the operation of detecting the address mark will be explained with reference to FIG 23 discussed. A read / write clock of the magnetic disk, when no data is read, is synchronized with a clock which is synchronous with a rotation of the magnetic disk. For this reason, before reading the data, the read / write clock is not in synchronism with a read waveform of the magnetic disk, and therefore, the correct data can not be read. Then, before reading the data, synchronization of the operation is effected by setting the read / write clock in phase.

A phase synchronization thereof is obtained by reading a slit pattern of the single frequency written on the magnetic disk. In the magnetic disk apparatus, the gap pattern is first detected and read therefrom, thereby obtaining the phase synchronization. As in 23 1, data values [0] having a length which is not apparent in the codes for encoding are written in an area of the slit pattern. This area is called an address mark.

The Cleavage pattern is detected by finding this address mark becomes. Then, the gap pattern is read, whereby a phase-pulling operation of the Read / write clock is started. At a synchronization are to read the data.

As in 23 3, three patterns each having a sequence of six data values [0] appear in the address mark (AM). Accordingly, the address mark can be detected by finding two patterns each having the sequence of six data values [0].

As in 18 shown is the path memory 56 that can hold five consecutive data values [0] with a path memory 57 Mistake. Furthermore, the in 20 shown address mark detection circuit 54 intended. Thereby, it is possible to detect the address mark in which two patterns each having the sequence of six data values [0] are present.

In this way, the address tag can only be detected by adding the simple circuit by the path memory 56 of the data buffer 52 is used effectively. Therefore, the address mark can be detected with the simple circuit.

In In this modified example, the ternary determination circuit of FIG Memory is constructed, and therefore the configuration of the maximum likelihood decoder simplified. The ternary determination can also be done simply by accessing the memory, and therefore it is possible the ternary determination issue to get at the high speed. Furthermore, the optimal Ternärbestimmungscharakteristik, which corresponds to the head characteristic, can be easily changed.

When next AGC and PLL loops are explained. In a partial-response regeneration system An error signal in the AGC and PLL loops is output as a digital value specified. For this reason, a converter for converting such is Digital error signal into an analog control variable with a simple design required.

A automatic gain control circuit (AGC) circuit, the for the partial response system is used has a feedback loop based on the digital data in addition to the feedback loop based on the analog size. Further Also, a phase synchronization circuit has the PLL loop the basis of digital data. This digital loop becomes the digital error signal converted to the analogue control variable, and therefore, a charge pump type D / A converter is used.

In a control loop based on the AGC digital data becomes a Control voltage generated. For this purpose, a subtractor subtracts one Target value (digital amplitude value) of discrete waveform data (Digital output) obtained by a digital equalizer, whereby n-bit amplitude error signals to be obtained. These amplitude error signals are divided into n pieces of Charge pump circuits entered and so converted into current values.

Each of the n-pieces of charge pumps kon Inverts the signal into the current value, which corresponds to a weight of each of the n-bits. Then, the sum of the outputs of n pieces of the charge pump circuits is converted into a voltage by a low-pass filter, and an AGC control voltage output is generated.

Become similar in a phase lock loop circuit through the partial response system corresponding bit outputs of 7-bit digital phase error signals from a phase error detector in seven pieces entered the charge pump circuits, and thereby converted into current values, which correspond to the bit weights. Then the sum of the outputs of the seven charge pump circuits entered into the filter, and thereby in converted a control voltage, causing the voltage-controlled Oscillator is controlled.

Generally is in the automatic gain control circuit and the phase synchronization circuit at the loop gain Drawing process higher set as at the time of station operation, thereby increasing the target amplitude in shorter Time is reached. Further, at the time of the station operation, the circuit is designed to produce a sequence of fast amplitude fluctuations due to variations in the frequency of the data by preventing the loop gain is reduced, and slow amplitude fluctuations in the modulation, etc., to absorb.

So far is as an element of change this loop gain a single charge pump circuit bit by bit from the output data of the Error signal provided. Furthermore Such a method has been used that the current value of each full-bit charge pump by a drag operation / station operation switch signal in the drawing state to a larger value, however in the stationary state is switched to a smaller value.

The however, corresponding charge pump cycles are required for the input full bits, and accordingly arises the problem that the Circuit configuration becomes complicated. Because of this, it increases the price of the device.

Now the A / D converter is explained with a simple construction.

24 Figure 12 is a block diagram of a control loop of a PRML regeneration device.

With reference to 24 are the same elements as the ones in 1 marked with the same reference numbers. As in 24 shown amplifies the gain control type amplifier (GCA) 12 a read signal read from the magnetic disk by the magnetic head. This gain control amplifier 12 can make its voltage variable by a control voltage from the outside. The electric filter 13 is a filter for equalizing a waveform that corresponds to (1 + D). It is to be noted that D denotes a data field input before a scan, and (1 + D) means a sum of the data input at the current time and the data delayed by 1 sample period.

The n-bit A / D converter 14 converts the analog outputs into n-bit digital outputs. The digital equalizer 15 is constructed from a known cosine equalizer. The digital equalizer 15 auto-equalizes the signal corresponding to the partial response characteristic in the radial direction of the disk.

An automatic gain control circuit 2 has an analog AGC loop and a digital AGC loop. An amplitude detector 22 detects a difference between an analog output amplitude of the electric filter 13 and an analog target amplitude. A circuit 23 performs a switch from the analog AGC loop to the digital AGC loop. A low pass filter 24 converts an output current of the switching circuit 23 to a voltage, whereby a control voltage of the gain control amplifier 12 is produced.

A subtractor 25 subtracts a digital target value from discrete waveform data from the digital equalizer 15 and outputs a digital error value. A D / A converter 26 The n-bit charge pump type converts n-bit digital error values to analog current magnitudes and supplies these quantities to the circuit 23 out.

The operation of the automatic gain control circuit 2 will be explained. First is the circuit 23 with the amplitude detector 22 connected, whereby the analog AGC loop is formed. That is, the circuit circuit 23 gives to the low-pass filter 24 an analog error magnitude obtained by subtracting the analog target amplitude from the analog output of the electrical filter 13 of the amplitude detector 22 is obtained. Thereby, a control voltage is generated from the analog error quantity, and then to the gain control amplifier 12 returned, whereby the amplitude is controlled.

After controlling the amplitude in this analog AGC loop, the circuit circuit causes 23 switching to the digital AGC loop. That is, the circuit circuit 23 is with the D / A converter 26 connected to the type of a charge pump. Accordingly, the D / A converter converts 26 of the type of a charge pump a digital error value of the subtractor 25 in the analog current size, which value by subtracting the digital target value from the discrete waveform data received from the digital equalizer 15 are delivered, and this analog current magnitude is in the circuit 23 entered. This analogue size is provided by the low-pass filter 24 converted into a voltage, whereby the gain control amplifier 12 is controlled.

Next contains the phase synchronization circuit (PLL loop) 7 a ternary determination unit 70 for performing a ternary determination on a sampling output Y (n) of the digital equalizer 15 and outputting a ternary determination output X (n). The ternary determination unit 70 compares the sample Y (n) with two slice levels S1, S2, and makes a determination in the form of determination values X (n) of [+1], [0], [-1].

A phase detector 71 calculates a phase difference Δτ (n) from the sampling output Y (n) and the ternary determination output X (n). This phase detector for PRML class IV is described in an article entitled [FAST TIMING RECOVERY FOR PARTIAL-RESPONSE SIGNALING SYSTEMS] (1986 IEEE CH2655-9 / 89 / 0000-0573) by F. Dolivo, W. Scott and G. Ungerbook described.

More specifically, the phase difference Δτ (n) is defined by the following expression: Δτ (n) = Y (n-1) × X (n) -Y (n) × X (n-1), where Y (n) is the sampling voltage of the read signal after performing the partial equalization, and X (n) is the result of the ternary determination by the ternary determination unit 70 is.

A frequency comparator 72 determines a frequency of a servo signal read from a servo surface of the magnetic disk, and outputs a frequency error. A multiplexer circuit 73 gives a phase error of the phase detector when reading from the magnetic disk 71 but if it is not read by the magnetic disk, it gives a frequency error of the frequency comparator 72 out.

A D / A converter 74 a charge pump type converts a digital error signal of the multiplexer circuit 73 in an analog current size. A loop filter 75 is from the low pass filter 75 constructed. The loop filter 75 converts the analog current magnitude into a voltage, creating a voltage control oscillator 76 is controlled. The voltage control oscillator 76 generates a synchronous clock, called the sampling clock of the A / D converter 74 is used.

The operation of the phase synchronization circuit 7 is described. During non-read processing from the magnetic disk is the multiplexer circuit 73 with the frequency comparator 72 connected. Through this connection, the voltage control oscillator generates 76 one clock in synchronism with the frequency of the servo signal.

During the read processing from the magnetic disk is the multiplexer circuit 73 however, with the phase detector 71 connected. Through this connection, the voltage control oscillator generates 76 a clock derived from the phase error of the sampling output of the digital equalizer 15 is controlled.

25 FIG. 12 is a block diagram showing the charge pump type automatic charge control type D / A converter 2 in 24 illustrated. 26 Fig. 13 is a diagram for assistance in explaining the operation thereof.

As in 25 illustrates is the D / A converter 26 type of charge pump with four multiplexers 27-1 to 27-4 Mistake. In an output of the subtractor 25 For example, the most significant bit is labeled with an output port number [1], whereas the least significant bit is marked with an output port number [8]. Outputs with the output terminal numbers [1], [5] are put into the multiplexer 27-1 entered. Outputs with the output terminal numbers [2], [6] are put into the multiplexer 27-2 entered. Outputs with the output terminal numbers [3], [7] are put into the multiplexer 27-3 entered. Outputs with the output terminal numbers [4], [8] are put into the multiplexer 27-4 entered.

An initial pull / station operation switch signal goes into each multiplexer 27-1 to 27-4 entered. If the switch signal then indicates the initial pull, select the appropriate multiplexers 27-1 to 27-4 the outputs with the output terminal numbers [1], [2], [3], [4] are off. On the other hand, when the switching signal indicates the station operation, the multiplexers select 27-1 to 27-4 the outputs with the output terminal numbers [5], [6], [7], [8] are off.

Further, the D / A converter 26 of the type of charge pump with four charge pump circuits 26-1 to 26-4 provided with the multiplexers 27-1 to 27-4 are connected. The initial pull / station operation switch signal also goes into each of these charge pump circuits 26-1 to 26-4 entered. When the switching signal then indicates the initial pulling, the corresponding charge pumping circuits give 26-1 to 26-4 Output currents of 128 mA, 64 mA, 32 mA, 16 mA off. When switching signal indicates the station operation, the charge pump circuits give 26-1 to 26-4 furthermore output currents of 8 mA, 4 mA, 2 mA, 1 mA.

That is, in the initial drag operation, the multiplexers choose 27-1 to 27-4 higher-order 4 bits, however, select low-order 4 bits in the station operation. Furthermore, each charge pump circuit 26-1 to 26-4 however, in the station operation, a current corresponding to a weight of the low-order 4 bits outputs, in the initial pull operation, a current corresponding to a weight of the high-order 4 bits, which is 16 times that specified above.

The operation of it is with reference to 26 explained. When a sampling mode switching signal assumes a low level, the switching circuit becomes 23 with the amplitude detector 22 connected, whereby the analog AGC loop is formed. The circuit circle 23 gives to the low-pass filter 24 an analog error magnitude obtained by subtracting the analog target amplitude from the analog output of the electrical filter 13 of the amplitude detector 22 is obtained. A control voltage is thereby generated from the analog error quantity and then to the amplifier 12 fed back with variable gain, whereby the amplitude is controlled.

Next, the sampling mode switching signal assumes a high level, and a mode (sampling mode) based on the digital AGC loop is displayed. With this processing is the circuit circuit 23 with the D / A converter 26 connected to the type of a charge pump. Simultaneously with this, a pull mode is displayed in which the pull / station operation switching signal is [LOW].

The multiplexers 27-1 to 27-4 This selects the high-quality 4 bits of the 8-bit outputs of the subtractor 25 out. Each of the charge pump circuits 26-1 to 26-4 Also outputs the current corresponding to the weight of the high-quality 4 bits.

Accordingly, the D / A converter converts 26 of the charge pump type, the high quality 4 bits of the subtractor 8-bit digitial error values 25 to an analog current magnitude, which value is obtained by subtracting the digital target value from the discrete waveform data provided by the digital equalizer 15 will be obtained, and this analog current magnitude will be in the circuit 23 entered. This analogue size is provided by the low-pass filter 24 converted into a voltage, causing the gain-controlled amplifier 12 is controlled.

After the completion of the drag operation, the drag / station operation switch signal indicates the station operation of [HIGH]. With this processing, each multiplexer selects 27-1 to 27-4 the least significant 4 bits from the 8-bit outputs of the subtractor 25 out. Further, the charge pump circuits give 26-1 to 26-4 the current corresponding to the weights of the lower 4 bits.

This converts the D / A converter 26 of the charge pump type, the low order 4 bits of 8 bit digitial error values of the subtractor 25 in analog current sizes, and gives these variables in the circuit 23 one. This analogue size is provided by the low-pass filter 24 converted into the voltage, causing the gain-controlled amplifier 12 is controlled.

Also therefore, if the number of charge pumping circuits is halved the automatic gain control carried out be, with the loop gain in the AGC reinforcement loop is made variable.

27 Fig. 10 is a block diagram showing a charge pump type phase-shift circuit type D / A converter 7 in 24 illustrated. 28 is a circuit diagram of the charge pump circuit in 27 ,

As in 27 shown is a multiplexer 77 designed to have 7-bit inputs and 4-bit outputs. The phase error signal consists of 8 bits, of which 7 bits are used as data bits, and one bit is used as a sign bit. The sign bit indicates the polarity of the 7-bit data bits. The seven data bits and one bit select signal are put into the multiplexer 77 entered. The multiplexer 77 selects the high or low 4 bits in accordance with the bit select signal.

The outputs of the multiplexer 77 , the bit select signal and the sign bit become four charge pump circuits 78-1 to 78-4 entered. Then, when the bit select signal indicates the initial pull, the corresponding charge pump cycles enter 78-1 to 78-4 the currents of 128 mA, 64 mA, 32 mA, 16 mA in accordance with the polarity of the sign bit off. When the bit select signal indicates the station operation, the individual charge pump circuits give 78-1 to 78-4 Further, the currents of 8 mA, 4 mA, 2 mA, 1 mA in accordance with the polarity of the sign bit.

That is, at the initial pull, the multiplexer selects 77 high-quality 4-bit, in station operation low-order 4-bit. Each charge pump circuit 78-1 to 78-4 Also, in the station operation, outputs the current corresponding to the weight of the low-order 4 bits, but at the initial drawing, outputs the current corresponding to the weight of the high-quality 4 bits, which is 16 times the above.

As in 28 illustrates each charge pump circuit contains 78-1 to 78-4 an AND gate 780 for picking up the AND of the sign bit with the data bit, an inverter circuit 781 for inverting the sign bit, and an AND gate 782 for receiving the AND of an output of the inverter circuit 781 with the data bit.

Furthermore, each charge pump circuit has 78-1 to 78-4 a first constant current source 783 for flowing the current in one direction, a first circuit circuit 784 passing through an output of the AND gate 780 is opened and closed, a second constant current source 786 for flowing the current in one direction, and a second circuit 785 passing through an output of the AND gate 782 opened and closed.

The individual power sources 783 . 786 are through the circuit circle 784 . 785 connected in series. Then is a loop filter constructed of a capacitor 75 with the midpoint between the power sources 783 . 786 connected. A power circuit 787 supplies a reference current of the current sources 783 . 786 in accordance with the bit select signal. When the bit select signal indicates the pull operation, this power circuit controls 787 the power sources 783 . 786 so that a current that is 16 times that when the bit selection signal indicates the station operation flows.

Accordingly, when the sign bit indicates positive ([1]), the circuit circuit becomes 784 from the AND gate 780 output data bit is opened and closed, with the result that the current from the first power source 783 flows. If, on the other hand, the sign bit indicates negative ([0]), the circuit becomes 785 from the AND gate 782 output data bit is opened and closed, with the result that the current in the direction of the second power source 786 flows. In this way, the current is obtained which corresponds to the polarity of the error signal.

Next, the operation of the phase synchronization circuit 7 explained. During non-read processing from the magnetic disk is the multiplexer circuit 73 with the frequency comparator 72 connected. Through this connection, the voltage control oscillator generates 76 one clock in synchronism with the frequency of the servo signal.

During the read processing from the magnetic disk is the multiplexer circuit 73 however, with the phase detector 71 connected. This connection creates the voltage controlled oscillator 76 the clock resulting from the phase error of the sampling output of the digital equalizer 15 is controlled. At this time, the bit select signal first indicates a pull mode of [LOW].

The multiplexer 77 This selects the high quality 4 bits from the 7-bit phase error signal outputs. Furthermore, each charge pump circuit 78-1 to 78-4 the current corresponding to the weight of the high quality 4 bits.

Accordingly, the high-quality 4-bits of the 7-bit digitial error values are converted by the D / A converter 74 converted by the type of a charge pump in the analog current size, and then through the filter 75 converted into a voltage, causing the gain-controlled oscillator 76 is controlled.

Upon completion of this drag operation, the bit select signal indicates a [HIGH] station operation. This will select the multiplexer 77 the low order 4 bits out of the 7 bit phase error signals. Each charge pump circuit 78-1 to 78-4 also outputs the current corresponding to the weight of the lower 4 bits.

With this processing, the least significant 4 bits of the 7-bit digitial error values are obtained by the D / A converter 74 be converted by the type of a charge pump in the analog current size, through the filter 75 converted into a voltage, whereby the gain control oscillator 76 is controlled.

When next another example of the phase synchronization circuit is given.

If in the partial-response regeneration system, the phase of the synchronous clock is shifted, occurs a demodulation error of the output signal of a recording channel. Therefore, it is necessary that the phase the synchronous clock is corrected on the basis of a phase error, that of an equalized amplitude value and a determination value is detected.

Usually becomes the phase difference in the read processing in the form of a voltage difference and, therefore, a smoothing filter involves use a gm amplifier filter, which is defined as a voltage control type filter. This gm amplifier filter is a filter having such a construction that a plurality of gm amplifiers are connected in series, and a capacitor is in the feedback loop intended.

Of the Reason why this voltage control filter from the gm amplifier filter is that the gm amplifier is a Lock frequency can make variable. This is because of the control the blocking frequency per zone on the magnetic disk advantageous.

The gm amplifier filter has a problem in that the configuration thereof is complicated and the scale the circuit increases. Furthermore leads the complicated configuration on the problem of price increase.

Now is a phase synchronization circuit to simplify the Circuit configuration of the voltage control filter shown.

29 is a block diagram of the phase synchronization circuit. 30 is a block diagram of a voltage difference arithmetic unit in FIG 29 , 31 is a timing diagram in non-read processing in 29 , 32 is a timing diagram in the reading processing in 29 ,

With reference to 29 is an external oscillator 80 constructed from a crystal oscillator. Then the external oscillator generates 80 Bars with a fixed period. A frequency phase comparator 81 compares an output clock of the external oscillator 80 with a synchronous clock of the voltage control oscillator 76 , and outputs a signal (phase difference signal) corresponding to a phase difference. A phase / voltage converter 82 converts this from the frequency phase comparator 81 transmitted phase difference signal to a voltage.

The partial equalizer 15 is constructed of the cosine equalizer as stated above. A voltage difference arithmetic unit 79 comprises a sampling circuit consisting of an A / D converter and an in 30 shown phase difference arithmetic circuit consists of. The voltage difference arithmetic unit 79 then causes the sampling circuit to sample the signal after equalization by the synchronous clock. The voltage difference arithmetic unit 79 calculates a voltage signal indicative of a phase difference from an amplitude of the sampled signal.

A voltage control filter 77 Disables a high frequency component of the voltage signal from the voltage difference arithmetic unit 79 or a phase / voltage converter 82 is transmitted, and is constructed of an integral circuit. This integral circuit consists of an input resistor R1, a current setting resistor R2 connected between the input resistor R1 and ground, and a capacitor C. Accordingly, this integral circuit constitutes a known integration-type passive filter.

The voltage controlled oscillator 76 generates the synchronous clock with a phase corresponding to the voltage. This synchronous clock is in the frequency phase comparator 81 and the voltage difference arithmetic unit 79 entered. A circuit 83 when reading through the head, connects the voltage control filter 77 with the voltage difference arithmetic unit 79 , however, connects the voltage control filter when not read by the head 77 with the phase / voltage converter 82 ,

The phase difference arithmetic circuit of the voltage difference arithmetic unit will be explained with reference to FIG 30 explained.

A ternary determination circuit 790 compares the sample Y (n) with the two slice levels S1, S2, and makes a determination in terms of the determination values X (n) of [+1], [0], [-1]. A first delay element 791 causes a sample delay of the sample Y (n), thereby obtaining Y (n-1). A second delay element 792 causes the one sample delay of the determination value X (n), whereby X (n-1) is obtained. A first multiplier 793 multiplies Y (n - 1) by X (n). A second multiplier 794 multiplies Y (n) by X (n - 1). An adder 795 subtracts an output Y (n) * X (n-1) of the second multiplier 794 from an output Y (n-1) X (n) of the first multiplier 793 , whereby a phase difference Δτ (n) is obtained.

Next is the operation of the circuit in 29 described. When the head reads a signal on the magnetic disk medium, the circuit circuit connects 83 the voltage control filter 77 with the voltage difference arithmetic unit 79 , Then a PLL loop of the partial equalizer 15 , the voltage difference arithmetic unit 79 , the voltage control filter 77 and the voltage controlled oscillator 76 educated.

In this PLL loop, in the read processing, the waveform of the signal read from the disk medium is from the partial equalizer 15 equalized, which serves as an equalizer for the partial response regeneration. As in 32 illustrates, the waveform of the equalized signal of a sample in the A / D converter of the voltage difference arithmetic unit 79 at a timing of the synchronous clock of the voltage control oscillator 76 subjected. The ternary determination circuit 790 performs a ternary determination with respect to the sample Y (n).

As in 32 2, a difference Δa between the amplitude of the sample Y (n) and a reference voltage a is proportional to a phase difference ΔT (n). The phase difference arithmetic circuit of the voltage difference arithmetic unit 79 , in the 30 is shown calculates the phase difference Δτ (n) in the formula given above. That is, the adder 795 obtains a difference between the output Y (n-1) * X (n) of the first multiplier 793 and the output Y (n) x (n-1) of the second multiplier 794 , The voltage output Δτ (n) of this adder 795 is Y (n-1) X (n) -Y (n) x (n-1).

The voltage difference arithmetic unit 79 smoothes this voltage signal using the capacitor C. Then, the voltage controlled oscillator 76 through an output of the voltage control filter 77 controlled. With this processing, the output is used as the voltage controlled oscillator 76 defined clock synchronized with the read signal.

However, in a processing other than the read processing, the circuit circuit connects 83 the voltage control filter 77 with the phase / voltage converter 82 , This will cause a PLL loop of the external oscillator 80 , the phase comparator 81 , the phase / voltage converter 82 , the voltage control filter 77 and the voltage control oscillator 76 educated.

This operation is with reference to 31 explained. In the frequency phase comparator 81 become an output of the external oscillator 80 and an output of the voltage controlled oscillator 76 entered. The frequency phase comparator 81 outputs a signal that is the phase difference between the output of the external oscillator 80 and the output of the voltage controlled oscillator 76 equivalent. The phase / voltage converter 82 outputs a voltage signal corresponding to the phase difference signal thereof. Then this voltage is passed through the voltage control filter 77 smoothed, reducing the voltage controlled oscillator 76 is controlled.

In this way, the voltage control filter 77 is constructed of the passive filter consisting of the integral circuit, and therefore the voltage control filter can be easily constructed at a low cost. Also, a difference between the frequency characteristics in the radial direction of the magnetic disk to some extent may be from the voltage-controlled oscillator 76 be absorbed.

According to this embodiment, the partial equalizer has been explained as having the analog output. As in 1 however, the A / D converter is provided before the cosine equalizer and, moreover, the cosine can be constructed more equal to a digital equalizer. In this case, the A / D converter is the voltage difference arithmetic unit 79 not mandatory.

As explained above the voltage control filter of the phase synchronization circuit is off the integration-type filter, resulting in a simplified configuration leads. Further, the integration-type filter is used, and therefore a cheap construction can be provided.

When next an explanation is given a modified example of the phase synchronization circuit, when the MR head is inserted.

In the phase synchronization circuit, the phase error value Δτ (n) is defined by the following comparison expression: Δτ (n) = Y (n) × X (n-1) -Y (n-1) × X (n).

Then the voltage control oscillator generates such a synchronous clock, that this Phase error value Δτ (n) zero becomes.

As in 33 1, as compared with a phase synchronous state, the non-phase asynchronous state is as follows. That is, as shown in Example (1), when the determination value of two consecutive data values (1, 1) is, the above comparison expression defines the phase error value Δτ (n) as follows: Δτ (n) = Y (n) x 1 -Y (n-1) x 1 = Y (n) -Y (n-1).

It that is a level difference in the data for individual determination as [1] detected in the form of a phase error.

Similarly, as shown in Example (2), when the determination value of two consecutive data values is (-1, 0), the phase error value Δτ (n) is expressed as follows: Δτ (n) = Y (n) x -1 - Y (n-1) x 0 = -Y (n).

This time that is the data level in the determination as [0] in the form of the phase error detected.

Therefore becomes according to the phase synchronization system the phase error between the data and the clock is not a time zone, but detected as a level variation. Then this phase error becomes Phase synchronization circuit fed back, whereby the phase synchronization control carried out becomes.

When the regeneration of the magnetic disk medium involves the use of the MR head, as in FIG 34 In addition, a positive / negative asymmetry of the read waveform is generated. This waveform asymmetry thus occurs in the form of an offset error ΔE when the determination value is [0]. In example (3) in 34 For example, the phase error value Δτ (n) is given by: Δτ (n) = Y (n) × 1 -Y (n-1) × 0 = Y (n) = ΔE.

Similarly, in Example (4) in 34 the phase error value Δτ (n) expressed as: Δτ (n) = Y (n) × 0 -Y (n-1) × 1 = Y (n-1) = ΔE.

Accordingly, it follows, as in 34 have shown that even in a state where the data is synchronous with the clock, the phase error value ΔE in addition to the original error with respect to the data containing [0].

Out that's why synchronization with the data is lost after that and this can be a reason for be the generation of a demodulation error.

Now For example, a phase synchronization circuit is shown to cause a phase correction error to avoid an asymmetry of the read waveform when the MR head is used as a read head.

35 Fig. 10 is a block diagram showing another modified example of the phase synchronization circuit. 36 is a circuit diagram of the error detection circuit in 35 , 37 is a time diagram in the construction in 35 ,

With reference to 35 are the same elements as the ones in 1 marked with the same reference numbers. As in 35 As shown, the phase synchronization circuit includes a binary / ternary determination unit 84 , a phase comparator 85 and a voltage controlled oscillator (VCO) 76 , The binary / ternary determination unit 84 performs a binary determination of the amplitude value Yn in the gap pattern of the read signal, and then makes a ternary determination of the amplitude value Yn in the data pattern. The phase comparator 85 calculates the phase error value Δτ (n) from the amplitude value Yn and the determination value Xn.

The error detection circuit 86 detects that the read signal is in a measurement range of the slit pattern, a binary / ternary determination switch signal, and a data read signal. The error detection circuit 86 Detects the offset error value ΔE from the amplitude value Y (n) and the determination value X (n). Then the error detection circuit stops 86 the offset error value ΔE, and outputs the offset error value ΔE only when the determination value X (n) is [0].

A subtractor 87 subtracts the offset error value ΔE from the amplitude value Y (n), and outputs a subtracted output (Yn-ΔE) to the phase comparator 85 out.

The error detection circuit 86 becomes with reference to 36 explained.

As in 36 illustrates decoding a decoder 820 the determination value X (n), and outputs a decode signal S1. When the determination value X (n) is [0], the decode signal S1 produces an output which assumes a low level. In other cases, the decode signal S1 produces an output which assumes a high level.

An AND gate 821 only outputs a VCO clock as the clock S2 when the binary / ternary decision switching signal output from the unillustrated control circuit is high, the data read signal is high, and the decode signal S1 is at the low level. That is, the AND gate 821 only outputs the clock when the determination value X (n) in the measuring range of the slit pattern is zero.

A shift register 822 is made up of 4-stage shift registers 822a to 822d constructed. The above-described clocks are placed in the 4-stage shift registers 822a to 822d entered. The most significant bit of the amplitude value Y (n) is put into the shift register 822a the first stage of the 4-stage shift registers 822a to 822d entered.

inverter circuits 823a to 823d invert outputs S3 to S6 of the corresponding shift register 822a to 822d , An AND gate 824a takes the AND of the outputs of the individual inverter circuits 823a to 823d on. An AND gate 824b takes the AND of the outputs S3 to S6 of the shift registers 822a to 822d on. An OR gate 825 takes the OR (Logic Sum) of the outputs of the AND gate 824a . 824b on.

A subtractor 826 subtracts a center value of the A / D converter 14 from the amplitude value Y (n). A register 827 holds an output of the subtractor 826 in response to a signal S7 of the AND gate 825 ,

An inverter circuit 828 inverts the decoder output S1 of the decoder 820 , An AND gate 829 gives the offset error value ΔE of the register 827 in accordance with an output of the inverter circuit 828 out.

At the first use, the operation is in construction in 35 explained.

A DC component of the read signal of the read head is blocked by an AC coupling made up of a capacitor of the head IC circuit 11 is constructed. A gain control amplifier 12 under the equalizer filters 12 . 13 and the gain control amplifier gives the input to the Read signal a gain, and outputs this.

Further, the equalizer filter shows 13 the (1 + D) characteristic, and equalizes an output of the gain control amplifier. The next effect is the A / D converter 14 sampling, when nT + τ, by the synchronous clock, and outputs a digital sample. The cosine equalizer 15 automatically equalizes the digital sample in accordance with the partial response characteristic in the radial direction of the disc and outputs the amplitude value Y (n).

On the other hand, as in 37 11 illustrates the gap pattern area formed before the data pattern area, an area in which the determination values [1], [-1] occur alternately. Here leads the binary / ternary determination unit 84 a binary determination by. Then the phase comparator calculates 85 a phase error in the above-mentioned comparison expression in accordance with this binary determination value and the amplitude value, whereby the voltage-controlled oscillator 76 is controlled. With this processing in the gap pattern, the clock phase is synchronized.

If these determination values [1], [-1] occur alternately in the gap pattern area, the offset error value occurs of the MR head does not open. On the other hand occurs in the data pattern area the determination value [0], and therefore the offset error value seen. In the data pattern area, the measurement of the displacement error is sufficient not and therefore an offset error quantity is measured in the gap pattern.

For this purpose, a ternary measuring range is formed in the gap pattern region. This measuring range is provided after the above binary range. That is, after performing the binary phase synchronization, the offset error is to be detected. A pattern containing a sequence of a plurality of determination values [0] is formed in this measurement area. As in 37 10, here, such a pattern is used that when two determination data values [0] succeed each other, two determination data values [-1] follow each other, and further two determination data values [0] follow each other.

As As described above, in providing the sequence of determination values [0] containing area possible the measurement of the displacement error on the basis of the amplitude value, which is also the determination value [0]. Thereby the offset error can be detected accurately.

Accordingly, the error detection circuit detects 86 the measurement range from the binary / ternary detection switching signal and the data read signal that arrives to take the high level from the header of the data pattern. Then the error detection circuit calculates 86 the offset error value Δ E from the amplitude value Y (n) when the determination value X (n) is [0], and holds this value.

Then, in the data pattern area, in accordance with the fact that the determination value X (n) is [0], the error detection circuit 86 this offset error value ΔE to the subtracter 87 out. As in 37 shown, subtracted. hence the subtractor 87 the offset error value ΔE from the amplitude value Y (n) only when the determination value is [0].

On the other hand, when the determination value Y (n) is [1] or [-1], the error detection circuit outputs 86 does not satisfy the offset error value, and hence the subtractor 87 the amplitude value Y (n) as it is. That is, the subtracter serves as a mere buffer.

In this way, the amplitude value Y (n) from which the offset error value ΔE of the MR head is subtracted is input to the phase comparator 85 entered. With this processing performs the phase comparator 85 the calculation based on the above phase error calculation formula, whereby the phase error Δτ (n) is calculated. For this reason, the voltage control oscillator becomes 76 controlled by this phase error, and therefore generates the clock phase synchronization with the input signal.

The operation in construction in 36 is described.

The decoder 820 decodes the determination value X (n), and when the determination value X (n) is [0], generates a low level output. Further, the binary / ternary determination switching signal assumes the high level from the starting point of the gap pattern measuring range. The data read signal also assumes the low level from the start point of the data pattern area.

The AND gate 821 only outputs the VCO clock as the clock S2 when the binary / ternary decision switching signal is at the high level, the data read signal is at the high level, and the decoding signal S1 is at the low level. That is, the AND gate 821 only outputs the clock S2 when the determination value X (n) in the measuring range of the slit pattern is zero.

Next, the most significant bit of the amplitude value Y (n) becomes the shift register 822a the first stage of the 4-stage shift registers 822a to 822d entered. Accordingly, the most significant bits of the amplitude value Y (n) when the determination value X (n) is [0], sequentially in the shift registers 822a to 822d set. Here, the MSB of the amplitude value Y (n) [1] is when the amplitude value is not smaller than a center voltage of the A / D converter 14 , If the amplitude value, however, is less than the center voltage of the A / D converter 14 , is the MSB [0].

As in 37 Fig. 14 illustrates that when all the amplitude values Y (n) of the determination values X (n) of [0] in the measurement range are the center voltage or greater, the outputs S3 to S6 of the corresponding flip-flops accordingly take 822a to 822d the high level. Therefore, the output S7 of the AND gate takes 825 the high level. This keeps the register 827 the offset error value ΔE obtained by subtracting the center voltage from the amplitude value Y (n) of the subtractor 826 is obtained.

If all the amplitude values Y (n) of the determination values X (n) of [0] in the measuring range are smaller than the center voltage, here take the outputs S3 to S6 of the corresponding flip-flops 822a to 822d the low level. Therefore, the output S7 of the AND gate takes 825 the high level. This keeps the register 827 the offset error value ΔE obtained by subtracting the center voltage from the amplitude value Y (n) of the subtractor 826 is obtained.

As explained above becomes both in the case where all the amplitude values Y (n) of the determination values X (n) of [0] in the measuring range the center voltage is greater or greater than also in the case where all these amplitude values Y (n) of the determination values smaller than the center voltage, the error measured. This is due to the fact that depending on from the characteristics of the MR head the displacement error the Center voltage is or larger and smaller as the center voltage.

Further are the cases where all the amplitude values Y (n) of the determination values X (n) of [0] the Center voltage is greater and greater less than the center voltage, set in the measuring range. The reason for that lies in the detection of the stable displacement value in the gap pattern region.

On the other hand, the decoder output S1 becomes the decoder 820 from the inverter circuit 28 inverted, and into the AND gate 829 entered. Accordingly, the AND gate 829 the offset error value ΔE of the register 827 only to the subtractor 87 if the determination value is X (n) [0]. The AND gate 829 also returns [0] if the determination value is X (n) [1] or [-1].

As in 37 Therefore, the subtractor subtracts 87 the offset error value ΔE from the amplitude value Y (n) only when the determination value X (n) is [0].

On the other hand, when the determination value X (n) is [1] or [-1], the error detection circuit outputs 86 [0], and therefore gives the subtractor 87 the amplitude value Y (n) as it is. That is, the subtractor 87 serves as a mere buffer.

Therefore becomes the displacement amount of the MR head detected from the slit pattern and from the amplitude value of the data pattern subtracted. That's why it's possible the VCO timing error due to the MR head own waveform asymmetry to reduce. Furthermore, all circuits are logic circuits constructed and therefore for a transformation in LSI suitable.

As As described above, the displacement amount of the MR head is detected from the slit pattern and subtracted from the amplitude value of the data pattern. Therefore, can the VCO timing error due to the MR head own waveform asymmetry reduced become. Furthermore, all circuits are constructed of logic circuits and therefore for a transformation in LSI suitable.

Even though The present invention has been described with reference to embodiments, the embodiments in various forms within the scope of the present Invention be modified.

Claims (1)

A maximum likelihood decoder in a PRML regeneration apparatus for regenerating a signal read from a storage medium by a head which is digitally conditioned to obtain a sequence of signal values (Y _n ) indicative of ternary regenerative signals having upper and lower threshold levels with the upper and lower threshold levels being adjustable, with a ternary determining circuit ( 1 . 14 . 15A ) for deriving the ternary regenerative signals by comparing the read signal with upper and lower threshold levels, the upper and lower threshold levels being changed depending on the result of the comparison, which ternary determining circuit is a memory ( 11 . 15A ), which contains a correspondence table for upper and lower threshold levels corresponding to the result of comparison, of an input circuit ( 55 . 502 . 18 ) for converting the ternary regenerative signals into binary data, a data buffer ( 2 . 14 ) for holding the binary data from the input circuit, and a correction circuit ( 3 . 14 ) for detecting a consecutivity of each bit signal (DDt 0, DDt 1) of the ternary regenerative signals and for correcting the binary data, each in the data buffer ( 2 ), by the detected result, characterized in that the correction circuit ( 3 ) comprises: a first consecutive detector ( 600 . 601 . 602 . 603 ) for detecting a consecutivity of a first bit signal (DDt 0) of the ternary regenerative signals, a second consecutive detector ( 6040 for detecting a consecutive of a second bit signal (DDt 1) of the ternary regenerative signals, and an OR logic circuit ( 605 ) for an OR operation of the outputs of the first and second consecutive detectors.