JPH0314251B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a circuit for extracting a clock signal from a received signal sequence in a digital transmission system using biphase codes.

(Prior art and its problems) Biphasic codes (also called Manchiesta codes) () Because the code sequence itself does not have a DC component, error-free code transmission is possible even when using a transmission line with low-frequency cutoff characteristics. , (2) Encoding and decoding are extremely simple, so it is widely used mainly for data transmission. Figure 1 shows the conversion rule for biphase codes, in which the original data series is converted to the clock frequency
f ₀ When expressed as a NRZ (non-return-to-zero) pulse, the “1” of this original data series is expressed as an NRZ pulse “10” with a clock frequency of 2f ₀ , and the “0” of the original data series is expressed as an NRZ pulse with a clock frequency of 2f 0. This converts the NRZ pulse of ₀ to “01” (of course, it converts it to “1”).
→ “01”, “0” → “10” is the same). FIG. 2 shows an example in which an original data sequence is encoded using this coding rule.

Figure 3 shows an example of a circuit that biphasically encodes a binary NRZ code, and 301 is an NRZ
Sign input 302 and clock signal (frequency f ₀ ) 30
This is an exclusive OR circuit that calculates the exclusive OR of 3. By appropriately selecting the phase relationship between the two input signals 302 and 303, the exclusive OR circuit 301
A biphase encoded signal is obtained as the output signal 304 of . Flip-flop circuit 306
is for shaping the output signal 304 and is driven by the clock signal 308 multiplied by the frequency 2f ₀ twice by the frequency multiplier circuit 307 to obtain the final biphase code output 305.

FIG. 4 is an example of a decoding circuit that converts the biphase code into the original NRZ code. 401 is a flip-flop circuit, and by adding a biphasically encoded input signal 402 and a clock signal 403 of frequency f ₀ in an appropriate phase relationship, a signal decoded to the original NRZ code is obtained as an output signal 404. It will be done.

As is clear from the examples shown in FIGS. 3 and 4, encoding and decoding of biphasic codes can be realized with extremely simple circuits. As can be seen from the correspondence between the original data and the biphase code in Figure 2, the phase of the clock input in the decoding circuit in Figure 4 is
A 180° shift completely reverses the polarity of the decoded output 404. In order to avoid such inconvenience, the binary NRZ code (302 in Figure 3) before biphase encoding is differentially encoded in advance, and the biphasically decoded signal (302 in Figure 4) is encoded differentially.
04) can be reversely differentially decoded.

As can be seen from the example of the decoding circuit shown in FIG. 4, a clock signal is required to return the biphase code to the original NRZ code. In a data transmission system, an encoding circuit as shown in Fig. 3 is placed in a transmitting device, a decoding circuit as shown in Fig. 4 is placed in a receiving device, and the transmitting device and receiving device are connected by a transmission path. They are usually placed at long distances. Therefore, rather than transmitting the data signal and the clock signal separately, it is preferable to transmit only the data signal and extract the clock signal from the data signal itself. The present invention provides a novel circuit for such clock extraction.

A known method for extracting a clock signal from a biphase code is the method described in PCT Application No. WO82/02985, published on September 2, 1982. As shown in FIG. 5, this is done by first decoding a biphase encoded input signal 501 into an NRZ code in a flip-flop circuit 502, and adding this decoded output 503 and an extraction clock signal 504 to an exclusive OR circuit 505. A biphase code 506 is obtained again. Since the phase of this biphasic code 506 changes depending on the phase of the extraction clock 504, the phase difference between the phase of the biphasic code 506 and the input biphasic code 501 is detected by a phase comparator 50.
7, and the output signal is passed through a low frequency currency filter 5.
08 and then applied to the voltage controlled oscillator 509. This forms a phase-locked loop, and the clock signal 5 is output as the output of the voltage controlled oscillator 509.
04 is obtained. The phase comparator 507, low-pass filter 508, and voltage-controlled oscillator 509 constitute a so-called phase-locked oscillator 510.

This method has the advantage of being able to perform biphase decoding and timing extraction at the same time, but on the other hand, it is a so-called decision feedback method in which the input biphasic code (501 in Figure 5) is identified and judged using the extracted clock (504 in Figure 5). Because of this configuration, during initial operation (for example, when power is turned on) or when transmission line errors occur frequently, phase synchronization may be lost or lock-in may become impossible, making stable clock extraction impossible. There were flaws.

(Objective of the Invention) The present invention has been made in view of the above drawbacks of the conventional clock extraction method, and an object of the present invention is to always perform stable clock extraction using a simple method.

(Structure of the Invention) According to the present invention, by detecting the sign change point of a biphase-encoded input signal, a change point detection signal is generated such that the binary state is alternately inverted at the sign change point. A biphasic code clock extraction circuit is obtained, which comprises a means for detecting a change point and an exclusive OR circuit for calculating an exclusive OR of the change point detection signal and the biphasically encoded input signal to generate a clock signal.

(Principle of the invention) The principle of the invention will be explained below with reference to the drawings. FIG. 6 is a diagram illustrating the principle of the clock extraction method of the present invention. In the figure, a is a biphasically encoded input signal, and shows the same code sequence as exemplified in FIG. Since the sign change points of this series are the points indicated by 601, 602, 603, 604, etc., these points are detected and 2
If a change point detection signal is created in which the value state is alternately inverted, the result will be as shown in Figure b. If this signal is exclusive-ORed with the input signal a, a clock signal as shown in FIG. 3c is obtained. Note that the change point detection signal may be a signal with the polarity inverted from the signal shown in FIG. In this case, the waveform shown in the figure e is obtained as the clock signal obtained by exclusive ORing with the input signal. This is a clock signal with the polarity inverted (or with a phase shifted by 180°) of the clock signal shown in FIG. In this way, there may be two types of phase states in the extracted clock signal depending on the initial state of operation, but as mentioned above, by making the data signal differential before biphase encoding, this can be achieved. Even if there is such uncertainty in the polarity of the clock signal, the original data can be reproduced without error.

As described above, the system of the present invention is extremely simple and does not have a decision feedback loop, so it always operates stably even during initial operation or when the transmission path is bad. Note that this method is realized using only simple logical operations, so if the data transmission speed is extremely high or the input waveform is highly distorted due to the transmission path characteristics, distortion or jitter may occur in the extracted timing waveform. There is sex. In such a case, jitter and waveform distortion can be removed by applying the extracted timing signal to the phase synchronized oscillator. In this case, unlike the conventional example shown in FIG. 5, the phase synchronized oscillator is completely connected to the output of the timing extraction circuit, so that the operation will not become unstable.

(Embodiment) FIG. 7 shows the configuration of a circuit embodying the clock extraction method of the present invention. In the same figure, 701 is “1” of the input signal 702 which is biphasically encoded →
A first sign change detection circuit that detects a sign change of “0”; 703 is a second sign change detection circuit that detects a sign change of “0” → “1” of the biphasically encoded input signal 702; 706 is the first
708 is a set/reset type flip-flop circuit in which one output signal (for example, 704) of the second sign change detection circuits 701 and 703 is used as a set input signal, and the other output signal (for example, 705) is used as a reset input signal. Exclusive OR circuits are shown which input the output signal 707 of the set/reset type flip-flop circuit and the biphasically encoded input signal and perform an exclusive OR operation. Assuming that the input signal 702 is the same signal as shown in FIG. 6a as shown in FIG. 8a,
The output signals 704 and 705 of the first and second sign change detection circuits shown in FIG. 7 become as shown in FIGS. 8b and 8c, respectively. Therefore, the output signal 707 of the set-reset type flip-flop circuit becomes as shown in FIG. The changing point detection signal as shown in FIG.
01,703 and 706. Since the signal in FIG. 8d is the same as the signal in FIG. 6d, the clock signal shown in FIG. 8e is obtained as the output signal 709 of the exclusive OR circuit 708, similar to that in FIG. 6e. Note that the sign change detection circuits 701 and 702 in FIG. 7 can be constructed by simple circuits such as those shown in FIG. 9 901 and 902, for example. In the same figure, 90
3 is an inverter, 904 and 905 are delay circuits with a delay time of T/2 (T=1/f ₀ ), and 906 and 907 are AND circuits. In the figure, if a biphase signal is applied to the input terminal 908, the output points 909 and 910 are outputted to the output points 704 and 70 in FIG.
An output signal corresponding to 5 is obtained.

As described above, according to the circuit of the present invention, it is possible to obtain a biphase code clock extraction circuit that always operates stably with a simple configuration. Note that the circuit of the present invention can be configured only with logic circuit elements as shown in FIGS. 7 and 9, so when used in a relatively low-speed region where the logic circuit operates close to ideal, , the basic configuration shown in FIG. 7 alone is sufficient for use. However, when operating in a high-speed region where logic circuit malfunctions (jitter, waveform deterioration, etc.) cannot be ignored, or even when the logic circuit is ideal, the input biphase signal itself may be subject to large waveform distortion due to the transmission path. If so, a jitter-free clock signal will no longer be obtained as the output signal 709 of the circuit of FIG. In such a case, for example, by continuously connecting a well-known phase-locked circuit 1005 as shown in FIG. 10 behind the circuit of FIG. 7, a good jitter-free output signal 1001 can be obtained. A clock signal can be obtained. In this case, the feedback loop of the phase locked circuit is independent of the clock extraction circuit, so the operation is always stable. 1 in Figure 10
002 is a phase comparator, 1003 is a low pass filter, and 1004 is a voltage controlled oscillator.

Note that instead of the phase-locked circuit shown in FIG. ₁₀ , a highly selective narrow band filter (for example, LC filter, cavity resonator,
It is also possible to remove jitter and obtain a good clock signal using a surface acoustic wave filter (surface acoustic wave filter, etc.).

FIG. 11 shows the configuration of another circuit embodying the clock extraction method of the present invention. In the same figure, 1101
11 is a sign change detection circuit that detects a sign change point of the biphase-encoded input signal 1102;
03 is the output signal 1104 of this sign change detection circuit
1105 is an exclusive OR circuit which inputs the output signal 1106 of this binary counter and the biphasically encoded input signal 1102 and performs an exclusive OR operation. Binary counter 1103 can be easily obtained, for example, by feeding back the output of a delay type flip-flop circuit to the D input and adding a signal as the C input, as shown in the figure. Further, the sign change detection circuit 1101 is configured to detect, for example, the 12th
As shown in the figure, this can be easily obtained by connecting an OR circuit 1201 to the two output points 909 and 910 of the circuit in FIG.

FIG. 13 explains the operation of the circuit shown in FIG. 11, taking as an example the same input signal 1102 as shown in FIG. 6a or FIG. 8a, as shown in FIG. 11a. At this time, the code detection circuit 1
As shown in FIG. 12, the output signal 1104 of 101 is the logical sum of the output of the "1" → "0" sign change detection circuit and the output of the "0" → "1" sign change detection circuit. , that is, the logical sum of waveforms b and c in FIG. 8 results in a waveform as shown in FIG. 13b. Therefore, such a signal is
The output signal 1106 when applied to the binary counter 1103 shown in the figure becomes as shown in FIG. 13c. 13th
A change point detection signal as shown in FIG. c is obtained by circuits 1101 and 1103. Figure 13c is Figure 8d
Since the waveform is exactly the same as that of FIG. 13, the clock signal output of FIG. 13d is obtained as the output signal after exclusive ORing with the input biphase code, similar to that of FIG. 8e. In this manner, the circuit shown in FIG. 11 has an extremely simple configuration similar to the circuit shown in FIG. 7, and can always stably extract the clock signal from the biphase code.
If a phase synchronization circuit or various narrowband filters are connected behind this circuit, an even better clock signal with almost no jitter can be obtained, just as in the case of the circuit shown in FIG.

In either case of the circuit shown in FIG. 7 or FIG. 11, depending on the initial state of the flip-flop circuit (706 in FIG. 7 or 1103 in FIG. 11), the phase of the clock signal changes to 2 as explained in FIG. (For example, if the power is turned off and turned on again during operation, the phase of the clock signal may change by 180 degrees before and after the power is turned off.)
However, as mentioned above, by differentially encoding the biphasic code in advance, the disadvantages associated with such clock phase inversion (data polarity after identification is completely inverted, resulting in all output data being erroneous) can be avoided. can be avoided.

(Effects of the Invention) As described in detail above, according to the circuit of the present invention, clock signal extraction from a biphase code can be realized with an extremely simple configuration, and its operation can always be kept stable. can. Since the circuit of the present invention has logic circuit elements as its main components, it is easy to construct the entire circuit as an integrated circuit, and it can be widely used in various data transmission devices.

[Brief explanation of the drawing]

Figure 1 is a diagram showing the conversion rules for biphasic codes;
Fig. 2 shows an example of encoding using the biphasic coding rule, Fig. 3 shows an example of a biphasic encoding circuit, Fig. 4 shows an example of a biphasic decoding circuit, and Fig. 5 shows a conventional clock extraction method. figure,
6A to 6E are diagrams explaining the principle of the method of the present invention, FIG. 7 is a diagram showing the configuration of the clock extraction circuit of the present invention, and FIGS. 8A to 8E are diagrams showing waveforms of various parts in the circuit of FIG. 9 is a diagram showing an example of the configuration of a sign change detection circuit, FIG. 10 is a diagram showing a phase synchronization circuit, FIG. 11 is a diagram showing another configuration of the clock extraction circuit of the present invention, and FIG. The figure shows a configuration example of a sign change detection circuit, and FIGS. 13a to 13d are diagrams showing waveforms of various parts in the circuit of FIG. 11. In the figure, 301 is an exclusive OR circuit, 302
is the NRZ code input, 303 is the clock signal, 30
4 is an output signal, 305 is a biphase output signal,
306 is a flip-flop circuit, 307 is a frequency multiplier circuit, 308 is a clock signal, 401 is a flip-flop circuit, 402 is an input signal, 403
is a clock signal, 404 is an output signal, 501 is an input signal, 502 is a flip-flop circuit, 503
is the decoded output, 504 is the extracted clock signal, 505
is an exclusive OR circuit, 506 is a biphase code, 507 is a phase comparator, 508 is a low pass filter, 509 is a voltage controlled oscillator, 510 is a phase synchronized oscillator, 601, 602, 603 and 604
701 is the first sign change detection circuit, 702 is the input signal, 703 is the second sign change detection circuit, 704 and 705 are the output signals, 706 is the set/reset type flip-flop circuit, and 707 is the output. signal, 708 is an exclusive OR circuit, 709 is an output signal, 901, 902 is a sign change detection circuit, 903 is an inverter, 904,
905 is a delay circuit, 906 and 907 are AND circuits, 908 is an input terminal, 909 and 910 are output points, 1001 is an output signal, 1002 is a phase comparator, 1003 is a low-pass filter, 1004 is a voltage controlled oscillator, 1005 is a phase-locked circuit, 110
1 is a sign change detection circuit, 1102 is an input signal, 1
103 is a binary counter, 1104 is an output signal, 1105 is an exclusive OR circuit, 1106 is an output signal, and 1201 is an OR circuit.

Claims (1)

[Scope of Claims] 1. Means for detecting a sign change point of a biphase-encoded input signal to generate a change point detection signal such that the binary state is alternately inverted at the sign change point; A biphasic code clock extraction circuit comprising an exclusive OR circuit that performs an exclusive OR of a change point detection signal and the biphasically encoded input signal to generate a clock signal. 2. The means includes a first sign change detection circuit that detects a sign change from "1" to "0" of the biphasically encoded input signal; a second sign change detection circuit for detecting a sign change of 1'';
and a set/reset type flip-flop circuit which uses one output signal of the second sign change detection circuit as a set input signal, the other output signal as a reset input signal, and outputs the change point detection signal. A biphasic code clock extraction circuit according to range 1. 3. The means includes a sign change detection circuit that detects a sign change point of the biphasically encoded input signal, and a binary counter that uses an output signal of the sign change detection circuit as an input signal and outputs the change point detection signal. A biphasic code clock extraction circuit according to claim 1 constructed.